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| proasic ? 3 handbook
proasic3 handbook table of contents low-power flash device handbooks introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i section i ? proasi c3 datasheet proasic3 flash family fpgas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i proasic3 device family overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1 proasic3 dc and switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 package pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1 section ii ? core architecture low-power flash technology and flash*freeze mode core architecture of igloo and proasic3 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 -1 low-power modes in actel proasic3/e fpgas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 global resources and clock conditioning global resources in actel low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 clock conditioning circuits in igloo and proasic3 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1 embedded memories flashrom in actel?s low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1 sram and fifo memories in actel's low- power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1 i/o descriptions and usage i/o structures in igloo and proasic3 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1 i/o software control in low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1 ddr for actel?s low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1 packaging and pin descriptions pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1 design migration migrating designs in proasic3 devices from higher-dens ity to mid-density devices . . . . . . . . . . .12-1 migrating designs from a3p250 to lower-logic-density devices . . . . . . . . . . . . . . . . . . . . . . . . . . .13-1 table of contents programming and security programming flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14-1 security in low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15-1 in-system programming (isp) of actel? s low-power flash devices using flashpro3 . . . . . . . . . . . . .16-1 microprocessor programming of actel?s low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . .17-1 boundary scan and ujtag boundary scan in low-power flash devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18-1 ujtag applications in actel?s low-power flash devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19-1 board-level requirements power-up/-down behavior of proasic3/e devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20- 1 proasic3/e sso and pin placement guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 metastability characterization report for actel flash fpgas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22-1 v1.0 i low-power flash device handbooks introduction low-power flash device handbooks introduction device handbooks contain all th e information available to help designers understand and use actel's devices. handbook chapters are groupe d into sections on th e website to simplify navigation. each chapter of the handbook can be viewed as an individual pdf file. at the top of the handbook web page, you will see a zip file for each product family. this file contains the complete device handbook. please re gister for product updates to be notified when a section of the handbook changes. versions device handbook chapters may have different version numbers. actel?s goal is to provide customers with the latest information in a timely matter. as a result, the handbook chapters will be updated independently of the handbook. categories in order to provide the latest information to desi gners, some datasheets are published before data has been fully characterized. datasheets are de signated as ?product brief,? ?advanced,? and ?production?. the definition of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) and contains general product information. this document give s an overview of specific device and family information. advanced this version contains initial estimated information based on simulation, ot her products, devices, or speed grades. this information can be used as estimates, but not for production. this label only applies to the dc and switching characteristics chapte r of the datasheet and will only be used when the data has not been fully characterized. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this do cument are subject to the expo rt administration regulations (ear). they could require an ap proved export license prior to export from the united states. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. part number and revision date part number 51700094-001-0 revised january 2008 section i ? proasic3 datasheet february 2008 i ? 2008 actel corporation proasic3 flash family fpgas with optional soft arm ? support features and benefits high capacity ? 15 k to 1 m system gates ? up to 144 kbits of true dual-port sram ? up to 300 user i/os reprogrammable flash technology ? 130-nm, 7-layer metal (6 copper), flash-based cmos process ? live at power-up (lapu) level 0 support ? single-chip solution ? retains programmed design when powered off high performance ? 350 mhz system performance ? 3.3 v, 66 mhz 64-bit pci ? in-system programming (isp) and security ? secure isp using on-chip 128-bit advanced encryption standard (aes) decryption (except arm ? -enabled proasic ? 3 devices) via jtag (ieee 1532?compliant) ? ?flashlock ? to secure fpga contents low power ? core voltage for low power ? support for 1.5 v-only systems ? low-impedance flash switches high-performance routing hierarchy ? segmented, hierarchical routing and clock structure advanced i/o ? 700 mbps ddr, lvds-capable i/os (a3p250 and above) ? 1.5 v, 1.8 v, 2.5 v, and 3.3 v mixed-voltage operation ? bank-selectable i/o voltages?up to 4 banks per chip ? single-ended i/o standards: lvttl, lvcmos 3.3 v / 2.5 v / 1.8 v / 1.5 v, 3.3 v pci / 3.3 v pci-x ? and lvcmos 2.5 v / 5.0 v input ? differential i/o standards: lvpecl, lvds, blvds, and m-lvds (a3p250 and above) ? i/o registers on input, output, and enable paths ? hot-swappable and cold sparing i/os ? ? programmable output slew rate ? and drive strength ? weak pull-up/-down ? ieee 1149.1 (jtag) boundary scan test ? pin-compatible packages across the proasic3 family clock conditioning circuit (ccc) and pll ? ? six ccc blocks, one with an integrated pll ? configurable phase-shift, multiply/divide, delay capabilities and external feedback ? wide input frequency range (1.5 mhz to 350 mhz) embedded memory ? ? 1 kbit of flashrom user nonvolatile memory ? srams and fifos with variab le-aspect-ratio 4,608-bit ram blocks (1, 2, 4, 9, and 18 organizations) ? ? true dual-port sram (except 18) arm processor support in proasic3 fpgas ? m1 and m7 proasic3 devices?cortex-m1 and coremp7 soft processor available with or without debug ? ? a3p015 and a3p030 devices do not support this feature. ? supported only by a3p015 and a3p030 devices. proasic3 product family proasic3 devices a3p015 a3p030 a3p060 a3p125 a3p250 a3p400 a3p600 a3p1000 arm7 devices 1 m7a3p1000 cortex-m1 devices 1 m1a3p250 m1a3p400 m1a3p600 m1a3p1000 system gates 15 k 30 k 60 k 125 k 250 k 400 k 600 k 1 m typical equivalent macrocells 128 256 512 1,024 ? ? ? ? versatiles (d-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576 ram kbits (1,024 bits) ? ? 18 36 36 54 108 144 4,608-bit blocks ??488122432 flashrom bits 1 k 1 k 1 k 1 k 1 k 1 k 1 k 1 k secure (aes) isp 2 ? ? yes yes yes yes yes yes integrated pll in cccs ??11 1 1 1 1 versanet globals 3 6 6 18 18 18 18 18 18 i/o banks 2222 4 4 4 4 maximum user i/os 49 81 96 133 157 194 235 300 package pins qfn vqfp tqfp pqfp fbga qn68 qn132 vq100 qn132 vq100 tq144 fg144 qn132 vq100 tq144 pq208 fg144 qn132 5 vq100 pq208 fg144/256 5 pq208 fg144/256/ 484 pq208 fg144/256/ 484 pq208 fg144/256/ 484 notes: 1. refer to the coremp7 datasheet or cortex-m1 product brief for more information. 2. aes is not available for arm-enabled proasic3 devices. 3. six chip (main) and three quadrant global networks are available for a3p060 and above. 4. for higher densities and support of additional features, refer to the proasic3e flash family fpgas with optional arm support handbook. 5. the m1a3p250 device does not support this package. v1.0 proasic3 flash family fpgas ii v1.0 i/os per package 1 proasic3 devices a3p015 a3p030 a3p060 a3p125 a3p250 3 a3p400 3 a3p600 a3p1000 arm7 devices m7a3p1000 cortex-m1 devices m1a3p250 3,6 m1a3p400 3 m1a3p600 m1a3p1000 package i/o type single-ended i/o single-ended i/o single-ended i/o single-ended i/o single-ended i/o 2 differential i/o pairs single-ended i/o 2 differential i/o pairs single-ended i/o 2 differential i/o pairs single-ended i/o 2 differential i/o pairs qn68 49 ? ? ? ? ? ?? ??? qn132 ? 8180848719?? ??? vq100 ? 77 71 71 68 13 ? ? ? ? ? tq144 ? ? 91 100 ? ? ?????? pq208 ? ? ? 133 151 34 151 34 154 35 154 35 fg144 ? ? 96 97 97 24 97 25 97 25 97 25 fg256 ? ? ? ? 157 38 178 38 177 43 177 44 fg484 ? ? ? ? ? ? 194 38 235 60 300 74 notes: 1. when considering migrating your design to a lower- or higher-density device, refer to the proasic3 flash family fpgas handbook to ensure complying with design and board migration requirements. 2. each used differential i/o pair reduces the nu mber of single-ended i/os available by two. 3. for a3p250 and a3p400 devices, the maximum number of lvpec l pairs in east and west banks cannot exceed 15. refer to the proasic3 flash family fpgas t handbook for position assi gnments of the 15 lvpecl pairs. 4. fg256 and fg484 are footprint-compatible packages. 5. "g" indicates rohs-compl iant packages. refer to "proasic3 ordering in formation" on page iii for the location of the "g" in the part number. 6. the m1a3p250 device does not su pport fg256 or qn132 packages. table 1-1 ? proasic3 fpgas package sizes dimensions package qn68 qn132 vq100 tq144 pq208 fg144 fg256 fg484 length width (mm\mm) 8 8 8 8 14 14 20 20 28 28 13 13 17 17 23 23 nominal area (mm 2 ) 64 64 196 400 784 169 289 529 pitch (mm) 0.40.50.50.50.51.01.01.0 height (mm) 0.90 0.75 1.00 1.40 3.40 1.45 1.60 2.23 proasic3 flash family fpgas v1.0 iii proasic3 ordering information * the dc and switching characteristics for the ?f speed grade targets are based only on simulation. the characteristics provided for the ?f speed grade are subj ect to change after establishing fpga specifications. some restrictions might be added and will be reflected in future revisions of this document. the ?f speed grade is only supported in the commercial temperature range. speed grade blank = standard 1 = 15% faster than standard 2 = 25% faster than standard f = 20% slower than standard* a3p1000 fg _ part number proasic3 devices proasic3 devices with arm7 1 package type vq = very thin quad flat pack (0.5 mm pitch) qn = quad flat pack no leads (0.4 mm and 0.5 mm pitches) tq = thin quad flat pack (0.5 mm pitch) 144 i package lead count g lead-free packaging application (temperature range) blank = commercial (0c to +70c ambient temperature) i = industrial ( ? 40c to +85c ambient temperature) blank = standard packaging g= rohs-compliant (green) packaging pp = pre-production es = engineering sample (room temperature only) 30,000 system gates a3p030 = 15,000 system gates a3p015 = 60,000 system gates a3p060 = 125,000 system gates a3p125 = 250,000 system gates a3p250 = 400,000 system gates a3p400 = 600,000 system gates a3p600 = 1,000,000 system gates a3p1000 = proasic3 devices with cortex-m1 250,000 system gates m1a3p250 = 400,000 system gates m1a3p400 = 600,000 system gates m1a3p600 = 1,000,000 system gates m1a3p1000 = 1,000,000 system gates m7a3p1000 = pq = plastic quad flat pack (0.5 mm pitch) fg = fine pitch ball grid array (1.0 mm pitch) proasic3 flash family fpgas iv v1.0 temperature grade offerings speed grade and temperature grade matrix references made to proasic3 devices also apply to arm-enabled proasic3 devices. the arm-enabled part numbers start with m7 (coremp7) and m1 (cortex-m1). contact your local actel represen tative for device availability: http://www.actel.com/contact/default.aspx . a3p015 and a3p030 the a3p015 and a3p030 are architecturally compatible; there are no ram or pll features. package a3p015 a3p030 a3p060 a3p125 a3p250 a3p400 a3p600 a3p1000 arm7 devices m7a3p1000 cortex-m1 devices m1a3p250 m1a3p400 m1a3p600 m1a3p1000 qn68 c, i?????? ? qn132 ? c, i c, i c, i c, i ? ? ? vq100 ? c, i c, i c, i c, i ? ? ? tq144 ? ? c, i c, i ? ? ? ? pq208 ? ? ? c, i c, i c, i c, i c, i fg144 ? ? c, i c, i c, i c, i c, i c, i fg256 ? ? ? ? c, i c, i c, i c, i fg484 ? ? ? ? ? c, i c, i c, i notes: 1. c = commercial temperature range: 0c to 70c ambient temperature 2. i = industrial temperature range: ?40c to 85c ambient temperature temperature grade ?f 1 std. ?1 ?2 c 2 ???? i 3 ? ??? notes: 1. the dc and switching characteri stics for the ?f speed grade target s are based only on simulation. the characteristics provided for the ?f speed grade are subj ect to change after establis hing fpga specifications. some restrictions might be added and will be reflected in future revisions of th is document. the ?f speed grade is only supported in the commerc ial temperature range. 2. c = commercial temperature range: 0c to 70c ambient temperature 3. i = industrial temperature range: ?40c to 85c ambient temperature v1.0 1-1 1 ? proasic3 device family overview general description proasic3, the third-generation family of acte l flash fpgas, offers performance, density, and features beyond those of the proasic plus ? family. nonvolatile flash technology gives proasic3 devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (lapu). proasic3 is reprogrammable and offers time -to-market benefits at an asic-level unit cost. these features enable designers to create high-den sity systems using existi ng asic or fpga design flows and tools. proasic3 devices offer 1 kbit of on-chip, reprog rammable, nonvolatile flashrom storage as well as clock conditioning circuitry based on an integr ated phase-locked loop (pll). the a3p015 and a3p030 devices have no pll or ram support. proasi c3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port sram and up to 300 user i/os. proasic3 devices support the arm7 soft ip core and cortex-m1 devices. the arm-enabled devices have actel ordering numbers that begin with m7a3p (coremp7) and m1a3p (cortex-m1) and do not support aes decryption. flash advantages reduced cost of ownership advantages to the designer extend beyond lo w unit cost, performance, and ease of use. unlike sram-based fpgas, flash-based proa sic3 devices allow all functionality to be live at power-up; no external boot prom is required. on-board security mechanisms prev ent access to all the programming information an d enable secure remote updates of the fpga logic. designers can perform secure remote in-system reprogramming to supp ort future design iterations and field upgrades with confidence that valuable intellectual property (ip) cannot be compromised or copied. secure isp can be performed using the industry-standard aes algorithm. the proasic3 family device architecture mitigates the need for asic migration at higher user volumes. this makes the proasic3 family a cost-effective asic re placement solution, especi ally for applications in the consumer, networking/ communication s, computing, and avionics markets. security the nonvolatile, flash-based proasic3 devices do not require a boot prom, so there is no vulnerable external bitstream that can be easil y copied. proasic3 device s incorporate flashlock, which provides a unique combination of reprogra mmability and design se curity without external overhead, advantages that only an fpga wi th nonvolatile flash programming can offer. proasic3 devices utilize a 128-bit flash-based lo ck and a separate aes key to secure programmed intellectual property and configuration data. in addition, all flashrom da ta in proasic3 devices can be encrypted prior to loading, using the industry-leading aes-128 (fips192) bit block cipher encryption standard. the aes standard was adopted by the national institute of standards and technology (nist) in 2000 and replaces the 1977 de s standard. proasic3 devi ces have a built-in aes decryption engine and a flash-based aes key that make them the most comprehensive programmable logic device securi ty solution available today. pr oasic3 devices with aes-based security allow for secure, remote field updates ov er public networks such as the internet, and ensure that valuable ip remain s out of the hands of system over builders, system cloners, and ip thieves. the contents of a progra mmed proasic3 device cannot be read back, although secure design verification is possible. arm-enabled proasic3 devices do not support user -controlled aes security mechanisms. since the arm core must be protected at all times, aes en cryption is always on for the core logic, so bitstreams are always encrypted. there is no user access to encryption for the flashrom programming data. proasic3 device family overview 1-2 v1.0 security, built into the fpga fabric, is an inherent component of the proasic3 family. the flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficul t. the proasic3 family, with flashlock and aes security, is unique in being highly resistant to both in vasive and noninvasive attacks. your valuable ip is protected and secure, making remote isp possible. an proasic3 device provides the most impenetrable security for programmable logic designs. single chip flash-based fpgas store their configuration information in on-chip flash cells. once programmed, the configuration data is an inherent part of the fpga structure, and no external configuration data needs to be loaded at system power-up (u nlike sram-based fpgas). therefore, flash-based proasic3 fpgas do not require system conf iguration components such as eeproms or microcontrollers to load device configuration da ta. this reduces bill-of-materials costs and pcb area, and increases securi ty and system reliability. live at power-up the actel flash-based proasic3 de vices support level 0 of the lapu classification standard. this feature helps in system component initialization, executio n of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock genera tion, and bus activity management. the lapu feature of flash-based proasic3 devices greatly simplifies total system design and reduces tota l system cost, often eliminating the need for cplds and clock generation plls that are used for these purposes in a syste m. in addition, glitches and brownouts in system power will not corrupt the proasic3 device's fl ash configuration, and unlike sram-based fpgas, the device will not have to be reloaded when system power is re stored. this enab les the reduction or complete removal of the configuration prom, expensive voltage monitor, brownout detection, and clock generator devices from the pcb design. flash-based proasic3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. firm errors firm errors occur most commonly when high-energ y neutrons, generated in the upper atmosphere, strike a configuration cell of an sram fpga. the energy of the coll ision can change the state of the configuration cell and thus change the logic, routing, or i/o behavior in an unpredictable way. these errors are impossible to prev ent in sram fpgas. the consequenc e of this type of error can be a complete system failure. firm e rrors do not exist in the configur ation memory of proasic3 flash- based fpgas. once it is progra mmed, the flash cell configurat ion element of proasic3 fpgas cannot be altered by high-energy neutrons and is therefore immune to th em. recoverable (or soft) errors occur in the user data sram of all fpga devi ces. these can easily be mitigated by using error detection and correction (edac) ci rcuitry built into the fpga fabric. low power flash-based proasic3 devices exhibit power characte ristics similar to an asic, making them an ideal choice for power-sensitive applicat ions. proasic3 devices have only a very limited power-on current surge and no high-current transition peri od, both of which occur on many fpgas. proasic3 devices also have low dynamic power consumption to further maximize power savings. proasic3 device family overview v1.0 1-3 advanced flash technology the proasic3 family offers many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm lvcmos proces s with seven layers of metal. standard cmos design techniques are used to implement logic and control functions. the combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromi sing device routability or perf ormance. logic functions within the device are interconnected thro ugh a four-level routing hierarchy. advanced architecture the proprietary proasic3 architecture provides gr anularity comparable to standard-cell asics. the proasic3 device consists of five distinct and programmabl e architectural features ( figure 1-1 and figure 1-2 on page 1-4 ): ? fpga versatiles ? dedicated flashrom ? dedicated sram/fifo memory ? ? extensive cccs and plls ? ? advanced i/o structure ? the a3p015 and a3p030 do not support pll or sram. * not supported by a3p015 and a3p030 devices figure 1-1 ? proasic3 device architecture overview with two i/o banks (a3p015, a3p030, a3p060, and a3p125) ram block 4,608-bit dual-port sram or fifo block* versatile ccc i/os isp aes decryption* user nonvolatile flashrom charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 proasic3 device family overview 1-4 v1.0 the fpga core consists of a sea of versatiles. ea ch versatile can be configured as a three-input logic function, a d-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. th e versatility of the proasic3 core tile as either a three-input lookup table (lut) equivalent or as a d-flip-flop /latch with enable allows for efficient use of the fpga fabric. the versatile capability is unique to the actel proasic family of third-generation architecture flash fpgas. versatiles are connected wi th any of the four levels of routing hierarchy. flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming . maximum core utilization is possible for virtually any design. in addition, extensive on-chip programming circ uitry allows for rapid, single-voltage (3.3 v) programming of proasic3 device s via an ieee 1532 jtag interface. versatiles the proasic3 core consists of versatiles, wh ich have been enhanced beyond the proasic plus ? core tiles. the proasic3 versat ile supports the following: ? all 3-input logic functions?lut-3 equivalent ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set figure 1-2 ? proasic3 device architecture overview with four i/o banks (a3p250, a3p600, and a3p1000) ram block 4,608-bit dual-port sram or fifo block (a3p600 and a3p1000) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 proasic3 device family overview v1.0 1-5 refer to figure 1-3 for versatile configurations. user nonvolatile flashrom actel proasic3 devices have 1 kbit of on-chip, us er-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications: ? internet protocol addressing (wireless or fixed) ? system calibration settings ? device serialization and/or inventory control ? subscription-based business mode ls (for example, set-top boxes) ? secure key storage for secu re communicati ons algorithms ? asset management/tracking ? date stamping ? version management the flashrom is written using the standard proa sic3 ieee 1532 jtag programming interface. the core can be individually programmed (erased and written), and on-chip aes decryption can be used selectively to securely load data over public networks (except in the a3p015 and a3p030 devices), as in security keys stored in the flashrom for a user design. the flashrom can be programmed via the jtag pr ogramming interf ace, and its contents can be read back either throug h the jtag programming interface or vi a direct fpga core addressing. note that the flashrom can only be programmed fro m the jtag interface and cannot be programmed from the internal logic array. the flashrom is programmed as 8 banks of 128 bi ts; however, reading is performed on a byte-by- byte basis using a synchronous interface. a 7-bit address from the fpga core defines which of the 8 banks and which of the 16 bytes within that ba nk are being read. the th ree most sign ificant bits (msbs) of the flashrom address determine the bank , and the four least sign ificant bits (lsbs) of the flashrom address define the byte. the actel proasic3 developmen t software solutions, libero ? integrated design environment (ide) and designer, have extensive su pport for the flashrom. one such feature is auto-generation of sequential programming fi les for applications requiring a un ique serial number in each part. another feature allows the inclusion of static data for system version control. data for the flashrom can be generated quickl y and easily using actel libero ide and designer software tools. comprehensive programming file su pport is also included to allo w for easy programming of large numbers of parts with di ffering flashrom contents. sram and fifo proasic3 devices (except the a3p015 and a3p030 devices) have embedded sram blocks along their north and south sides. each variab le-aspect-ratio sram block is 4, 608 bits in size. available memory configurations are 25618, 512 9, 1k4, 2k2, and 4k1 bits . the individual blocks have independent read and write ports that can be configured with different bit widths on each port. for example, data can be sent through a 4-bit po rt and read as a single bitstream. the embedded sram blocks can be initialized via the device jtag port (rom emulation mode) using the ujtag macro (except in a3p015 and a3p030 devices). figure 1-3 ? versatile configurations x1 y x2 x3 lut-3 data y clk enable clr d-ff data y clk clr d-ff lut-3 equivalent d-flip-flop with clear or set enable d-flip-flop with clear or set proasic3 device family overview 1-6 v1.0 in addition, every sram block has an embedded fifo control unit. the control unit allows the sram block to be configured as a synchronous fi fo without using additional core versatiles. the fifo width and depth are programmable. the fifo also features programmable almost empty (aempty) and almost full (afull) flags in additi on to the normal empt y and full flags. the embedded fifo control unit cont ains the counters necessary for ge neration of the read and write address pointers. the embedded sram /fifo blocks can be cascaded to create larger configurations. pll and ccc proasic3 devices provide designer s with very flexible clock cond itioning capabili ties. each member of the proasic3 family contains six cccs. one ccc (center west side) has a pll. the a3p015 and a3p030 devices do not have a pll. the six ccc blocks are located at the four corn ers and the centers of the east and west sides. all six ccc blocks are usable; the four corner cccs and the east ccc allow simple clock delay operations as well as clock spine access. the inputs of the six ccc blocks are accessible from the fpga core or fro m one of several inputs located near the ccc that have dedicated connections to the ccc block. the ccc block has these key features: ? wide input frequency range (f in_ccc ) = 1.5 mhz to 350 mhz ? output frequency range (f out_ccc ) = 0.75 mhz to 350 mhz ? clock delay adjustment via programmable and fixed delays from ?7.56 ns to +11.12 ns ? 2 programmable delay types for clock skew minimization ? clock frequency synthesis (for pll only) additional ccc specifications: ? internal phase shift = 0, 90, 180, and 270 . output phase shift depends on the output divider configuration (for pll only). ? output duty cycle = 50% 1.5% or better (for pll only) ? low output jitter: worst case < 2.5% cloc k period peak-to-peak peri od jitter when single global network used (for pll only) ? maximum acquisition time = 300 s (for pll only) ? low power consumption of 5 mw ? exceptional tolerance to input pe riod jitter? allo wable input jitter is up to 1.5 ns (for pll only) ? four precise phases; maximum misalignment betw een adjacent phases of 40 ps (350 mhz / f out_ccc ) (for pll only) global clocking proasic3 devices have exte nsive support for multiple clocking domains. in addition to the ccc and pll support described above, there is a comp rehensive global cloc k distribution network. each versatile input and output port has access to nine versanets: six chip (main) and three quadrant global networks. the ve rsanets can be driven by the ccc or directly accessed from the core via multiplexers (muxes). the versanets can be used to distribute low-s kew clock signals or for rapid distribution of high fanout nets. proasic3 device family overview v1.0 1-7 i/os with advanced i/o standards the proasic3 family of fpgas features a flexible i/o structure, supporti ng a range of voltages (1.5 v, 1.8 v, 2.5 v, and 3.3 v). proasic3 fpgas su pport many different i/o standards?single-ended and differential. the i/os are organized into banks, with two or four banks per device. the configuration of these banks determines the i/o standards supported. each i/o module contains several input, output , and enable registers. these registers allow the implementation of the following: ? single-data-rate applications ? double-data-rate applications?ddr lvds, blvds, and m-lvds i/os for point-to-point communications proasic3 banks for the a3p250 device and above support lvpecl, lvds, blvds and m-lvds. blvds and m-lvds can support up to 20 loads. part number and revision date part number 51700097-001-1 revised february 2008 list of changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current version (v1.0) page 51700097-001-1 this document was divided into two sections and given a version number, starting at v1.0. the first section of th e document includes features, benefits, ordering information, and temperature and speed grade offerings. the second section is a device family overview. 51700097-001-0 (january 2008) this document was updated to include a3p015 device information. qn68 is a new package that was added because it is offered in the a3p015. the following sections were updated: "features and benefits" "proasic3 ordering information" "temperature grade offerings" "proasic3 prod uct family" "a3p015 and a3p030" note "introduction and overview" n/a the "proasic3 fpgas package sizes dimensions" table is new. ii in the "proasic3 ordering information" , the qn package measurements were updated to include bo th 0.4 mm and 0.5 mm. iii in the "general description" section , the number of i/os was updated from 288 to 300. 1-1 v2.2 (july 2007) this document was previously in datasheet v2.2. as a result of moving to the handbook format, actel ha s restarted the version numbers. the new version number is 51700097-001-0. n/a proasic3 device family overview 1-8 v1.0 v2.1 (may 2007) the m7 and m1 device part numbers have been updated in table 1 ? proasic3 product family, "i/os per package", "automotive proasic3 ordering information", "temperature grade offerings", and "speed grade and temperature grade matrix". i, ii, iii, iii, iv the words "ambient temperature" were added to the temperature range in the "automotive proasic3 ordering information", "temperature grade offerings", and "speed grade and temperature grade matrix"sections. iii, iii, iv v2.0 (april 2007) in the "clock conditioning circuit (ccc) and pll" section, the wide input frequency range (1.5 mhz to 200 mhz) was changed to (1.5 mhz to 350 mhz). i the "clock conditioning circuit (ccc) and pll" section was updated. i in the "i/os per package" section, th e a3p030, a3p060, a3p125, acp250, and a3p600 device i/os were updated. ii advanced v0.7 (january 2007) in the "packaging tables", ambient was deleted. ii ambient was deleted from the "speed grade and temperature grade matrix". iv advanced v0.6 (april 2006) in the "i/os per package" table, th e i/o numbers were added for a3p060, a3p125, and a3p250. the a3p030-vq100 i/o was changed from 79 to 77. ii advanced v0.5 (january 2006) blvds and m-ldvs are new i/o standards added to the datasheet. n/a the term flow-through was ch anged to pass-through. n/a table 1 was updated to include the qn132. ii the "i/os per package" table was upda ted with the qn132. the footnotes were also updated. the a3p400-fg144 i/o count was updated. ii "automotive proasic3 ordering informa tion" was updated with the qn132. iii "temperature grade offerings" was updated with the qn132. iii advanced v0.4 (november 2005) the "i/os per package" table was up dated for the foll owing devices and packages: device package a3p250/m7acp250 vq100 a3p250/m7acp250 fg144 a3p1000 fg256 ii advanced v0.3 m7 device information is new. n/a the i/o counts in the "i/os per package" table were updated. ii advanced v0.2 the "i/os per package" table was updated. ii previous version changes in current version (v1.0) page v1.1 2-1 proasic3 dc and switching characteristics 2 ? proasic3 dc and switching characteristics general specifications dc and switching characteristic s for ?f speed grade targets ar e based only on simulation. the characteristics provided for the ?f speed grad e are subject to change after establishing fpga specifications. some restri ctions might be added and will be re flected in future revisions of this document. the ?f speed grade is only suppo rted in the commercial temperature range. operating conditions stresses beyond those listed in table 2-1 may cause permanent damage to the device. exposure to absolute maximum rati ng conditions for extended period s may affect device reliability. absolute maximum ratings are stress ratings only; fu nctional operation of the device at these or any other conditions beyond those listed unde r the recommended operat ing conditions specified in table 2-2 on page 2-2 is not implied. table 2-1 ? absolute maxi mum ratings symbol parameter limits units v cc dc core supply vo ltage ?0.3 to 1.65 v v jtag jtag dc voltage ?0.3 to 3.75 v v pump programming voltage ?0.3 to 3.75 v v ccpll analog power supply (pll) ?0.3 to 1.65 v v cci dc i/o output buffer supply voltage ?0.3 to 3.75 v vmv dc i/o input buffer supply voltage ?0.3 to 3.75 v vi i/o input voltage ?0.3 v to 3.6 v (when i/o hot insertion mode is enabled) ?0.3 v to (v cci + 1 v) or 3.6 v, whichever voltage is lower (when i/o hot-insertion mode is disabled) v t stg 2 storage temperature ?65 to +150 c t j 2 junction temperature +125 c notes: 1. the device should be operated with in the limits specified by the datash eet. during transi tions, the input signal may undershoot or overshoot according to the limits shown in table 2-4 on page 2-3 . 2. for flash programming and rete ntion maximum limits, refer to table 2-3 on page 2-2 , and for recommended operatin g limits, refer to table 2-2 on page 2-2 . proasic3 dc and switching characteristics 2-2 v1.1 table 2-2 ? recommended operating conditions symbol parameter commer cial industrial units t a ambient temperature 0 to +70 4,6 ?40 to +85 5,6 c v cc 1.5 v dc core supply voltag e 1.425 to 1.575 1.425 to 1.575 v v jtag jtag dc voltage 1.4 to 3.6 1.4 to 3.6 v v pump programming voltage programming mode 3.15 to 3.45 3.15 to 3.45 v operation 3 0 to 3.6 0 to 3.6 v v ccpll analog power supply (pll) 1.4 to 1.6 1.4 to 1.6 v v cci and vmv 1.5 v dc su pply voltage 1.425 to 1.575 1.425 to 1.575 v 1.8 v dc supply voltage 1.7 to 1.9 1.7 to 1.9 v 2.5 v dc supply voltage 2.3 to 2.7 2.3 to 2.7 v 3.3 v dc supply voltage 3.0 to 3.6 3.0 to 3.6 v lvds/blvds/m-lvds differential i/o 2.375 to 2.625 2.375 to 2.625 v lvpecl differential i/o 3 .0 to 3.6 3.0 to 3.6 v notes: 1. the ranges given here are for powe r supplies only. the recommended inpu t voltage ranges specific to each i/o standard are given in table 2-14 on page 2-17 . vmv and v cci should be at the same voltage within a given i/o bank. 2. all parameters representing voltages are measured with respect to gnd unless otherwise specified. 3. v pump can be left floating during operation (not programming mode). 4. maximum t j = 85c. 5. maximum t j = 100c. 6. to ensure targeted reliab ility standards are met across ambient an d junction operating temperatures, actel recommends that the user follow best design practices using actel?s ti ming and power simulation tools. table 2-3 ? flash programming limits ? retention, storage and operating temperature 1 product grade programming cycles program retention (biased/unbiased) maximum storage temperature t stg (c) 2 maximum operating junction temperature t j (c) 2 commercial 500 20 years 110 100 industrial 500 20 years 110 100 notes: 1. this is a stress rating only; functional operation at any condition other than t hose indicated is not implied. 2. these limits apply for program/ data retention only. refer to table 2-1 on page 2-1 and table 2-2 for device operating conditions and absolute limits. proasic3 dc and switching characteristics v1.1 2-3 i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial) sophisticated power-up management circuitry is designed into every proasic3 device. these circuits ensure eas y transition from the powered-off state to the powered-up state of the device. the many different supplies can power up in any se quence with minimized current spikes or surges. in addition, the i/o will be in a known state through the power-up sequence. the basic principle is shown in figure 2-1 on page 2-4 . there are five regions to consider during power-up. proasic3 i/os are activated only if all of the following thre e conditions are met: 1. v cc and v cci are above the minimum specified trip points ( figure 2-1 on page 2-4 ). 2. v cci > v cc ? 0.75 v (typical) 3. chip is in the operating mode. v cci trip point: ramping up: 0.6 v < tr ip_point_up < 1.2 v ramping down: 0.5 v < trip_point_down < 1.1 v v cc trip point: ramping up: 0.6 v < tr ip_point_up < 1.1 v ramping down: 0.5 v < trip_point_down < 1 v v cc and v cci ramp-up trip points are about 100 mv hi gher than ramp-dow n trip points. this specifically built-in hysteresis pr events undesirable power-up oscillations and current surges. note the following: ? during programming, i/os become tri stated and weakly pulled up to v cci . ? jtag supply, pll power supplies, and charge pump v pump supply have no influence on i/o behavior. pll behavior at br ownout condition actel recommends using monotonic power supplies or voltage regula tors to ensure proper power- up behavior. power ramp-up should be monotonic at least until v cc and v ccpllx exceed brownout activation levels. the v cc activation level is specified as 1.1 v worst-case (see figure 2-1 on page 2-4 for more details). table 2-4 ? overshoot and undershoot limits (as measured on quiet i/os) 1 v cci and vmv average v cci ?gnd overshoot or undershoot duration as a percentage of clock cycle 2 maximum overshoot/ undershoot 2 2.7 v or less 10% 1.4 v 5% 1.49 v 3 v 10% 1.1 v 5% 1.19 v 3.3 v 10% 0.79 v 5% 0.88 v 3.6 v 10% 0.45 v 5% 0.54 v notes: 1. based on reliability requirements at 85c. 2. the duration is allowed at one out of six clock cy cles (estimated sso density over cycles). if the overshoot/undershoot occurs at one out of two cy cles, the maximum overshoot/undershoot has to be reduced by 0.15 v. 3. this table refers only to overshoo t/undershoot limits for si multaneous switching i/os and does not provide pci overshoot/un dershoot limits. proasic3 dc and switching characteristics 2-4 v1.1 when pll power supply voltage and/or v cc levels drop below the v cc brownout levels (0.75 v 0.25 v), the pll output lock sign al goes low and/or the output clock is lost. refer to the power-up behavior of proasic3/e devices chapter of the handbook for information on clock and lock recovery. internal power-up activation sequence 1. core 2. input buffers output buffers, after 200 ns dela y from input buffer activation figure 2-1 ? i/o state as a function of v cci and v cc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v v cc v cc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification. v cc = v cci + vt proasic3 dc and switching characteristics v1.1 2-5 thermal characteristics introduction the temperature variable in the actel designer software refers to the junction temperature, not the ambient temperature. this is an important distinction be cause dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. eq 2-1 can be used to calculate junction temperature. t j = junction temperature = t + t a eq 2-1 where: t a = ambient temperature t = temperature gradient between junction (silicon) and ambient t = ja * p ja = junction-to-ambient of the package. ja numbers are located in table 2-5 . p = power dissipation package thermal characteristics the device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja . the thermal characteristics for ja are shown for two air flow rates. the absolute maximum junction temperature is 110c. eq 2-2 shows a sample calculation of the absolute maximum power dissipation allo wed for a 484-pin fbga package at commercial temperature and in still air. eq 2-2 maximum power allowed max. junction temp. ( c) max. ambient temp. ( c) ? ja ( c/w) ------------------------------------------------------------------------------------------------------------------------------- -------- 110 c70 c ? 20.5 c/w ------------------------------------ 1 . 9 5 1 w = = = table 2-5 ? package thermal resistivities package type device pin count jc ja units still air 200 ft./min. 500 ft./min. quad flat no lead a3p0 30 132 0.4 21.4 16.8 15.3 c/w a3p060 132 0.3 21.2 16.6 15.0 c/w a3p125 132 0.2 21.1 16.5 14.9 c/w a3p250 132 0.1 21.0 16.4 14.8 c/w very thin quad flat pack (vqf p) all devices 100 10.0 35.3 29.4 27.1 c/w thin quad flat pack (tqfp) al l devices 144 11.0 33.5 28.0 25.7 c/w plastic quad flat pack (pqfp) all devices 208 8.0 26.1 22.5 20.8 c/w pqfp with embedded heatspreader all device s 208 3.8 16.2 13.3 11.9 c/w fine pitch ball grid array (fbg a) see note* 144 3.8 26.9 22.9 21.5 c/w see note* 256 3.8 26.6 22.8 21.5 c/w see note* 484 3.2 20.5 17.0 15.9 c/w a3p1000 144 6.3 31.6 26.2 24.2 c/w a3p1000 256 6.6 28.1 24.4 22.7 c/w a3p1000 484 8.0 23.3 19.0 16.7 c/w * this information applies to all proasic3 devices ex cept the a3p1000. detailed device/package thermal information will be available in future revisions of the datasheet. proasic3 dc and switching characteristics 2-6 v1.1 temperature and voltage derating factors calculating power dissipation quiescent supply current table 2-6 ? temperature and voltage derating factors for timing delays (normalized to t j = 70c, v cc = 1.425 v) array voltage v cc (v) junction temperature (c) ?40c 0c 25c 70c 85c 110c 1.425 0.87 0.92 0. 95 1.00 1.02 1.05 1.500 0.83 0.88 0. 90 0.95 0.97 0.99 1.575 0.80 0.85 0. 87 0.92 0.93 0.96 table 2-7 ? quiescent supply current characteristics a3p030 a3p060 a3p125 a3p250 a3p400 a3p600 a3p1000 typical (25c) 2 ma 2 ma 2 ma 3 ma 3 ma 5 ma 8 ma maximum (commercial) 10 ma 10 ma 10 ma 20 ma 20 ma 30 ma 50 ma maximum (industrial ) 15 ma 15 ma 15 ma 30 ma 30 ma 45 ma 75 ma notes: 1. i dd includes v cc , v pump , v cci , and vmv currents. values do not include i/o static contribution, which is shown in table 2-8 and table 2-9 on page 2-7 . 2. ?f speed grade devices may ex perience higher standby i dd of up to five ti mes the standard i dd and higher i/o leakage. proasic3 dc and switching characteristics v1.1 2-7 power per i/o pin table 2-8 ? summary of i/o input buffer power (p er pin) ? default i/o software settings 1 applicable to advanced i/o banks c load (pf) v cci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 468.67 2.5 v lvcmos 35 2.5 ? 267.48 1.8 v lvcmos 35 1.8 ? 149.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 103.12 3.3 v pci 10 3.3 ? 201.02 3.3 v pci-x 10 3.3 ? 201.02 differential lvds ? 2.5 7.74 88.92 lvpecl ? 3.3 19.54 166.52 notes: 1. dynamic power consumption is given for stand ard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on vmv. 3. p ac10 is the total dynamic power measured on v cc and vmv. table 2-9 ? summary of i/o input buffer power (per pin) ? default i/o software settings 1 applicable to standard plus i/o banks c load (pf) v cci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 452.67 2.5 v lvcmos 35 2.5 ? 258.32 1.8 v lvcmos 35 1.8 ? 133.59 1.5 v lvcmos (jesd8-11) 35 1.5 ? 92.84 3.3 v pci 10 3.3 ? 184.92 3.3 v pci-x 10 3.3 ? 184.92 notes: 1. dynamic power consumption is given for stand ard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on vmv. 3. p ac10 is the total dynamic power measured on v cc and vmv. proasic3 dc and switching characteristics 2-8 v1.1 table 2-10 ? summary of i/o output buffer power (per pin) ? default i/o software settings 1 applicable to standard i/o banks c load (pf) v cci (v) static power p dc3 (mw) 2 dynamic power p ac10 (w/mhz) 3 single-ended 3.3 v lvttl / 3.3 v lvcmos 35 3.3 ? 431.08 2.5 v lvcmos 35 2.5 ? 247.36 1.8 v lvcmos 35 1.8 ? 128.46 1.5 v lvcmos (jesd8-11) 35 1.5 ? 89.46 notes: 1. dynamic power consumption is given for stand ard load and software default drive strength and output slew. 2. p dc3 is the static power (where applicable) measured on v cci . 3. p ac10 is the total dynamic power measured on v cc and v cci . proasic3 dc and switching characteristics v1.1 2-9 power consumption of various internal resources table 2-11 ? different components contributing to dynamic power consumption in proasic3 devices parameter definition device specific dynamic power (w/mhz) a3p1000 a3p600 a3p400 a3p250 a3p125 a3p060 a3p030 p ac1 clock contribution of a global ri b 14.50 12.80 12.80 11.00 11.00 9.30 9.30 p ac2 clock contribution of a global spine 2.48 1.85 1.35 1.58 0.81 0.81 0.41 p ac3 clock contribution of a versatile row 0.81 p ac4 clock contribution of a versatile used as a sequential module 0.12 p ac5 first contribution of a versatile used as a sequential module 0.07 p ac6 second contribution of a versatile used as a sequential module 0.29 p ac7 contribution of a versatile used as a combinatorial module 0.29 p ac8 average contribution of a routing net 0.70 p ac9 contribution of an i/o input pin (standard- dependent) see table 2-8 on page 2-7 . p ac10 contribution of an i/o output pin (standard- dependent) see table 2-8 on page 2-7 and table 2-9 on page 2-7 . p ac11 average contribution of a ram block during a read operation 25.00 p ac12 average contribution of a ram block during a write operation 30.00 p ac13 static pll contribution 2.55 mw p ac14 dynamic contributi on for pll 2.60 * for a different output load, drive strength, or slew ra te, actel recommends using the actel power spreadsheet calculator or smartpower tool in actel libero ? integrated design environment (ide). proasic3 dc and switching characteristics 2-10 v1.1 power calculation methodology this section describes a simplified method to estimate power consumptio n of an application. for more accurate and deta iled power estima tions, use the smartpower tool in actel libero ide software. the power calculation methodology described below uses the following variables: ? the number of plls as well as the number and the frequency of each output clock generated ? the number of combinatorial and se quential cells used in the design ?the internal clock frequencies ? the number and the standard of i/o pins used in the design ? the number of ram blocks used in the design ? toggle rates of i/o pins as well as versatiles?guidelines are provided in table 2-12 on page 2-12 . ? enable rates of output buffers?guidelines are provided for typical applications in table 2-13 on page 2-12 . ? read rate and write rate to the memory?guide lines are provided for typical applications in table 2-13 on page 2-12 . the calculation should be repeat ed for each clock domain defined in the design. methodology total power consumption?p total p total = p stat + p dyn p stat is the total static power consumption. p dyn is the total dynamic power consumption. total static power consumption?p stat p stat = p dc1 + n inputs * p dc2 + n outputs * p dc3 n inputs is the number of i/o input buffers used in the design. n outputs is the number of i/o output buffers used in the design. total dynamic power consumption?p dyn p dyn = p clock + p s-cell + p c-cell + p net + p inputs + p outputs + p memory + p pll global clock contribution?p clock p clock = (p ac1 + n spine *p ac2 + n row *p ac3 + n s-cell * p ac4 ) * f clk n spine is the number of global spines used in the user design?guidelines are provided in table 2-12 on page 2-12 . n row is the number of versatile rows used in the design?guidelines are provided in table 2-12 on page 2-12 . f clk is the global clock signal frequency. n s-cell is the number of versatiles used as sequential modules in the design. p ac1 , p ac2 , p ac3 , and p ac4 are device-dependent. sequential cells contribution?p s-cell p s-cell = n s-cell * (p ac5 + 1 / 2 * p ac6 ) * f clk n s-cell is the number of versatiles used as sequen tial modules in the de sign. when a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-12 on page 2-12 . f clk is the global clock signal frequency. proasic3 dc and switching characteristics v1.1 2-11 combinatorial cells contribution?p c-cell p c-cell = n c-cell * 1 / 2 * p ac7 * f clk n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-12 on page 2-12 . f clk is the global clock signal frequency. routing net contribution?p net p net = (n s-cell + n c-cell ) * 1 / 2 * p ac8 * f clk n s-cell is the number of versatiles used as sequential modules in the design. n c-cell is the number of versatiles used as combinatorial modules in the design. 1 is the toggle rate of versatile outputs?guidelines are provided in table 2-12 on page 2-12 . f clk is the global clock signal frequency. i/o input buffer contribution?p inputs p inputs = n inputs * 2 / 2 * p ac9 * f clk n inputs is the number of i/o input buffers used in the design. 2 is the i/o buffer toggle ra te?guidelines are provided in table 2-12 on page 2-12 . f clk is the global clock signal frequency. i/o output buffer contribution?p outputs p outputs = n outputs * 2 / 2 * 1 * p ac10 * f clk n outputs is the number of i/o output buffers used in the design. 2 is the i/o buffer toggle ra te?guidelines are provided in table 2-12 on page 2-12 . 1 is the i/o buffer enable rate?guidelines are provided in table 2-13 on page 2-12 . f clk is the global clock signal frequency. ram contribution?p memory p memory = p ac11 * n blocks * f read-clock * 2 + p ac12 * n block * f write-clock * 3 n blocks is the number of ram blocks used in the design. f read-clock is the memory r ead clock frequency. 2 is the ram enable rate for read operations. f write-clock is the memory write clock frequency. 3 is the ram enable rate for write op erations?guidelines are provided in table 2-13 on page 2-12 . pll contribution?p pll p pll = p ac13 + p ac14 *f clkout f clkout is the output clock frequency. 1 1. the pll dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the pll, and the frequency of each output clock. if a pll is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (p ac14 * f clkout product) to the total pll contribution. proasic3 dc and switching characteristics 2-12 v1.1 guidelines toggle rate definition a toggle rate defines the frequency of a net or logi c element relative to a clock. it is a percentage. if the toggle rate of a net is 1 00%, this means that this net swit ches at half the clock frequency. below are some examples: ? the average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. ? the average toggle rate of an 8-bit counter is 25%: ? bit 0 (lsb) = 100% ? bit 1 = 50% ? bit 2 = 25% ?? ? bit 7 (msb) = 0.78125% ? average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 enable rate definition output enable rate is the average percentage of time during which tris tate outputs are enabled. when nontristate output buffers are us ed, the enable rate should be 100%. table 2-12 ? toggle rate guidelines reco mmended for power calculation component definition guideline 1 toggle rate of versatile outputs 10% 2 i/o buffer toggle rate 10% table 2-13 ? enable rate guidelines reco mmended for power calculation component definition guideline 1 i/o output buffer enable rate 100% 2 ram enable rate for read operations 12.5% 3 ram enable rate for write operations 12.5% proasic3 dc and switching characteristics v1.1 2-13 user i/o characteristics timing model figure 2-2 ? timing model operating conditions: ?2 speed, commercial temperature range (t j = 70c), worst case v cc =1.425v dq y y dq dq dq y combinational cell combinational cell combinational cell i/o module (registered) i/o module (non-registered) register cell register cell i/o module (registered) i/o module (non-registered) lvpecl (applicable to advanced i/o banks only)l lvpecl (applicable to advanced i/o banks only) lvds, blvds, m-lvds (applicable for advanced i/o banks only) lvttl 3.3 v output drive strength = 12 ma high slew rate y combinational cell y combinational cell y combinational cell i/o module (non-registered) lvttl output drive strength = 8 ma high slew rate i/o module (non-registered) lvcmos 1.5 v output drive strength = 4 ma high slew rate lvttl output drive strength = 12 ma high slew rate i/o module (non-registered) input lvttl clock input lvttl clock input lvttl clock t pd = 0.56 ns t pd = 0.49 ns t dp = 1.34 ns t pd = 0.87 ns t dp = 2.64 ns (advanced i/o banks) t pd = 0.47 ns t dp = 3.66 ns (advanced i/o banks) t pd = 0.47 ns t dp = 3.97 ns (advanced i/o banks) t pd = 0.47 ns t py = 0.76 ns (advanced i/o banks) t clkq = 0.55 ns t oclkq = 0.59 ns t sud = 0.43 ns t osud = 0.31 ns t dp = 2.64 ns (advanced i/o banks) t py = 0.76 ns (advanced i/o banks) t py = 1.20 ns t clkq = 0.55 ns t sud = 0.43 ns t py = 0.76 ns (advanced i/o banks) t iclkq = 0.24 ns t isud = 0.26 ns t py = 1.05 ns proasic3 dc and switching characteristics 2-14 v1.1 figure 2-3 ? input buffer timing model and delays (example) t py (r) pad y v trip gnd t py (f) v trip 50% 50% v ih v cc v il t dout (r) din gnd t dout (f) 50% 50% v cc pad y t py d clk q i/o interface din t din to array t py = max(t py (r), t py (f)) t din = max(t din (r), t din (f)) proasic3 dc and switching characteristics v1.1 2-15 figure 2-4 ? output buffer model and delays (example) t dp (r) pad v ol t dp (f) v trip v trip v oh v cc d 50% 50% v cc 0 v dout 50% 50% 0 v t dout (r) t dout (f) from array pad t dp std load d clk q i/o interface dout d t dout t dp = max(t dp (r), t dp (f)) t dout = max(t dout (r), t dout (f)) proasic3 dc and switching characteristics 2-16 v1.1 figure 2-5 ? tristate output buffer timing model and delays (example) d clk q d clk q 10% v cci t zl v trip 50% t hz 90% v cci t zh v trip 50% 50% t lz 50% eout pad d e 50% t eout (r) 50% t eout (f) pad dout eout d i/o interface e t eout t zls v trip 50% t zhs v trip 50% eout pad d e 50% 50% t eout (r) t eout (f) 50% v cc v cc v cc v cci v cc v cc v cc v oh v ol v ol t zl , t zh , t hz , t lz , t zls , t zhs t eout = max(t eout (r), t eout (f)) proasic3 dc and switching characteristics v1.1 2-17 overview of i/o performance summary of i/o dc input and output levels ? default i/o software settings table 2-14 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings applicable to advanced i/o banks i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 12 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 12 12 1.5 v lvcmos 12 ma high ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 12 12 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 85c junction temperature. table 2-15 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings applicable to standard plus i/o banks i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 12 ma high ?0.3 0.8 2 3.6 0.4 2.4 12 12 2.5 v lvcmos 12 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 1.8 v lvcmos 8 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 1.5 v lvcmos 4 ma high ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 4 4 3.3 v pci per pci specifications 3.3 v pci-x per pci-x specifications note: currents are measured at 85c junction temperature. table 2-16 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions?software default settings applicable to standard i/o banks i/o standard drive strength slew rate v il v ih v ol v oh i ol i oh min, v max, v min, v max, v max, v min, v ma ma 3.3 v lvttl / 3.3 v lvcmos 8 ma high ?0.3 0.8 2 3.6 0.4 2.4 8 8 2.5 v lvcmos 8 ma high ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 1.8 v lvcmos 4 ma high ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 1.5 v lvcmos 2 ma high ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 22 note: currents are measured at 85c junction temperature. proasic3 dc and switching characteristics 2-18 v1.1 summary of i/o timing characteristics ? defaul t i/o software settings table 2-17 ? summary of maximum and minimum dc input levels applicable to commercial and industrial conditions dc i/o standards commercial 1 industrial 2 i il i ih i il i ih a a a a 3.3 v lvttl / 3.3 v lvcmos 10 10 15 15 2.5 v lvcmos 10 10 15 15 1.8 v lvcmos 10 10 15 15 1.5 v lvcmos 10 10 15 15 3.3 v pci 10 10 15 15 3.3 v pci-x 10 10 15 15 notes: 1. commercial range (0c < t a < 70c) 2. industrial range (?40c < t a < 85c) table 2-18 ? summary of ac measuring points standard measuring trip point (v trip ) 3.3 v lvttl / 3.3 v lvcmos 1.4 v 2.5 v lvcmos 1.2 v 1.8 v lvcmos 0.90 v 1.5 v lvcmos 0.75 v 3.3 v pci 0.285 * v cci (rr) 0.615 * v cci (ff) 3.3 v pci-x 0.285 * v cci (rr) 0.615 * v cci (ff) table 2-19 ? i/o ac parameter definitions parameter parameter definition t dp data to pad delay thro ugh the output buffer t py pad to data delay thro ugh the input buffer t dout data to output buffer dela y through the i/o interface t eout enable to output buffer tristate co ntrol delay through the i/o interface t din input buffer to data delay through the i/o interface t hz enable to pad delay through the output buffer?high to z t zh enable to pad delay through the output buffer?z to high t lz enable to pad delay through the output buffer?low to z t zl enable to pad delay through the output buffer?z to low t zhs enable to pad delay through the output buffer with delayed enable?z to high t zls enable to pad delay through the output buffer with delayed enable?z to low proasic3 dc and switching characteristics v1.1 2-19 table 2-20 ? summary of i/o timing character istics?software default settings ?2 speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v advanced i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor ( ) t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 high 35 ? 0.492.640.030.760.322.692.112.402.684.363.78 ns 2.5 v lvcmos 12 high 35 ? 0.492.660.030.980.322.712.562.472.574.384.23 ns 1.8 v lvcmos 12 high 35 ? 0.492.640.030.910.322.692.272.763.054.363.94 ns 1.5 v lvcmos 12 high 35 ? 0.493.050.031.070.323.102.672.953.144.774.34 ns 3.3 v pci per pci spec. high 10 25 2 0.49 2.00 0.03 0.65 0.32 2.04 1. 46 2.40 2.68 3.71 3.13 ns 3.3 v pci-x per pci-x spec. high 10 25 2 0.49 2.00 0.03 0.65 0.32 2.04 1. 46 2.40 2.68 3.71 3.13 ns lvds 24 high??0.491.370.031.20???????ns lvpecl 24 high??0.491.340.031.05???????ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. resistance is used to measure i/o propagatio n delays as defined in pci specifications. see figure 2-10 on page 2-54 for connectivity. this resistor is not required during normal operation. proasic3 dc and switching characteristics 2-20 v1.1 table 2-21 ? summary of i/o timing character istics?software default settings ?2 speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci =3.0v standard plus i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) t zls (ns) t zhs (ns) units 3.3 v lvttl / 3.3 v lvcmos 12 ma high 35 pf ? 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns 2.5 v lvcmos 12 ma high 35 pf ? 0.49 2.39 0.03 0 .970.322.442.352.112.324.114.02 ns 1.8 v lvcmos 8 ma high 35 pf ? 0.49 3.03 0.03 0 .900.322.873.032.192.324.544.70 ns 1.5 v lvcmos 4 ma high 35 pf ? 0.49 3.61 0.03 1 .060.323.353.612.262.345.025.28 ns 3.3 v pci per pci spec. high 10 pf 25 2 0.49 1.72 0.03 0.64 0.32 1.76 1. 27 2.08 2.41 3.42 2.94 ns 3.3 v pci-x per pci-x spec. high 10 pf 25 2 0.49 1.72 0.03 0.64 0.32 1.76 1. 27 2.08 2.41 3.42 2.94 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. resistance is used to measure i/o propagatio n delays as defined in pci specifications. see figure 2-10 on page 2-54 for connectivity. this resistor is not required during normal operation. table 2-22 ? summary of i/o timing character istics?software default settings ?2 speed grade, commercial-case conditions: t j = 70c, worst case v cc = 1.425 v, worst case v cci = 3.0 v standard i/o banks i/o standard drive strength (ma) slew rate capacitive load (pf) external resistor t dout (ns) t dp (ns) t din (ns) t py (ns) t eout (ns) t zl (ns) t zh (ns) t lz (ns) t hz (ns) units 3.3 v lvttl / 3.3 v lvcmos 8 ma high 35 pf ? 0.49 3.29 0.03 0. 75 0.32 3.36 2.80 1.79 2.01 ns 2.5 v lvcmos 8 ma high 35 pf ? 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns 1.8 v lvcmos 4 ma high 35 pf ? 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns 1.5 v lvcmos 2 ma high 35 pf ? 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns notes: 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. 2. resistance is used to measure i/o propagatio n delays as defined in pci specifications. see figure 2-10 on page 2-54 for connectivity. this resistor is not required during normal operation. proasic3 dc and switching characteristics v1.1 2-21 detailed i/o dc characteristics table 2-23 ? input capacitance symbol definition conditions min. max. units c in input capacitance v in = 0, f = 1.0 mhz 8 pf c inclk input capacitance on the clock pin v in = 0, f = 1.0 mhz 8 pf table 2-24 ? i/o output buffer maximum resistances 1 applicable to advanced i/o banks standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 17 50 24 ma 11 33 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 16 ma 20 40 24 ma 11 22 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 12 ma 20 22 16 ma 20 22 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 6 ma 67 75 8 ma 33 37 12 ma 33 37 3.3 v pci/pci-x per pci/pci-x specification 25 75 notes: 1. these maximum values are prov ided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, te mperature, and process. for board design considerations and detailed out put buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.co m/download/ibi s/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec proasic3 dc and switching characteristics 2-22 v1.1 table 2-25 ? i/o output buffer maximum resistances 1 applicable to standard plus i/o banks standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 12 ma 25 75 16 ma 25 75 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 12 ma 25 50 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 6 ma 50 56 8 ma 50 56 1.5 v lvcmos 2 ma 200 224 4 ma 100 112 3.3 v pci/pci-x per pci/pci-x specification 0 0 notes: 1. these maximum values are prov ided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, te mperature, and process. for board design considerations and detailed out put buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.co m/download/ibi s/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec proasic3 dc and switching characteristics v1.1 2-23 table 2-26 ? i/o output buffer maximum resistances 1 applicable to standard i/o banks standard drive strength r pull-down ( ) 2 r pull-up ( ) 3 3.3 v lvttl / 3.3 v lvcmos 2 ma 100 300 4 ma 100 300 6 ma 50 150 8 ma 50 150 2.5 v lvcmos 2 ma 100 200 4 ma 100 200 6 ma 50 100 8 ma 50 100 1.8 v lvcmos 2 ma 200 225 4 ma 100 112 1.5 v lvcmos 2 ma 200 224 notes: 1. these maximum values are prov ided for informational reasons only. minimum output buffer resistance values depend on v cci , drive strength selection, te mperature, and process. for board design considerations and detailed out put buffer resistances, use the corresponding ibis models located on the actel website at http://www.actel.co m/download/ibi s/default.aspx . 2. r (pull-down-max) = (v olspec ) / i olspec 3. r (pull-up-max) = (v ccimax ? v ohspec ) / i ohspec table 2-27 ? i/o weak pull-up/pu ll-down resistances minimum and maximum w eak pull-up/pull-down resistance values v cci r (weak pull-up) 1 ( ) r (weak pull-down) 2 ( ) min. max. min. max. 3.3 v 10 k 45 k 10 k 45 k 2.5 v 11 k 55 k 12 k 74 k 1.8 v 18 k 70 k 17 k 110 k 1.5 v 19 k 90 k 19 k 140 k notes: 1. r (weak pull-up-max) = (v olspec ) / i (weak pull-up-min) 2. r (weak pull-up-max) = (v ccimax ? v ohspec ) / i (weak pull-up-min) proasic3 dc and switching characteristics 2-24 v1.1 table 2-28 ? i/o short currents i osh /i osl applicable to advanced i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 127 132 24 ma 181 268 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 127 132 24 ma 181 268 2.5 v lvcmos 2 ma 18 16 4 ma 18 16 6 ma 37 32 8 ma 37 32 12 ma 74 65 16 ma 87 83 24 ma 124 169 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 6 ma 44 35 8 ma 51 45 12 ma 74 91 16 ma 74 91 1.5 v lvcmos 2 ma 16 13 4 ma 33 25 6 ma 39 32 8 ma 55 66 12 ma 55 66 3.3 v pci/pci-x per pci/pci-x specification 109 103 * t j = 100c proasic3 dc and switching characteristics v1.1 2-25 table 2-29 ? i/o short currents i osh /i osl applicable to standard plus i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 12 ma 109 103 16 ma 109 103 2.5 v lvcmos 2 ma 18 16 4 ma 18 16 6 ma 37 32 8 ma 37 32 12 ma 74 65 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 6 ma 44 35 8 ma 44 35 1.5 v lvcmos 2 ma 16 13 4 ma 33 25 3.3 v pci/pci-x per pci/pci-x specification 109 103 * t j = 100c table 2-30 ? i/o short currents i osh /i osl applicable to standard i/o banks drive strength i osl (ma)* i osh (ma)* 3.3 v lvttl / 3.3 v lvcmos 2 ma 27 25 4 ma 27 25 6 ma 54 51 8 ma 54 51 2.5 v lvcmos 2 ma 18 16 4 ma 18 16 6 ma 37 32 8 ma 37 32 1.8 v lvcmos 2 ma 11 9 4 ma 22 17 1.5 v lvcmos 2 ma 16 13 * t j = 100c proasic3 dc and switching characteristics 2-26 v1.1 the length of time an i/o can withstand i osh /i osl events depends on the junction temperature. the reliability data below is based on a 3.3 v, 12 ma i/o setting, which is the worst case for this type of analysis. for example, at 110c, the short current condition would have to be sustain ed for more than three months to cause a reliability concern. the i/o desi gn does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. table 2-31 ? short current event duration before failure temperature time before failure ?40c > 20 years 0c > 20 years 25c > 20 years 70c 5 years 85c 2 years 100c 6 months 110c 3 months table 2-32 ? i/o input rise time, fall time , and related i/o reliability input buffer input rise/fall time (min.) input rise/fall time (max.) reliability lvttl/lvcmos no requirement 10 ns * 20 years (110c) lvds/blvds/ m-lvds/lvpecl no requirement 10 ns * 10 years (100c) * the maximum input rise/fall time is related to the noise induced into the input buffer trace. if the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. the longer the rise/fall times, the more susceptible the input signal is to the board noise. actel recommends signal integrit y evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. proasic3 dc and switching characteristics v1.1 2-27 single-ended i/o characteristics 3.3 v lvttl / 3.3 v lvcmos low-voltage transistor?transistor logic (lvttl) is a general-purpose standard (eia/jesd) for 3.3 v applications. it uses an lvttl input buffer and push-pull output buffer. table 2-33 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 ma ?0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-34 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 ma ?0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 ma ?0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. proasic3 dc and switching characteristics 2-28 v1.1 table 2-35 ? minimum and maximum dc input and output levels applicable to standard i/o banks 3.3 v lvttl / 3.3 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 ma ?0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 ma ?0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 ma ?0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-6 ? ac loading table 2-36 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 03.31.435 * measuring point = v trip. see table 2-18 on page 2-18 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz proasic3 dc and switching characteristics v1.1 2-29 timing characteristics table 2-37 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.79 9.20 0.05 1.22 0.51 9. 37 7.91 3.18 3.14 12.05 10.60 ns std. 0.66 7.66 0.04 1.02 0.43 7. 80 6.59 2.65 2.61 10.03 8.82 ns ?1 0.56 6.51 0.04 0.86 0.36 6. 63 5.60 2.25 2.22 8.54 7.51 ns ?2 0.49 5.72 0.03 0.76 0.32 5. 82 4.92 1.98 1.95 7.49 6.59 ns 6 ma ?f 0.79 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3. 85 8.69 7.57 ns std. 0.66 4.91 0.04 1.02 0.43 5. 00 4.07 2.99 3.20 7.23 6.31 ns ?1 0.56 4.17 0.04 0.86 0.36 4. 25 3.46 2.54 2.73 6.15 5.36 ns ?2 0.49 3.66 0.03 0.76 0.32 3. 73 3.04 2.23 2.39 5.40 4.71 ns 8 ma ?f 0.79 5.89 0.05 1.22 0.51 6.00 4.89 3.59 3. 85 8.69 7.57 ns std. 0.66 4.91 0.04 1.02 0.43 5. 00 4.07 2.99 3.20 7.23 6.31 ns ?1 0.56 4.17 0.04 0.86 0.36 4. 25 3.46 2.54 2.73 6.15 5.36 ns ?2 0.49 3.66 0.03 0.76 0.32 3. 73 3.04 2.23 2.39 5.40 4.71 ns 12 ma ?f 0.79 4.24 0.05 1.22 0.51 4.32 3.39 3.86 4.30 7.01 6.08 ns std. 0.66 3.53 0.04 1.02 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns ?1 0.56 3.00 0.04 0.86 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns ?2 0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns 16 ma ?f 0.79 4.00 0.05 1.22 0.51 4.08 3.08 3.92 4. 42 6.76 5.77 ns std. 0.66 3.33 0.04 1.02 0.43 3. 39 2.56 3.26 3.68 5.63 4.80 ns ?1 0.56 2.83 0.04 0.86 0.36 2. 89 2.18 2.77 3.13 4.79 4.08 ns ?2 0.49 2.49 0.03 0.76 0.32 2. 53 1.91 2.44 2.75 4.20 3.58 ns 24 ma ?f 0.79 3.69 0.05 1.22 0.51 3.76 2.54 3.99 4. 88 6.45 5.23 ns std. 0.66 3.08 0.04 1.02 0.43 3. 13 2.12 3.32 4.06 5.37 4.35 ns ?1 0.56 2.62 0.04 0.86 0.36 2. 66 1.80 2.83 3.45 4.57 3.70 ns ?2 0.49 2.30 0.03 0.76 0.32 2. 34 1.58 2.48 3.03 4.01 3.25 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-30 v1.1 table 2-38 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.79 12.32 0.05 1.22 0.51 12.55 10.69 3.18 2.95 15.23 13.37 ns std. 0.66 10.26 0.04 1.02 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns ?1 0.56 8.72 0.04 0.86 0.36 8. 89 7.57 2.25 2.09 10.79 9.47 ns ?2 0.49 7.66 0.03 0.76 0.32 7. 80 6.64 1.98 1.83 9.47 8.31 ns 6 ma ?f 0.79 8.74 0.05 1.22 0.51 8. 90 7.55 3.58 3.65 11.59 10.23 ns std. 0.66 7.27 0.04 1.02 0.43 7. 41 6.28 2.98 3.04 9.65 8.52 ns ?1 0.56 6.19 0.04 0.86 0.36 6. 30 5.35 2.54 2.59 8.20 7.25 ns ?2 0.49 5.43 0.03 0.76 0.32 5. 53 4.69 2.23 2.27 7.20 6.36 ns 8 ma ?f 0.79 8.74 0.05 1.22 0.51 8. 90 7.55 3.58 3.65 11.59 10.23 ns std. 0.66 7.27 0.04 1.02 0.43 7. 41 6.28 2.98 3.04 9.65 8.52 ns ?1 0.56 6.19 0.04 0.86 0.36 6. 30 5.35 2.54 2.59 8.20 7.25 ns ?2 0.49 5.43 0.03 0.76 0.32 5. 53 4.69 2.23 2.27 7.20 6.36 ns 12 ma ?f 0.79 6.70 0.05 1.22 0.51 6.83 5.85 3.85 4.10 9.51 8.54 ns std. 0.66 5.58 0.04 1.02 0.43 5. 68 4.87 3.21 3.42 7.92 7.11 ns ?1 0.56 4.75 0.04 0.86 0.36 4. 84 4.14 2.73 2.91 6.74 6.05 ns ?2 0.49 4.17 0.03 0.76 0.32 4. 24 3.64 2.39 2.55 5.91 5.31 ns 16 ma ?f 0.79 6.25 0.05 1.22 0.51 6.37 5.48 3.91 4.22 9.06 8.17 ns std. 0.66 5.21 0.04 1.02 0.43 5. 30 4.56 3.26 3.51 7.54 6.80 ns ?1 0.56 4.43 0.04 0.86 0.36 4. 51 3.88 2.77 2.99 6.41 5.79 ns ?2 0.49 3.89 0.03 0.76 0.32 3. 96 3.41 2.43 2.62 5.63 5.08 ns 24 ma ?f 0.79 5.83 0.05 1.22 0.51 5.93 5.46 3.98 4.67 8.62 8.15 ns std. 0.66 4.85 0.04 1.02 0.43 4. 94 4.54 3.32 3.88 7.18 6.78 ns ?1 0.56 4.13 0.04 0.86 0.36 4. 20 3.87 2.82 3.30 6.10 5.77 ns ?2 0.49 3.62 0.03 0.76 0.32 3. 69 3.39 2.48 2.90 5.36 5.06 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-31 table 2-39 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.79 8.65 0.05 1.20 0.51 8. 81 7.55 2.73 2.81 11.50 10.24 ns std. 0.66 7.20 0.04 1.00 0.43 7. 34 6.29 2.27 2.34 9.57 8.52 ns ?1 0.56 6.13 0.04 0.85 0.36 6. 24 5.35 1.93 1.99 8.14 7.25 ns ?2 0.49 5.38 0.03 0.75 0.32 5. 48 4.69 1.70 1.75 7.15 6.36 ns 6 ma ?f 0.79 5.41 0.05 1.20 0.51 5. 51 4.58 3.10 3.45 8.19 7.27 ns std. 0.66 4.50 0.04 1.00 0.43 4. 58 3.82 2.58 2.88 6.82 6.05 ns ?1 0.56 3.83 0.04 0.85 0.36 3. 90 3.25 2.19 2.45 5.80 5.15 ns ?2 0.49 3.36 0.03 0.75 0.32 3. 42 2.85 1.92 2.15 5.09 4.52 ns 8 ma ?f 0.79 5.41 0.05 1.20 0.51 5.51 4.58 3.10 3.45 8.19 7.27 ns std. 0.66 4.50 0.04 1.00 0.43 4. 58 3.82 2.58 2.88 6.82 6.05 ns ?1 0.56 3.83 0.04 0.85 0.36 3. 90 3.25 2.19 2.45 5.80 5.15 ns ?2 0.49 3.36 0.03 0.75 0.32 3. 42 2.85 1.92 2.15 5.09 4.52 ns 12 ma ?f 0.79 3.80 0.05 1.20 0.51 3.87 3.10 3.35 3.87 6.55 5.79 ns std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns ?1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns ?2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns 16 ma ?f 0.79 3.80 0.05 1.20 0.51 3.87 3.10 3.35 3.87 6.55 5.79 ns std. 0.66 3.16 0.04 1.00 0.43 3. 22 2.58 2.79 3.22 5.45 4.82 ns ?1 0.56 2.69 0.04 0.85 0.36 2. 74 2.20 2.37 2.74 4.64 4.10 ns ?2 0.49 2.36 0.03 0.75 0.32 2. 40 1.93 2.08 2.41 4.07 3.60 ns notes: 1. software default select ion highlighted in gray. 1. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-32 v1.1 table 2-40 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.79 11.63 0.05 1.20 0.51 11.84 10.12 2.74 2.65 14.53 12.81 ns std. 0.66 9.68 0.04 1.00 0.43 9. 86 8.42 2.28 2.21 12.09 10.66 ns ?1 0.56 8.23 0.04 0.85 0.36 8. 39 7.17 1.94 1.88 10.29 9.07 ns ?2 0.49 7.23 0.03 0.75 0.32 7. 36 6.29 1.70 1.65 9.03 7.96 ns 6 ma ?f 0.79 8.05 0.05 1.20 0.51 8.20 7.07 3.10 3.29 10.88 9.76 ns std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns ?1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns ?2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns 8 ma ?f 0.79 8.05 0.05 1.20 0.51 8.20 7.07 3.10 3.29 10.88 9.76 ns std. 0.66 6.70 0.04 1.00 0.43 6. 82 5.89 2.58 2.74 9.06 8.12 ns ?1 0.56 5.70 0.04 0.85 0.36 5. 80 5.01 2.20 2.33 7.71 6.91 ns ?2 0.49 5.00 0.03 0.75 0.32 5. 10 4.40 1.93 2.05 6.76 6.06 ns 12 ma ?f 0.79 6.06 0.05 1.20 0.51 6.18 5.42 3.35 3.70 8.86 8.10 ns std. 0.66 5.05 0.04 1.00 0.43 5. 14 4.51 2.79 3.08 7.38 6.75 ns ?1 0.56 4.29 0.04 0.85 0.36 4. 37 3.84 2.38 2.62 6.28 5.74 ns ?2 0.49 3.77 0.03 0.75 0.32 3. 84 3.37 2.09 2.30 5.51 5.04 ns 16 ma ?f 0.79 6.06 0.05 1.20 0.51 6.18 5.42 3.35 3.70 8.86 8.10 ns std. 0.66 5.05 0.04 1.00 0.43 5. 14 4.51 2.79 3.08 7.38 6.75 ns ?1 0.56 4.29 0.04 0.85 0.36 4. 37 3.84 2.38 2.62 6.28 5.74 ns ?2 0.49 3.77 0.03 0.75 0.32 3. 84 3.37 2.09 2.30 5.51 5.04 note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-33 table 2-41 ? 3.3 v lvttl / 3.3 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma ?f 0.79 8.49 0.05 1.20 0. 51 8.65 7.48 2.49 2.58 ns std. 0.66 7.07 0.04 1.00 0. 43 7.20 6.23 2.07 2.15 ns ?1 0.56 6.01 0.04 0.85 0. 36 6.12 5.30 1.76 1.83 ns ?2 0.49 5.28 0.03 0.75 0. 32 5.37 4.65 1.55 1.60 ns 4 ma ?f 0.79 8.49 0.05 1.20 0.51 8.65 7.48 2.49 2.58 ns std. 0.66 7.07 0.04 1.00 0. 43 7.20 6.23 2.07 2.15 ns ?1 0.56 6.01 0.04 0.85 0. 36 6.12 5.30 1.76 1.83 ns ?2 0.49 5.28 0.03 0.75 0. 32 5.37 4.65 1.55 1.60 ns 6 ma ?f 0.79 5.30 0.05 1.20 0. 51 5.40 4.51 2.88 3.23 ns std. 0.66 4.41 0.04 1.00 0. 43 4.49 3.75 2.39 2.69 ns ?1 0.56 3.75 0.04 0.85 0. 36 3.82 3.19 2.04 2.29 ns ?2 0.49 3.29 0.03 0.75 0. 32 3.36 2.80 1.79 2.01 ns 8 ma ?f 0.79 5.30 0.05 1.20 0.51 5.40 4.51 2.88 3.23 ns std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns ?1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns ?2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-34 v1.1 table 2-42 ? 3.3 v lvttl / 3.3 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma ?f 0.79 11.37 0.05 1.20 0.51 11.58 10.26 2.49 2.45 ns std. 0.66 9.46 0.04 1.00 0. 43 9.64 8.54 2.07 2.04 ns ?1 0.56 8.05 0.04 0.85 0. 36 8.20 7.27 1.76 1.73 ns ?2 0.49 7.07 0.03 0.75 0. 32 7.20 6.38 1.55 1.52 ns 4 ma ?f 0.79 11.37 0.05 1.20 0.51 11.58 10.26 2.49 2.45 ns std. 0.66 9.46 0.04 1.00 0. 43 9.64 8.54 2.07 2.04 ns ?1 0.56 8.05 0.04 0.85 0. 36 8.20 7.27 1.76 1.73 ns ?2 0.49 7.07 0.03 0.75 0. 32 7.20 6.38 1.55 1.52 ns 6 ma ?f 0.79 7.89 0.05 1.20 0. 51 8.04 7.19 2.88 3.09 ns std. 0.66 6.57 0.04 1.00 0. 43 6.69 5.98 2.40 2.57 ns ?1 0.56 5.59 0.04 0.85 0. 36 5.69 5.09 2.04 2.19 ns ?2 0.49 4.91 0.03 0.75 0. 32 5.00 4.47 1.79 1.92 ns 8 ma ?f 0.79 7.89 0.05 1.20 0.51 8.04 7.19 2.88 3.09 ns std. 0.66 6.57 0.04 1.00 0. 43 6.69 5.98 2.40 2.57 ns ?1 0.56 5.59 0.04 0.85 0. 36 5.69 5.09 2.04 2.19 ns ?2 0.49 4.91 0.03 0.75 0. 32 5.00 4.47 1.79 1.92 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-35 2.5 v lvcmos low-voltage cmos for 2.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 2.5 v applications. it uses a 5 v?tolerant input buffer and push-pull output buffer. table 2-43 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 16 ma ?0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10 24 ma ?0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-44 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 18 16 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 37 32 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10 12 ma ?0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. proasic3 dc and switching characteristics 2-36 v1.1 table 2-45 ? minimum and maximum dc input and output levels applicable to standard i/o banks 2.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10 4 ma ?0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 ma ?0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 ma ?0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. figure 2-7 ? ac loading table 2-46 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 02.51.235 * measuring point = v trip. see table 2-18 on page 2-18 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz proasic3 dc and switching characteristics v1.1 2-37 timing characteristics table 2-47 ? 2.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.72 10.41 0.05 1.57 0.51 9.41 10.41 3.22 2.77 12.09 13.09 ns std. 0.60 8.66 0.04 1.31 0.43 7. 83 8.66 2.68 2.30 10.07 10.90 ns ?1 0.51 7.37 0.04 1.11 0.36 6. 66 7.37 2.28 1.96 8.56 9.27 ns ?2 0.45 6.47 0.03 0.98 0.32 5. 85 6.47 2.00 1.72 7.52 8.14 ns 6 ma ?f 0.72 6.21 0.05 1.57 0.51 6. 05 6.21 3.66 3.60 8.74 8.89 ns std. 0.60 5.17 0.04 1.31 0.43 5. 04 5.17 3.05 3.00 7.27 7.40 ns ?1 0.51 4.39 0.04 1.11 0.36 4. 28 4.39 2.59 2.55 6.19 6.30 ns ?2 0.45 3.86 0.03 0.98 0.32 3. 76 3.86 2.28 2.24 5.43 5.53 ns 8 ma ?f 0.72 6.21 0.05 1.57 0.51 6.05 6.21 3.66 3.60 8.74 8.89 ns std. 0.60 5.17 0.04 1.31 0.43 5. 04 5.17 3.05 3.00 7.27 7.40 ns ?1 0.51 4.39 0.04 1.11 0.36 4. 28 4.39 2.59 2.55 6.19 6.30 ns ?2 0.45 3.86 0.03 0.98 0.32 3. 76 3.86 2.28 2.24 5.43 5.53 ns 12 ma ?f 0.72 4.28 0.05 1.57 0.51 4.36 4.12 3.97 4.13 7.04 6.81 ns std. 0.60 3.56 0.04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns ?1 0.51 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns ?2 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns 16 ma ?f 0.72 4.03 0.05 1.57 0.51 4. 10 3.68 4.04 4.26 6.79 6.36 ns std. 0.60 3.35 0.04 1.31 0.43 3. 41 3.06 3.36 3.55 5.65 5.30 ns ?1 0.51 2.85 0.04 1.11 0.36 2. 90 2.60 2.86 3.02 4.81 4.51 ns ?2 0.45 2.50 0.03 0.98 0.32 2. 55 2.29 2.51 2.65 4.22 3.96 ns 24 ma ?f 0.72 3.71 0.05 1.57 0.51 3. 78 2.93 4.13 4.80 6.47 5.62 ns std. 0.60 3.09 0.04 1.31 0.43 3. 15 2.44 3.44 4.00 5.38 4.68 ns ?1 0.51 2.63 0.04 1.11 0.36 2. 68 2.08 2.92 3.40 4.58 3.98 ns ?2 0.45 2.31 0.03 0.98 0.32 2. 35 1.82 2.57 2.98 4.02 3.49 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-38 v1.1 table 2-48 ? 2.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.72 13.69 0.05 1.57 0.51 13.48 13.69 3.22 2.65 16.16 16.38 ns std. 0.60 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns ?1 0.51 9.69 0.04 1.11 0.36 9. 54 9.69 2.28 1.88 11.44 11.60 ns ?2 0.45 8.51 0.03 0.98 0.32 8. 38 8.51 2.00 1.65 10.05 10.18 ns 6 ma ?f 0.72 9.56 0.05 1.57 0.51 9. 74 9.39 3.66 3.47 12.43 12.07 ns std. 0.60 7.96 0.04 1.31 0.43 8. 11 7.81 3.05 2.89 10.34 10.05 ns ?1 0.51 6.77 0.04 1.11 0.36 6. 90 6.65 2.59 2.46 8.80 8.55 ns ?2 0.45 5.94 0.03 0.98 0.32 6. 05 5.84 2.28 2.16 7.72 7.50 ns 8 ma ?f 0.72 9.56 0.05 1.57 0.51 9.74 9.39 3.66 3.47 12.43 12.07 ns std. 0.60 7.96 0.04 1.31 0.43 8. 11 7.81 3.05 2.89 10.34 10.05 ns ?1 0.51 6.77 0.04 1.11 0.36 6. 90 6.65 2.59 2.46 8.80 8.55 ns ?2 0.45 5.94 0.03 0.98 0.32 6. 05 5.84 2.28 2.16 7.72 7.50 ns 12 ma ?f 0.72 7.42 0.05 1.57 0.51 7.56 7.11 3.97 3.99 10.25 9.80 ns std. 0.60 6.18 0.04 1.31 0.43 6. 29 5.92 3.30 3.32 8.53 8.15 ns ?1 0.51 5.26 0.04 1.11 0.36 5. 35 5.03 2.81 2.83 7.26 6.94 ns ?2 0.45 4.61 0.03 0.98 0.32 4. 70 4.42 2.47 2.48 6.37 6.09 ns 16 ma ?f 0.72 6.92 0.05 1.57 0.51 7. 05 6.64 4.04 4.13 9.74 9.32 ns std. 0.60 5.76 0.04 1.31 0.43 5. 87 5.53 3.36 3.44 8.11 7.76 ns ?1 0.51 4.90 0.04 1.11 0.36 4. 99 4.70 2.86 2.92 6.90 6.60 ns ?2 0.45 4.30 0.03 0.98 0.32 4. 38 4.13 2.51 2.57 6.05 5.80 ns 24 ma ?f 0.72 6.61 0.05 1.57 0.51 6. 61 6.61 4.13 4.65 9.30 9.30 ns std. 0.60 5.51 0.04 1.31 0.43 5. 50 5.51 3.43 3.87 7.74 7.74 ns ?1 0.51 4.68 0.04 1.11 0.36 4. 68 4.68 2.92 3.29 6.58 6.59 ns ?2 0.45 4.11 0.03 0.98 0.32 4. 11 4.11 2.56 2.89 5.78 5.78 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-39 table 2-49 ? 2.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.79 9.94 0.05 1.56 0.51 8. 90 9.94 2.70 2.49 11.58 12.63 ns std. 0.66 8.28 0.04 1.30 0.43 7. 41 8.28 2.25 2.07 9.64 10.51 ns ?1 0.56 7.04 0.04 1.10 0.36 6. 30 7.04 1.92 1.76 8.20 8.94 ns ?2 0.49 6.18 0.03 0.97 0.32 5. 53 6.18 1.68 1.55 7.20 7.85 ns 6 ma ?f 0.79 5.83 0.05 1.56 0.51 5. 58 5.83 3.11 3.26 8.27 8.52 ns std. 0.66 4.85 0.04 1.30 0.43 4. 65 4.85 2.59 2.71 6.88 7.09 ns ?1 0.56 4.13 0.04 1.10 0.36 3. 95 4.13 2.20 2.31 5.85 6.03 ns ?2 0.49 3.62 0.03 0.97 0.32 3. 47 3.62 1.93 2.02 5.14 5.29 ns 8 ma ?f 0.79 5.83 0.05 1.56 0.51 5.58 5.83 3.11 3.26 8.27 8.52 ns std. 0.66 4.85 0.04 1.30 0.43 4. 65 4.85 2.59 2.71 6.88 7.09 ns ?1 0.56 4.13 0.04 1.10 0.36 3. 95 4.13 2.20 2.31 5.85 6.03 ns ?2 0.49 3.62 0.03 0.97 0.32 3. 47 3.62 1.93 2.02 5.14 5.29 ns 12 ma ?f 0.79 3.85 0.05 1.56 0.51 3.92 3.77 3.39 3.74 6.61 6.46 ns std. 0.66 3.21 0.04 1.30 0.43 3.27 3.14 2.82 3.11 5.50 5.38 ns ?1 0.56 2.73 0.04 1.10 0.36 2.78 2.67 2.40 2.65 4.68 4.57 ns ?2 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-40 v1.1 table 2-50 ? 2.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 4 ma ?f 0.79 13.02 0.05 1.56 0.51 12.78 13.02 2.71 2.39 15.46 15.71 ns std. 0.66 10.84 0.04 1.30 0.43 10.64 10.84 2.26 1.99 12.87 13.08 ns ?1 0.56 9.22 0.04 1.10 0.36 9. 05 9.22 1.92 1.69 10.95 11.12 ns ?2 0.49 8.10 0.03 0.97 0.32 7. 94 8.10 1.68 1.49 9.61 9.77 ns 6 ma ?f 0.79 8.85 0.05 1.56 0.51 9. 01 8.84 3.11 3.14 11.70 11.53 ns std. 0.66 7.37 0.04 1.30 0.43 7. 50 7.36 2.59 2.61 9.74 9.60 ns ?1 0.56 6.27 0.04 1.10 0.36 6. 38 6.26 2.20 2.22 8.29 8.16 ns ?2 0.49 5.50 0.03 0.97 0.32 5. 60 5.50 1.93 1.95 7.27 7.17 ns 8 ma ?f 0.79 8.85 0.05 1.56 0.51 9.01 8.84 3.11 3.14 11.70 11.53 ns std. 0.66 7.37 0.04 1.30 0.43 7. 50 7.36 2.59 2.61 9.74 9.60 ns ?1 0.56 6.27 0.04 1.10 0.36 6. 38 6.26 2.20 2.22 8.29 8.16 ns ?2 0.49 5.50 0.03 0.97 0.32 5. 60 5.50 1.93 1.95 7.27 7.17 ns 12 ma ?f 0.79 6.76 0.05 1.56 0.51 6.89 6.61 3.40 3.62 9.57 9.30 ns std. 0.66 5.63 0.04 1.30 0.43 5. 73 5.51 2.83 3.01 7.97 7.74 ns ?1 0.56 4.79 0.04 1.10 0.36 4. 88 4.68 2.41 2.56 6.78 6.59 ns ?2 0.49 4.20 0.03 0.97 0.32 4. 28 4.11 2.11 2.25 5.95 5.78 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-41 table 2-51 ? 2.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma ?f 0.79 9.86 0.05 1.55 0. 51 8.70 9.86 2.44 2.29 ns std. 0.66 8.20 0.04 1.29 0. 43 7.24 8.20 2.03 1.91 ns ?1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns ?2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns 4 ma ?f 0.79 9.86 0.05 1.55 0. 51 8.70 9.86 2.44 2.29 ns std. 0.66 8.20 0.04 1.29 0. 43 7.24 8.20 2.03 1.91 ns ?1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns ?2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns 6 ma ?f 0.79 5.72 0.05 1.55 0. 51 5.47 5.72 2.86 3.07 ns std. 0.66 4.77 0.04 1.29 0. 43 4.55 4.77 2.38 2.55 ns ?1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns ?2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns 8 ma ?f 0.79 5.72 0.05 1.55 0.51 5.47 5.72 2.86 3.07 ns std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns ?1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns ?2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-42 v1.1 table 2-52 ? 2.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma ?f 0.79 13.21 0.05 1.55 0.51 12.46 13.21 2.44 2.20 ns std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns ?1 0.56 9.35 0.04 1.10 0. 36 8.83 9.35 1.73 1.56 ns ?2 0.49 8.21 0.03 0.96 0. 32 7.75 8.21 1.52 1.37 ns 4 ma ?f 0.79 13.21 0.05 1.55 0.51 12.46 13.21 2.44 2.20 ns std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns ?1 0.56 9.35 0.04 1.10 0. 36 8.83 9.35 1.73 1.56 ns ?2 0.49 8.21 0.03 0.96 0. 32 7.75 8.21 1.52 1.37 ns 6 ma ?f 0.79 9.01 0.05 1.55 0. 51 8.84 9.01 2.87 2.96 ns std. 0.66 7.50 0.04 1.29 0. 43 7.36 7.50 2.39 2.46 ns ?1 0.56 6.38 0.04 1.10 0. 36 6.26 6.38 2.03 2.10 ns ?2 0.49 5.60 0.03 0.96 0. 32 5.49 5.60 1.78 1.84 ns 8 ma ?f 0.79 9.01 0.05 1.55 0. 51 8.84 9.01 2.87 2.96 ns std. 0.66 7.50 0.04 1.29 0. 43 7.36 7.50 2.39 2.46 ns ?1 0.56 6.38 0.04 1.10 0. 36 6.26 6.38 2.03 2.10 ns ?2 0.49 5.60 0.03 0.96 0. 32 5.49 5.60 1.78 1.84 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-43 1.8 v lvcmos low-voltage cmos for 1.8 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.8 v applications. it uses a 1.8 v input buffer and a push-pull output buffer. table 2-53 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 51 45 10 10 12 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 12 12 74 91 10 10 16 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 16 16 74 91 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-54 ? minimum and maximum dc input and output levels applicable to standard plus i/o i/o banks 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 11 9 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 22 17 10 10 6 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 6 6 44 35 10 10 8 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 8 8 44 35 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default select ion highlighted in gray. proasic3 dc and switching characteristics 2-44 v1.1 table 2-55 ? minimum and maximum dc input and output levels applicable to standard i/o banks 1.8 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 2 2 9 11 10 10 4 ma ?0.3 0.35 * v cci 0.65 * v cci 3.6 0.45 v cci ? 0.45 4 4 17 22 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default select ion highlighted in gray. figure 2-8 ? ac loading table 2-56 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 01.80.935 * measuring point = v trip. see table 2-18 on page 2-18 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz proasic3 dc and switching characteristics v1.1 2-45 timing characteristics table 2-57 ? 1.8 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.79 14.25 0.05 1.46 0.51 10.97 14.25 3.33 1.99 13.66 16.94 ns std. 0.66 11.86 0.04 1.22 0.43 9.14 11.86 2.77 1.66 11.37 14.10 ns ?1 0.56 10.09 0.04 1.04 0.36 7.77 10.09 2.36 1.41 9.67 11.99 ns ?2 0.49 8.86 0.03 0.91 0.32 6. 82 8.86 2.07 1.24 8.49 10.53 ns 4 ma ?f 0.79 8.31 0.05 1.46 0.51 7.04 8.31 3.87 3.41 9.73 10.99 ns std. 0.66 6.91 0.04 1.22 0.43 5. 86 6.91 3.22 2.84 8.10 9.15 ns ?1 0.56 5.88 0.04 1.04 0.36 4. 99 5.88 2.74 2.41 6.89 7.78 ns ?2 0.49 5.16 0.03 0.91 0.32 4. 38 5.16 2.41 2.12 6.05 6.83 ns 6 ma ?f 0.79 5.34 0.05 1.46 0.51 5. 02 5.34 4.24 4.06 7.71 8.03 ns std. 0.66 4.45 0.04 1.22 0.43 4. 18 4.45 3.53 3.38 6.42 6.68 ns ?1 0.56 3.78 0.04 1.04 0.36 3. 56 3.78 3.00 2.88 5.46 5.69 ns ?2 0.49 3.32 0.03 0.91 0.32 3. 12 3.32 2.64 2.53 4.79 4.99 ns 8 ma ?f 0.79 4.71 0.05 1.46 0.51 4. 72 4.71 4.32 4.23 7.40 7.40 ns std. 0.66 3.92 0.04 1.22 0.43 3. 93 3.92 3.60 3.52 6.16 6.16 ns ?1 0.56 3.34 0.04 1.04 0.36 3. 34 3.34 3.06 3.00 5.24 5.24 ns ?2 0.49 2.93 0.03 0.91 0.32 2. 93 2.93 2.69 2.63 4.60 4.60 ns 12 ma ?f 0.79 4.24 0.05 1.46 0.51 4.32 3.65 4.45 4.90 7.01 6.34 ns std. 0.66 3.53 0.04 1.22 0.43 3.60 3.04 3.70 4.08 5.84 5.28 ns ?1 0.56 3.01 0.04 1.04 0.36 3.06 2.59 3.15 3.47 4.96 4.49 ns ?2 0.49 2.64 0.03 0.91 0.32 2.69 2.27 2.76 3.05 4.36 3.94 ns 16 ma ?f 0.79 4.24 0.05 1.46 0.51 4. 32 3.65 4.45 4.90 7.01 6.34 ns std. 0.66 3.53 0.04 1.22 0.43 3. 60 3.04 3.70 4.08 5.84 5.28 ns ?1 0.56 3.01 0.04 1.04 0.36 3. 06 2.59 3.15 3.47 4.96 4.49 ns ?2 0.49 2.64 0.03 0.91 0.32 2. 69 2.27 2.76 3.05 4.36 3.94 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-46 v1.1 table 2-58 ? 1.8 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.79 18.66 0.05 1.46 0.51 16.95 18.66 3.34 1.92 19.64 21.34 ns std. 0.66 15.53 0.04 1.22 0.43 14.11 15.53 2.78 1.60 16.35 17.77 ns ?1 0.56 13.21 0.04 1.04 0.36 12.01 13.21 2.36 1.36 13.91 15.11 ns ?2 0.49 11.60 0.03 0.91 0.32 10.54 11.60 2.07 1.19 12.21 13.27 ns 4 ma ?f 0.79 12.58 0.05 1.46 0.51 12.51 12.58 3.88 3.28 15.19 15.27 ns std. 0.66 10.48 0.04 1.22 0.43 10.41 10.48 3.23 2.73 12.65 12.71 ns ?1 0.56 8.91 0.04 1.04 0.36 8.86 8.91 2.75 2.33 10.76 10.81 ns ?2 0.49 7.82 0.03 0.91 0.32 7. 77 7.82 2.41 2.04 9.44 9.49 ns 6 ma ?f 0.79 9.67 0.05 1.46 0.51 9. 85 9.42 4.25 3.93 12.53 12.11 ns std. 0.66 8.05 0.04 1.22 0.43 8. 20 7.84 3.54 3.27 10.43 10.08 ns ?1 0.56 6.85 0.04 1.04 0.36 6. 97 6.67 3.01 2.78 8.88 8.57 ns ?2 0.49 6.01 0.03 0.91 0.32 6. 12 5.86 2.64 2.44 7.79 7.53 ns 8 ma ?f 0.79 9.01 0.05 1.46 0.51 9. 18 8.77 4.33 4.10 11.87 11.45 ns std. 0.66 7.50 0.04 1.22 0.43 7. 64 7.30 3.61 3.41 9.88 9.53 ns ?1 0.56 6.38 0.04 1.04 0.36 6. 50 6.21 3.07 2.90 8.40 8.11 ns ?2 0.49 5.60 0.03 0.91 0.32 5. 71 5.45 2.69 2.55 7.38 7.12 ns 12 ma ?f 0.79 8.76 0.05 1.46 0.51 8. 69 8.76 4.45 4.74 11.38 11.45 ns std. 0.66 7.29 0.04 1.22 0.43 7. 23 7.29 3.71 3.95 9.47 9.53 ns ?1 0.56 6.20 0.04 1.04 0.36 6. 15 6.20 3.15 3.36 8.06 8.11 ns ?2 0.49 5.45 0.03 0.91 0.32 5. 40 5.45 2.77 2.95 7.07 7.12 ns 16 ma ?f 0.79 8.76 0.05 1.46 0.51 8. 69 8.76 4.45 4.74 11.38 11.45 ns std. 0.66 7.29 0.04 1.22 0.43 7. 23 7.29 3.71 3.95 9.47 9.53 ns ?1 0.56 6.20 0.04 1.04 0.36 6. 15 6.20 3.15 3.36 8.06 8.11 ns ?2 0.49 5.45 0.03 0.91 0.32 5. 40 5.45 2.77 2.95 7.07 7.12 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-47 table 2-59 ? 1.8 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.79 13.61 0.05 1.44 0.51 10.48 13.61 2.70 1.83 13.17 16.30 ns std. 0.66 11.33 0.04 1.20 0.43 8.72 11.33 2.24 1.52 10.96 13.57 ns ?1 0.56 9.64 0.04 1.02 0.36 7. 42 9.64 1.91 1.29 9.32 11.54 ns ?2 0.49 8.46 0.03 0.90 0.32 6. 51 8.46 1.68 1.14 8.18 10.13 ns 4 ma ?f 0.79 7.79 0.05 1.44 0.51 6.58 7.79 3.18 3.13 9.27 10.47 ns std. 0.66 6.48 0.04 1.20 0.43 5. 48 6.48 2.65 2.60 7.72 8.72 ns ?1 0.56 5.51 0.04 1.02 0.36 4. 66 5.51 2.25 2.21 6.56 7.42 ns ?2 0.49 4.84 0.03 0.90 0.32 4. 09 4.84 1.98 1.94 5.76 6.51 ns 6 ma ?f 0.79 4.88 0.05 1.44 0.51 4. 61 4.88 3.52 3.73 7.30 7.56 ns std. 0.66 4.06 0.04 1.20 0.43 3. 84 4.06 2.93 3.10 6.07 6.30 ns ?1 0.56 3.45 0.04 1.02 0.36 3. 27 3.45 2.49 2.64 5.17 5.36 ns ?2 0.49 3.03 0.03 0.90 0.32 2. 87 3.03 2.19 2.32 4.54 4.70 ns 8 ma ?f 0.79 4.88 0.05 1.44 0.51 4.61 4.88 3.52 3.73 7.30 7.56 ns std. 0.66 4.06 0.04 1.20 0.43 3.84 4.06 2.93 3.10 6.07 6.30 ns ?1 0.56 3.45 0.04 1.02 0.36 3.27 3.45 2.49 2.64 5.17 5.36 ns ?2 0.49 3.03 0.03 0.90 0.32 2.87 3.03 2.19 2.32 4.54 4.70 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-48 v1.1 table 2-60 ? 1.8 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.7 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.79 17.78 0.05 1.44 0.51 16.21 17.78 2.70 1.76 18.90 20.47 ns std. 0.66 14.80 0.04 1.20 0.43 13.49 14.80 2.25 1.46 15.73 17.04 ns ?1 0.56 12.59 0.04 1.02 0.36 11.4 8 12.59 1.91 1.25 13.38 14.49 ns ?2 0.49 11.05 0.03 0.90 0.32 10.0 8 11.05 1.68 1.09 11.75 12.72 ns 4 ma ?f 0.79 11.89 0.05 1.44 0.51 11.69 11.89 3.19 3.00 14.38 14.58 ns std. 0.66 9.90 0.04 1.20 0.43 9. 73 9.90 2.65 2.50 11.97 12.13 ns ?1 0.56 8.42 0.04 1.02 0.36 8. 28 8.42 2.26 2.12 10.18 10.32 ns ?2 0.49 7.39 0.03 0.90 0.32 7. 27 7.39 1.98 1.86 8.94 9.06 ns 6 ma ?f 0.79 8.93 0.05 1.44 0.51 9. 10 8.79 3.53 3.59 11.79 11.48 ns std. 0.66 7.44 0.04 1.20 0.43 7. 58 7.32 2.94 2.99 9.81 9.56 ns ?1 0.56 6.33 0.04 1.02 0.36 6. 44 6.23 2.50 2.54 8.35 8.13 ns ?2 0.49 5.55 0.03 0.90 0.32 5. 66 5.47 2.19 2.23 7.33 7.14 ns 8 ma ?f 0.79 8.93 0.05 1.44 0.51 9.10 8.79 3.53 3.59 11.79 11.48 ns std. 0.66 7.44 0.04 1.20 0.43 7. 58 7.32 2.94 2.99 9.81 9.56 ns ?1 0.56 6.33 0.04 1.02 0.36 6. 44 6.23 2.50 2.54 8.35 8.13 ns ?2 0.49 5.55 0.03 0.90 0.32 5. 66 5.47 2.19 2.23 7.33 7.14 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-61 ? 1.8 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma ?f 0.79 13.47 0.05 1.44 0.51 10.25 13.47 2.39 1.45 ns std. 0.66 11.21 0.04 1.20 0. 43 8.53 11.21 1.99 1.21 ns ?1 0.56 9.54 0.04 1.02 0. 36 7.26 9.54 1.69 1.03 ns ?2 0.49 8.37 0.03 0.90 0. 32 6.37 8.37 1.49 0.90 ns 4 ma ?f 0.79 7.62 0.05 1.44 0.51 6.46 7.62 2.89 2.98 ns std. 0.66 6.34 0.04 1.20 0.43 5.38 6.34 2.41 2.48 ns ?1 0.56 5.40 0.04 1.02 0.36 4.58 5.40 2.05 2.11 ns ?2 0.49 4.74 0.03 0.90 0.32 4.02 4.74 1.80 1.85 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-49 1.5 v lvcmos (jesd8-11) low-voltage cmos for 1.5 v is an extension of the lvcmos standard (jesd8-5) used for general- purpose 1.5 v applications. it uses a 1.5 v input buffer and a push-pull output buffer. table 2-62 ? 1.8 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma ?f 0.79 18.03 0.05 1.44 0.51 15.80 18.03 2.40 2.40 ns std. 0.66 15.01 0.04 1.20 0.43 13.15 15.01 1.99 1.99 ns ?1 0.56 12.77 0.04 1.02 0.36 11.19 12.77 1.70 1.70 ns ?2 0.49 11.21 0.03 0.90 0.32 9.82 11.21 1.49 1.49 ns 4 ma ?f 0.79 12.13 0.05 1.44 0.51 11.48 12.13 2.90 2.85 ns std. 0.66 10.10 0.04 1.20 0.43 9.55 10.10 2.41 2.37 ns ?1 0.56 8.59 0.04 1.02 0. 36 8.13 8.59 2.05 2.02 ns ?2 0.49 7.54 0.03 0.90 0. 32 7.13 7.54 1.80 1.77 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-63 ? minimum and maximum dc input and output levels applicable to advanced i/o banks 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 16 13 10 10 4 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 4 4 33 25 10 10 6 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 6 6 39 32 10 10 8 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 8 8 55 66 10 10 12 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 12 12 55 66 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. proasic3 dc and switching characteristics 2-50 v1.1 table 2-64 ? minimum and maximum dc input and output levels applicable to standard plus i/o banks 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 22 0 0 1010 4 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 4 4 0 0 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default selection highlighted in gray. table 2-65 ? minimum and maximum dc input and output levels applicable to standard i/o banks 1.5 v lvcmos v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min., v max., v min., v max., v max., v min., v ma ma max., ma 1 max., ma 1 a 2 a 2 2 ma ?0.3 0.30 * v cci 0.7 * v cci 3.6 0.25 * v cci 0.75 * v cci 2 2 13 16 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. 3. software default select ion highlighted in gray. figure 2-9 ? ac loading table 2-66 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 1.5 0.75 35 * measuring point = v trip. see table 2-18 on page 2-18 for a complete table of trip points. test point test point enable path datapath 35 pf r = 1 k r to v cci for t lz /t zl /t zls r to gnd for t hz /t zh /t zhs 35 pf for t zh /t zh s/t zl /t zls 5 pf for t hz /t lz proasic3 dc and switching characteristics v1.1 2-51 timing characteristics table 2-67 ? 1.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.79 10.05 0.05 1.73 0.51 8.20 10.05 4.07 3.32 10.88 12.73 ns std. 0.66 8.36 0.04 1.44 0.43 6. 82 8.36 3.39 2.77 9.06 10.60 ns ?1 0.56 7.11 0.04 1.22 0.36 5. 80 7.11 2.88 2.35 7.71 9.02 ns ?2 0.49 6.24 0.03 1.07 0.32 5. 10 6.24 2.53 2.06 6.76 7.91 ns 4 ma ?f 0.79 6.38 0.05 1.73 0.51 5.83 6.38 4.49 4.09 8.51 9.07 ns std. 0.66 5.31 0.04 1.44 0.43 4. 85 5.31 3.74 3.40 7.09 7.55 ns ?1 0.56 4.52 0.04 1.22 0.36 4. 13 4.52 3.18 2.89 6.03 6.42 ns ?2 0.49 3.97 0.03 1.07 0.32 3. 62 3.97 2.79 2.54 5.29 5.64 ns 6 ma ?f 0.79 5.61 0.05 1.73 0.51 5.46 5.61 4.59 4.28 8.15 8.29 ns std. 0.66 4.67 0.04 1.44 0.43 4. 55 4.67 3.82 3.56 6.78 6.90 ns ?1 0.56 3.97 0.04 1.22 0.36 3. 87 3.97 3.25 3.03 5.77 5.87 ns ?2 0.49 3.49 0.03 1.07 0.32 3. 40 3.49 2.85 2.66 5.07 5.16 ns 8 ma ?f 0.79 4.90 0.05 1.73 0.51 4.99 4.30 4.74 5.05 7.68 6.98 ns std. 0.66 4.08 0.04 1.44 0.43 4. 15 3.58 3.94 4.20 6.39 5.81 ns ?1 0.56 3.47 0.04 1.22 0.36 3. 53 3.04 3.36 3.58 5.44 4.95 ns ?2 0.49 3.05 0.03 1.07 0.32 3. 10 2.67 2.95 3.14 4.77 4.34 ns 12 ma ?f 0.79 4.90 0.05 1.73 0.51 4.99 4.30 4.74 5.05 7.68 6.98 ns std. 0.66 4.08 0.04 1.44 0.43 4.15 3.58 3.94 4.20 6.39 5.81 ns ?1 0.56 3.47 0.04 1.22 0.36 3.53 3.04 3.36 3.58 5.44 4.95 ns ?2 0.49 3.05 0.03 1.07 0.32 3.10 2.67 2.95 3.14 4.77 4.34 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-52 v1.1 table 2-68 ? 1.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to advanced i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.79 15.36 0.05 1.73 0.51 15.39 15.36 4.08 3.18 18.07 18.04 ns std. 0.66 12.78 0.04 1.44 0.43 12.81 12.78 3.40 2.64 15.05 15.02 ns ?1 0.56 10.87 0.04 1.22 0.36 10.90 10.87 2.89 2.25 12.80 12.78 ns ?2 0.49 9.55 0.03 1.07 0.32 9.57 9.55 2.54 1.97 11.24 11.22 ns 4 ma ?f 0.79 12.02 0.05 1.73 0.51 12.25 11.47 4.50 3.93 14.93 14.15 ns std. 0.66 10.01 0.04 1.44 0.43 10.19 9.55 3.75 3.27 12.43 11.78 ns ?1 0.56 8.51 0.04 1.22 0.36 8.67 8.12 3.19 2.78 10.57 10.02 ns ?2 0.49 7.47 0.03 1.07 0.32 7. 61 7.13 2.80 2.44 9.28 8.80 ns 6 ma ?f 0.79 11.21 0.05 1.73 0.51 11.42 10.68 4.60 4.12 14.11 13.37 ns std. 0.66 9.33 0.04 1.44 0.43 9. 51 8.89 3.83 3.43 11.74 11.13 ns ?1 0.56 7.94 0.04 1.22 0.36 8. 09 7.56 3.26 2.92 9.99 9.47 ns ?2 0.49 6.97 0.03 1.07 0.32 7. 10 6.64 2.86 2.56 8.77 8.31 ns 8 ma ?f 0.79 10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37 ns std. 0.66 8.91 0.04 1.44 0.43 9. 07 8.89 3.95 4.05 11.31 11.13 ns ?1 0.56 7.58 0.04 1.22 0.36 7. 72 7.57 3.36 3.44 9.62 9.47 ns ?2 0.49 6.65 0.03 1.07 0.32 6. 78 6.64 2.95 3.02 8.45 8.31 ns 12 ma ?f 0.79 10.70 0.05 1.73 0.51 10.90 10.68 4.75 4.86 13.59 13.37 ns std. 0.66 8.91 0.04 1.44 0.43 9. 07 8.89 3.95 4.05 11.31 11.13 ns ?1 0.56 7.58 0.04 1.22 0.36 7. 72 7.57 3.36 3.44 9.62 9.47 ns ?2 0.49 6.65 0.03 1.07 0.32 6. 78 6.64 2.95 3.02 8.45 8.31 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-53 table 2-69 ? 1.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.79 9.41 0.05 1.71 0.51 7.71 9.41 3.25 3.06 10.40 12.09 ns std. 0.66 7.83 0.04 1.42 0.43 6. 42 7.83 2.71 2.55 8.65 10.07 ns ?1 0.56 6.66 0.04 1.21 0.36 5. 46 6.66 2.31 2.17 7.36 8.56 ns ?2 0.49 5.85 0.03 1.06 0.32 4. 79 5.85 2.02 1.90 6.46 7.52 ns 4 ma ?f 0.79 5.81 0.05 1.71 0.51 5.39 5.81 3.64 3.76 8.08 8.50 ns std. 0.66 4.84 0.04 1.42 0.43 4.49 4.84 3.03 3.13 6.72 7.08 ns ?1 0.56 4.12 0.04 1.21 0.36 3.82 4.12 2.58 2.66 5.72 6.02 ns ?2 0.49 3.61 0.03 1.06 0.32 3.35 3.61 2.26 2.34 5.02 5.28 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-70 ? 1.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 1.4 v applicable to standard plus i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units 2 ma ?f 0.79 14.51 0.05 1.71 0.51 14.42 14.51 3.26 2.91 17.11 17.20 ns std. 0.66 12.08 0.04 1.42 0.43 12.01 12.08 2.72 2.43 14.24 14.31 ns ?1 0.56 10.27 0.04 1.21 0.36 10.21 10.27 2.31 2.06 12.12 12.18 ns ?2 0.49 9.02 0.03 1.06 0.32 8.97 9.02 2.03 1.81 10.64 10.69 ns 4 ma ?f 0.79 11.15 0.05 1.71 0.51 11.35 10.71 3.65 3.60 14.04 13.40 ns std. 0.66 9.28 0.04 1.42 0.43 9. 45 8.91 3.04 3.00 11.69 11.15 ns ?1 0.56 7.89 0.04 1.21 0.36 8. 04 7.58 2.58 2.55 9.94 9.49 ns ?2 0.49 6.93 0.03 1.06 0.32 7. 06 6.66 2.27 2.24 8.73 8.33 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-54 v1.1 3.3 v pci, 3.3 v pci-x peripheral component interface for 3.3 v standard specifies support for 33 mhz and 66 mhz pci bus applications. ac loadings are defined per the pc i/pci-x specifications for the da tapath; actel loadings for enable path characterization are described in figure 2-10 . table 2-71 ? 1.5 v lvcmos high slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma ?f 0.79 9.18 0.05 1.70 0.51 7.58 9.18 2.94 2.94 ns std. 0.66 7.65 0.04 1.42 0.43 6.31 7.65 2.45 2.45 ns ?1 0.56 6.50 0.04 1.21 0.36 5.37 6.50 2.08 2.08 ns ?2 0.49 5.71 0.03 1.06 0.32 4.71 5.71 1.83 1.83 ns notes: 1. software default select ion highlighted in gray. 2. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-72 ? 1.5 v lvcmos low slew commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard i/o banks drive strength speed grade t dout t dp t din t py t eout t zl t zh t lz t hz units 2 ma ?f 0.79 14.81 0.05 1.70 0.51 14.17 14.81 2.94 2.79 ns std. 0.66 12.33 0.04 1.42 0.43 11.79 12.33 2.45 2.32 ns ?1 0.56 10.49 0.04 1.21 0.36 10.03 10.49 2.08 1.98 ns ?2 0.49 9.21 0.03 1.06 0. 32 8.81 9.21 1.83 1.73 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-73 ? minimum and maximum dc input and output levels 3.3 v pci/pci-x v il v ih v ol v oh i ol i oh i osl i osh i il i ih drive strength min, v max, v min, v max, v max, v min, v ma ma max, ma 1 max, ma 1 a 2 a 2 per pci specification per pci curves 10 10 notes: 1. currents are measured at high temperature (100 c junction temperatur e) and maximum voltage. 2. currents are measured at 85c junction temperature. figure 2-10 ? ac loading test point enable path r to v for t /t /t cci lz zl zls 10 pf for t /t /t /t zh zhs zls zl 5 pf for t hz /t lz r to gnd for t /t /t hz zh zh s r = 1 k test point datapath r = 25 r to v cci for t dp (f) r to gnd for t dp (r) proasic3 dc and switching characteristics v1.1 2-55 ac loadings are defi ned per pci/pci-x specifications for the datapath; actel loading for tristate is described in table 2-74 . timing characteristics table 2-74 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) c load (pf) 0 3.3 0.285 * v cci for t dp(r) 0.615 * v cci for t dp(f) 10 * measuring point = v trip. see table 2-18 on page 2-18 for a complete table of trip points. table 2-75 ? 3.3 v pci/pci-x commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to advanced i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units ?f 0.79 3.22 0.05 1.04 0.51 3.28 2.34 3.86 4.30 5.97 5.03 ns std. 0.66 2.68 0.04 0.86 0.43 2. 73 1.95 3.21 3.58 4.97 4.19 ns ?1 0.56 2.28 0.04 0.73 0.36 2. 32 1.66 2.73 3.05 4.22 3.56 ns ?2 0.49 2.00 0.03 0.65 0.32 2. 04 1.46 2.40 2.68 3.71 3.13 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-76 ? 3.3 v pci/pci-x commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v applicable to standard plus i/o banks speed grade t dout t dp t din t py t eout t zl t zh t lz t hz t zls t zhs units ?f 0.79 2.77 0.05 1.02 0.51 2.82 2.05 3.35 3.87 5.51 4.73 ns std. 0.66 2.31 0.04 0.85 0.43 2. 35 1.70 2.79 3.22 4.59 3.94 ns ?1 0.56 1.96 0.04 0.72 0.36 2. 00 1.45 2.37 2.74 3.90 3.35 ns ?2 0.49 1.72 0.03 0.64 0.32 1. 76 1.27 2.08 2.41 3.42 2.94 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-56 v1.1 differential i/o characteristics physical implementation configuration of the i/o modules as a differential pair is handled by actel designer software when the user instantiates a differen tial i/o macro in the design. differential i/os can also be used in conjunction with the embedded input register (inreg), output register (outreg), enable register (enreg), and double data rate (ddr). however, there is no support for bidirectional i/os or tr istates with the lvpecl standards. lvds low-voltage differential signaling (ansi/tia/eia-644 ) is a high-speed, differential i/o standard. it requires that one data bit be carried through tw o signal lines, so two pi ns are needed. it also requires external resistor termination. the full implementation of the lvds transmitt er and receiver is shown in an example in figure 2-11 . the building blocks of the lvds transmitte r-receiver are one transmitter macro, one receiver macro, three board resistors at the transm itter end, and one resistor at the receiver end. the values for the three driv er resistors are different from those used in the lvpecl implementation because the output sta ndard specifications are different. along with lvds i/o, proasic3 also supports bus lvds structur e and multipoint lvds (m-lvds) configuration (up to 40 nodes). figure 2-11 ? lvds circuit diagram and board-level implementation table 2-77 ? minimum and maximum dc input and output levels dc parameter description min. typ. max. units v cci supply voltage 2.375 2.5 2.625 v v ol output low voltage 0.9 1.075 1.25 v v oh output high voltage 1.25 1.425 1.6 v v i input voltage 0 ? 2.925 v v odiff differential output voltage 250 350 450 mv v ocm output common-mode vo ltage 1.125 1.25 1.375 v v icm input common-mode voltage 0.05 1.25 2.35 v v idiff input differential voltage 100 350 ? mv notes: 1. 5% 2. differential input voltage = 350 mv 140 100 z 0 = 50 z 0 = 50 165 165 + ? p n p n inbuf_lvds outbuf_lvds fpga fpga bourns part number: cat16-lv4f12 proasic3 dc and switching characteristics v1.1 2-57 timing characteristics blvds/m-lvds bus lvds (blvds) and multipoint lvds (m-lvds) sp ecifications extend the existing lvds standard to high-performance mult ipoint bus applications. multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. actel lvds drivers provide the higher drive current required by blvds and m- lvds to accommodate the loading. the drivers require series terminations for better signal qua lity and to control voltage swing. termination is also required at both ends of the bus since the driver can be located anywhere on the bus. these configurations can be implemented using the tribuf_lvds and bibuf_lvds macros along with appropriate terminations. multipoint designs usin g actel lvds macros can achieve up to 200 mhz with a maximum of 20 loads. a sa mple application is given in figure 2-12 . the input and output buffer delays are available in the lvds section in table 2-79 . example: for a bus consisting of 20 equidistant loads, the following te rminations provide the required differential volt age, in worst-case industrial operating conditions, at the farthest receiver: r s =60 and r t =70 , given z 0 =50 (2") and z stub =50 (~1.5"). table 2-78 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.075 1.325 cross point * measuring point = v trip. see table 2-18 on page 2-18 for a complete table of trip points. table 2-79 ? lvds commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 2.3 v speed grade t dout t dp t din t py units ?f 0.79 2.20 0.05 1.92 ns std. 0.66 1.83 0.04 1.60 ns ?1 0.56 1.56 0.04 1.36 ns ?2 0.49 1.37 0.03 1.20 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. figure 2-12 ? blvds/m-lvds multipoint appl ication using lvds i/o buffers ... r t r t bibuf_lvds r + - t + - r + - t + - d + - en en en en en receiver transceiver receiver transceiver driver r s r s r s r s r s r s r s r s r s r s z stub z stub z stub z stub z stub z stub z stub z stub z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 z 0 proasic3 dc and switching characteristics 2-58 v1.1 lvpecl low-voltage positive emitter-coupled logic (lvpecl) is another differential i/o standard. it requires that one data bit be carried through two signal lines. like lvds, two pins are needed. it also requires external resistor termination. the full implementation of the lvds transmitt er and receiver is shown in an example in figure 2-13 . the building blocks of the lvpecl transmitt er-receiver are one tra nsmitter macro, one receiver macro, three board resistors at the transm itter end, and one resistor at the receiver end. the values for the three driver resistors are diff erent from those used in the lvds implementation because the output standard specifications are different. timing characteristics figure 2-13 ? lvpecl circuit diagram and board-level implementation table 2-80 ? minimum and maximum dc input and output levels dc parameter description min. max. min. max. min. max. units v cci supply voltage 3.0 3.3 3.6 v v ol output low voltage 0.96 1.27 1.06 1.43 1.30 1.57 v v oh output high voltage 1.8 2.11 1.92 2.28 2.13 2.41 v v il , v ih input low, input high voltages 0 3.3 0 3.6 0 3.9 v v odiff differential output voltag e 0.625 0.97 0.625 0.97 0.625 0.97 v v ocm output common-mode voltage 1 .762 1.98 1.762 1.98 1.762 1.98 v v icm input common-mode voltage 1.01 2.57 1.01 2.57 1.01 2.57 v v idiff input differential voltage 300 300 300 mv table 2-81 ? ac waveforms, measuring points, and capacitive loads input low (v) input high (v) measuring point* (v) 1.64 1.94 cross point * measuring point = v trip. see table 2-18 on page 2-18 for a complete table of trip points. 187 w 100 z 0 = 50 z 0 = 50 100 100 + ? p n p n inbuf_lvpecl outbuf_lvpecl fpga fpga bourns part number: cat16-pc4f12 table 2-82 ? lvpecl commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v, worst-case v cci = 3.0 v speed grade t dout t dp t din t py units ?f 0.79 2.16 0.05 1.69 ns std. 0.66 1.80 0.04 1.40 ns ?1 0.56 1.53 0.04 1.19 ns ?2 0.49 1.34 0.03 1.05 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-59 i/o register specifications fully registered i/o buffers with s ynchronous enable an d asynchronous preset figure 2-14 ? timing model of registered i/ o buffers with synchronous en able and asynchronous preset inbuf inbuf inbuf tribuf clkbuf inbuf inbuf clkbuf data input i/o register with: active high enable active high preset positive-edge triggered data output register and enable output register with: active high enable active high preset postive-edge triggered pad out clk enable preset data_out data eout dout enable clk dq dfn1e1p1 pre dq dfn1e1p1 pre dq dfn1e1p1 pre d_enable a b c d e e e e f g h i j l k y core array proasic3 dc and switching characteristics 2-60 v1.1 table 2-83 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register h, dout t osud data setup time for the output data register f, h t ohd data hold time for the output data register f, h t osue enable setup time for the output data register g, h t ohe enable hold time for the output data register g, h t opre2q asynchronous preset-to-q of th e output data register l, dout t orempre asynchronous preset removal time for the output data register l, h t orecpre asynchronous preset recovery time for the output data register l, h t oeclkq clock-to-q of the output enable register h, eout t oesud data setup time for the output enable register j, h t oehd data hold time for the ou tput enable register j, h t oesue enable setup time for the ou tput enable register k, h t oehe enable hold time for the output enable register k, h t oepre2q asynchronous preset-to-q of th e output enable register i, eout t oerempre asynchronous preset removal time fo r the output enable register i, h t oerecpre asynchronous preset recovery time for the output enab le register i, h t iclkq clock-to-q of the input data register a, e t isud data setup time for the input data register c, a t ihd data hold time for the input data register c, a t isue enable setup time for the input data register b, a t ihe enable hold time for the input data register b, a t ipre2q asynchronous preset-to-q of the input data register d, e t irempre asynchronous preset removal time for the input data register d, a t irecpre asynchronous preset recovery time for the input data register d, a * see figure 2-14 on page 2-59 for more information. proasic3 dc and switching characteristics v1.1 2-61 fully registered i/o buffers with s ynchronous enable an d asynchronous clear figure 2-15 ? timing model of the registered i/o buffers with synchronous enable and asynchronous clear enable clk pad out clk enable clr data_out data y aa eout dout core array dq dfn1e1c1 e clr dq dfn1e1c1 e clr dq dfn1e1c1 e clr d_e nable bb cc dd ee ff gg ll hh jj kk clkbuf inbuf inbuf tribuf inbuf inbuf clkbuf inbuf data input i/o register with active high enable active high clear positive-edge triggered data output register and enable output register with active high enable active high clear positive-edge triggered proasic3 dc and switching characteristics 2-62 v1.1 table 2-84 ? parameter definition and measuring nodes parameter name parameter definition measuring nodes (from, to)* t oclkq clock-to-q of the output data register hh, dout t osud data setup time for the output data register ff, hh t ohd data hold time for the output data register ff, hh t osue enable setup time for the output data register gg, hh t ohe enable hold time for the output data register gg, hh t oclr2q asynchronous clear-to-q of the output data register ll, dout t oremclr asynchronous clear removal time fo r the output data register ll, hh t orecclr asynchronous clear reco very time for the output data register ll, hh t oeclkq clock-to-q of the output enable register hh, eout t oesud data setup time for the ou tput enable register jj, hh t oehd data hold time for the output enable register jj, hh t oesue enable setup time for the ou tput enable register kk, hh t oehe enable hold time for the ou tput enable register kk, hh t oeclr2q asynchronous clear-to-q of the output enable register ii, eout t oeremclr asynchronous clear removal time fo r the output enab le register ii, hh t oerecclr asynchronous clear recove ry time for the output enable register ii, hh t iclkq clock-to-q of the input data register aa, ee t isud data setup time for the input data register cc, aa t ihd data hold time for the input data register cc, aa t isue enable setup time for the input data register bb, aa t ihe enable hold time for the input data register bb, aa t iclr2q asynchronous clear-to-q of the input data register dd, ee t iremclr asynchronous clear removal time for the input data register dd, aa t irecclr asynchronous clear reco very time for the inpu t data register dd, aa * see figure 2-15 on page 2-61 for more information. proasic3 dc and switching characteristics v1.1 2-63 input register timing characteristics figure 2-16 ? input register timing diagram 50% preset clear out_1 clk data enable t isue 50% 50% t isud t ihd 50% 50% t iclkq 1 0 t ihe t irecpre t irempre t irecclr t iremclr t iwclr t iwpre t ipre2q t iclr2q t ickmpwh t ickmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-85 ? input data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t iclkq clock-to-q of the input data register 0.24 0.27 0.32 0.38 ns t isud data setup time for the input data register 0.26 0.30 0.35 0.42 ns t ihd data hold time for the input data register 0.00 0.00 0.00 0.00 ns t isue enable setup time for the input data register 0.37 0.42 0.50 0.60 ns t ihe enable hold time fo r the input data regi ster 0.00 0.00 0.00 0.00 ns t iclr2q asynchronous clear-to-q of the inpu t data register 0.45 0.52 0.61 0.73 ns t ipre2q asynchronous preset-to-q of the input data regi ster 0.45 0.52 0.61 0.73 ns t iremclr asynchronous clear removal time for th e input data register 0.00 0.00 0.00 0.00 ns t irecclr asynchronous clear recovery time for the input data register 0.22 0.25 0.30 0.36 ns t irempre asynchronous preset remova l time for the input data register 0.00 0.00 0.00 0.00 ns t irecpre asynchronous preset recovery time for the input data register 0.22 0.25 0.30 0.36 ns t iwclr asynchronous clear mi nimum pulse width for the input data register 0.22 0.25 0.30 0.36 ns t iwpre asynchronous preset minimum pulse width for the input data register 0.22 0.25 0.30 0.36 ns t ickmpwh clock minimum pulse width high for the input data register 0.36 0.41 0.48 0.57 ns t ickmpwl clock minimum pulse width low for the input data register 0.32 0.37 0.43 0.52 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-64 v1.1 output register timing characteristics figure 2-17 ? output register timing diagram preset clear dout clk data_out enable t osue 50% 50% t osud t ohd 50% 50% t oclkq 1 0 t ohe t orecpre t orempre t orecclr t oremclr t owclr t owpre t opre2q t oclr2q t ockmpwh t ockmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-86 ? output data register propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t oclkq clock-to-q of the output da ta register 0.59 0.67 0.79 0.95 ns t osud data setup time for the output data register 0.31 0.36 0.42 0.50 ns t ohd data hold time for the output data register 0.00 0.00 0.00 0.00 ns t osue enable setup time for the output data register 0.44 0.50 0.59 0.70 ns t ohe enable hold time for the output data register 0.00 0.00 0.00 0.00 ns t oclr2q asynchronous clear-to-q of the out put data register 0.80 0.91 1.07 1.29 ns t opre2q asynchronous preset-to-q of the outp ut data register 0.80 0.91 1.07 1.29 ns t oremclr asynchronous clear removal time for the output data register 0.00 0.00 0.00 0.00 ns t orecclr asynchronous clear recovery time for th e output data register 0.22 0.25 0.30 0.36 ns t orempre asynchronous preset removal time for th e output data register 0.00 0.00 0.00 0.00 ns t orecpre asynchronous preset recovery time for th e output data register 0.22 0.25 0.30 0.36 ns t owclr asynchronous clear minimum pulse width for the output data register 0.22 0.25 0.30 0.36 ns t owpre asynchronous preset minimum pu lse width for the output data register 0.22 0.25 0.30 0.36 ns t ockmpwh clock minimum pulse width high for the output data register 0.36 0.41 0.48 0.57 ns t ockmpwl clock minimum pulse width low for the output data register 0.32 0.37 0.43 0.52 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-65 output enable register figure 2-18 ? output enable regist er timing diagram 50% preset clear eout clk d_enable enable t oesue 50% 50% t oesud t oehd 50% 50% t oeclkq 1 0 t oehe t oerecpre t oerempre t oerecclr t oeremclr t oewclr t oewpre t oepre2q t oeclr2q t oeckmpwh t oeckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% proasic3 dc and switching characteristics 2-66 v1.1 timing characteristics table 2-87 ? output enable regist er propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t oeclkq clock-to-q of the output enab le register 0.59 0.67 0.79 0.95 ns t oesud data setup time for the output enable register 0.31 0.36 0.42 0.50 ns t oehd data hold time for the output enable register 0.00 0.00 0.00 0.00 ns t oesue enable setup time for the output enable register 0.44 0.50 0.58 0.70 ns t oehe enable hold time for the output enable register 0. 00 0.00 0.00 0.00 ns t oeclr2q asynchronous clear-to-q of the output enable register 0.67 0.76 0.89 1.07 ns t oepre2q asynchronous preset-to-q of the outp ut enable register 0.67 0.76 0.89 1.07 ns t oeremclr asynchronous clear removal time for the output enable regist er 0.00 0.00 0.00 0.00 ns t oerecclr asynchronous clear recovery time for the output enable regist er 0.22 0.25 0.30 0.36 ns t oerempre asynchronous preset removal time for the output enable regist er 0.00 0.00 0.00 0.00 ns t oerecpre asynchronous preset recovery time for th e output enable regi ster 0.22 0.25 0.30 0.36 ns t oewclr asynchronous clear minimum puls e width for the output enable register 0.22 0.25 0.30 0.36 ns t oewpre asynchronous preset minimum pu lse width for th e output enable register 0.22 0.25 0.30 0.36 ns t oeckmpwh clock minimum pulse width high for the ou tput enable register 0.36 0.41 0.48 0.57 ns t oeckmpwl clock minimum pulse width low for the ou tput enable register 0.32 0.37 0.43 0.52 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-67 ddr module specifications input ddr module figure 2-19 ? input ddr timing model table 2-88 ? parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddriclkq1 clock-to-out out_qr b, d t ddriclkq2 clock-to-out out_qf b, e t ddrisud data setup time of ddr input a, b t ddrihd data hold time of ddr input a, b t ddriclr2q1 clear-to-out out_qr c, d t ddriclr2q2 clear-to-out out_qf c, e t ddriremclr clear removal c, b t ddrirecclr clear recovery c, b input ddr data clk clkbuf inbuf out_qf (to core) ff2 ff1 inbuf clr ddr_in e a b c d out_qr (to core) proasic3 dc and switching characteristics 2-68 v1.1 timing characteristics figure 2-20 ? input ddr timing diagram t ddriclr2q2 t ddriremclr t ddrirecclr t ddriclr2q1 12 3 4 5 6 7 8 9 clk data clr out_qr out_qf t ddriclkq1 2 4 6 3 5 7 t ddrihd t ddrisud t ddriclkq2 table 2-89 ? input ddr propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ddriclkq1 clock-to-out out_qr for input ddr 0.39 0.44 0.52 0.62 ns t ddriclkq2 clock-to-out out_qf for input ddr 0.27 0.31 0.37 0.44 ns t ddrisud data setup for input ddr 0.28 0.32 0.38 0.45 ns t ddrihd data hold for input ddr 0.00 0.00 0.00 0.00 ns t ddriclr2q1 asynchronous clear-to-out out_qr for input ddr 0.57 0.65 0.76 0.92 ns t ddriclr2q2 asynchronous clear-to-out out_qf for input ddr 0.46 0.53 0.62 0.74 ns t ddriremclr asynchronous clear removal time for input ddr 0.00 0.00 0.00 0.00 ns t ddrirecclr asynchronous clear re covery time for input ddr 0.22 0.25 0.30 0.36 ns t ddriwclr asynchronous clear minimum pulse width for input ddr 0.22 0.25 0.30 0.36 ns t ddrickmpwh clock minimum pulse width high for input ddr 0.36 0.41 0.48 0.57 ns t ddrickmpwl clock minimum pulse width low for input ddr 0.32 0.37 0.43 0.52 ns f ddrimax maximum frequency for input ddr tbd tbd tbd tbd mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-69 output ddr module figure 2-21 ? output ddr timing model table 2-90 ? parameter definitions parameter name parameter definiti on measuring nodes (from, to) t ddroclkq clock-to-out b, e t ddroclr2q asynchronous clear-to-out c, e t ddroremclr clear removal c, b t ddrorecclr clear recovery c, b t ddrosud1 data setup data_f a, b t ddrosud2 data setup data_r d, b t ddrohd1 data hold data_f a, b t ddrohd2 data hold data_r d, b data_f (from core) clk clkbuf out ff2 inbuf clr ddr_out output ddr ff1 0 1 x x x x x x x x a b d e c c b outbuf data_r (from core) proasic3 dc and switching characteristics 2-70 v1.1 timing characteristics figure 2-22 ? output ddr timing diagram 11 6 1 7 2 8 3 910 45 28 3 9 t ddroremclr t ddrohd1 t ddroremclr t ddrohd2 t ddrosud2 t ddroclkq t ddrorecclr clk data_r data_f clr out t ddroclr2q 710 4 table 2-91 ? output ddr propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ddroclkq clock-to-out of ddr for output ddr 0.70 0.80 0.94 1.13 ns t ddrosud1 data_f data setup for output ddr 0.38 0.43 0.51 0.61 ns t ddrosud2 data_r data setup for output ddr 0.38 0.43 0.51 0.61 ns t ddrohd1 data_f data hold for output ddr 0.00 0.00 0.00 0.00 ns t ddrohd2 data_r data hold for output ddr 0.00 0.00 0.00 0.00 ns t ddroclr2q asynchronous clear-to-out fo r output ddr 0.80 0.91 1.07 1.29 ns t ddroremclr asynchronous clear removal time for output ddr 0.00 0.00 0.00 0.00 ns t ddrorecclr asynchronous clear recovery time for output ddr 0.22 0.25 0.30 0.36 ns t ddrowclr1 asynchronous clear minimum pulse widt h for output ddr 0.22 0.25 0.30 0.36 ns t ddrockmpwh clock minimum pulse width high fo r the output ddr 0.36 0.41 0.48 0.57 ns t ddrockmpwl clock minimum pulse width low for the output ddr 0.32 0.37 0.43 0.52 ns f ddomax maximum frequency for the output ddr tbd tbd tbd tbd mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-71 versatile characteristics versatile specifications as a combinatorial module the proasic3 library offers all combinations of lut-3 combinatorial functions. in this section, timing characteristics are presented for a sample of the libr ary. for more details, refer to the fusion, igloo/e, and proasi c3/e macro library guide . figure 2-23 ? sample of combinatorial cells maj3 a c by mux2 b 0 1 a s y ay b b a xor2 y nor2 b a y b a y or2 inv a y and2 b a y nand3 b a c xor3 y b a c nand2 proasic3 dc and switching characteristics 2-72 v1.1 figure 2-24 ? timing model and waveforms t pd a b t pd = max(t pd(rr) , t pd(rf) , t pd(ff) , t pd(fr) ) where edges are applicable for the particular combinatorial cell y nand2 or any combinatorial logic t pd t pd 50% v cc v cc v cc 50% gnd a, b, c 50% 50% 50% (rr) (rf) gnd out out gnd 50% (ff) (fr) t pd t pd proasic3 dc and switching characteristics v1.1 2-73 timing characteristics versatile specifications as a sequential module the proasic3 library offers a wide variety of sequential cells, including flip-flops and latches. each has a data input and optional enable, clear, or pres et. in this section, ti ming characteristics are presented for a representative sample from the library. for more details, refer to the fusion, igloo/e, and proasic3/e macro library guide . table 2-92 ? combinatorial cell propagation delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v combinatorial cell equation parameter ?2 ?1 std. ?f units inv y = !a t pd 0.40 0.46 0.54 0.65 ns and2 y = a b t pd 0.47 0.54 0.63 0.76 ns nand2 y = !(a b) t pd 0.47 0.54 0.63 0.76 ns or2 y = a + b t pd 0.49 0.55 0.65 0.78 ns nor2 y = !(a + b) t pd 0.49 0.55 0.65 0.78 ns xor2 y = a bt pd 0.74 0.84 0.99 1.19 ns maj3 y = maj(a , b, c) t pd 0.70 0.79 0.93 1.12 ns xor3 y = a b ct pd 0.87 1.00 1.17 1.41 ns mux2 y = a !s + b s t pd 0.51 0.58 0.68 0.81 ns and3 y = a b c t pd 0.56 0.64 0.75 0.90 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. figure 2-25 ? sample of sequential cells dq dfn1 data clk out d q dfn1c1 data clk out clr dq dfi1e1p1 data clk out en pre d q dfn1e1 data clk out en proasic3 dc and switching characteristics 2-74 v1.1 timing characteristics figure 2-26 ? timing model and waveforms pre clr out clk data en t sue 50% 50% t sud t hd 50% 50% t clkq 0 t he t recpre t rempre t recclr t remclr t wclr t wpre t pre2q t clr2q t ckmpwh t ckmpwl 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% table 2-93 ? register delays commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t clkq clock-to-q of the core register 0.55 0.63 0.74 0.89 ns t sud data setup time for the core register 0.43 0.49 0.57 0.69 ns t hd data hold time for the core register 0.00 0.00 0.00 0.00 ns t sue enable setup time for the co re register 0.45 0.52 0.61 0.73 ns t he enable hold time for the core register 0.00 0.00 0.00 0.00 ns t clr2q asynchronous clear-to-q of the core register 0.40 0.45 0.53 0.64 ns t pre2q asynchronous preset-to-q of the core register 0.40 0.45 0.53 0.64 ns t remclr asynchronous clear removal time for the core register 0.00 0.00 0.00 0.00 ns t recclr asynchronous clear recovery time fo r the core register 0.22 0.25 0.30 0.36 ns t rempre asynchronous preset removal time fo r the core register 0.00 0.00 0.00 0.00 ns t recpre asynchronous preset recovery time fo r the core register 0.22 0.25 0.30 0.36 ns t wclr asynchronous clear minimum pulse width for the core regist er 0.22 0.25 0.30 0.36 ns t wpre asynchronous preset minimum pulse width for the core register 0.22 0.25 0.30 0.36 ns t ckmpwh clock minimum pulse width high for the core register 0.32 0.37 0.43 0.52 ns t ckmpwl clock minimum pulse width low for th e core register 0.36 0.41 0.48 0.57 ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-75 global resource characteristics a3p250 clock tree topology clock delays are device-specific. figure 2-27 is an example of a global tree used for clock routing. the global tree presented in figure 2-27 is driven by a ccc located on the west side of the a3p250 device. it is used to drive al l d-flip-flops in the device. figure 2-27 ? example of global tree use in an a3p250 device for clock routing central global rib versatile rows global spine ccc proasic3 dc and switching characteristics 2-76 v1.1 global tree timing characteristics global clock delays include the central rib delay, the spine delay, and the row delay. delays do not include i/o input buffer clock delays, as these are i/o standard?dependent, and the clock may be driven and conditioned internally by the ccc module. for more details on clock conditioning capabilities, refer to the "clock conditioning circuits" section on page 2-80 . table 2-94 to table 2-100 on page 2-79 present minimum and maximum global clock delays within each device. minimum and maximum delays are measur ed with minimum an d maximum loading. timing characteristics table 2-94 ? a3p030 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.67 0.81 0.76 0.92 0.89 1.09 1.07 1.31 ns t rckh input high delay for gl obal clock 0.680.850.770.970.911.141.091.37 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.18 0.21 0.24 0.29 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-95 ? a3p060 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.71 0.93 0.81 1.05 0.95 1.24 1.14 1.49 ns t rckh input high delay for gl obal clock 0.700.960.801.090.941.281.131.54 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.29 0.34 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-77 table 2-96 ? a3p125 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.77 0.99 0.87 1.12 1.03 1.32 1.24 1.58 ns t rckh input high delay for gl obal clock 0.761.020.871.161.021.371.231.64 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.29 0.34 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-97 ? a3p250 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.80 1.01 0.91 1.15 1.07 1.36 1.28 1.63 ns t rckh input high delay for gl obal clock 0.781.040.891.181.041.391.251.66 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.29 0.34 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-78 v1.1 table 2-98 ? a3p400 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns t rckh input high delay for gl obal clock 0.861.110.981.271.151.491.381.79 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.29 0.34 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. table 2-99 ? a3p600 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.87 1.09 0.99 1.24 1.17 1.46 1.40 1.75 ns t rckh input high delay for gl obal clock 0.861.110.981.271.151.491.381.79 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.29 0.34 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-79 table 2-100 ? a3p1000 global resource commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 min. 1 max. 2 t rckl input low delay for global clock 0.94 1.16 1.07 1.32 1.26 1.55 1.51 1.86 ns t rckh input high delay for gl obal clock 0.931.191.061.351.241.591.491.91 ns t rckmpwh minimum pulse width high for global clock ns t rckmpwl minimum pulse width low for global clock ns t rcksw maximum skew for global clock 0.26 0.29 0.35 0.41 ns f rmax maximum frequency for global clock mhz notes: 1. value reflects minimum load . the delay is measured from the ccc ou tput to the clock pin of a sequential element, located in a lightly loaded row (sin gle element is connected to the global net). 2. value reflects maximum load . the delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-f lops are connected to th e global net in the row). 3. for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-80 v1.1 clock conditioning circuits ccc electrical specifications timing characteristics table 2-101 ? proasic3 ccc/pll specification parameter minimum typical maximum units clock conditioning circuitry input frequency f in_ccc 1.5 350 mhz clock conditioning circuitry output frequency f out_ccc 0.75 350 mhz serial clock (sclk) for dynamic pll 1 125 mhz delay increments in programmable delay blocks 2, 3 160 ps number of programmable values in each programmable delay block 32 input period jitter 1.5 ns ccc output peak-to-p eak period jitter f ccc_out max peak-to-peak period jitter 1 global network used 3 global networks used 0.75 mhz to 24 mhz 0.50% 0.70% 24 mhz to 100 mhz 1.00% 1.20% 100 mhz to 250 mhz 1.75% 2.00% 250 mhz to 350 mhz 2.50% 5.60% acquisition time (a3p250 and a3p1000 only) lockcontrol = 0 300 s lockcontrol = 1 300 s (all other dies) lockcontrol = 0 300 s lockcontrol = 1 6.0 ms tracking jitter 5 (a3p250 and a3p1000 only) lockcontrol = 0 1.6 ns lockcontrol = 1 1.6 ns (all other dies) lockcontrol = 0 1.6 ns lockcontrol = 1 0.8 ns output duty cycle 48.5 51.5 % delay range in block: programmable delay 1 2, 3 0.6 5.56 ns delay range in block: programmable delay 2 2, 3 0.025 5.56 ns delay range in block: fixed delay 2, 3 2.2 ns notes: 1. maximum value obtained fo r a ?2 speed-grade device in worst-ca se commercial conditions. for specific junction temperature and volt age supply levels, refer to table 2-6 on page 2-6 for derating values. 2. this delay is a function of voltage and temperature. see table 2-6 on page 2-6 for deratings. 3. t j = 25c, v cc = 1.5 v 4. the a3p030 device do es not contain a pll. 5. tracking jitter is defined as the va riation in clock edge position of p ll outputs with reference to the pll input clock edge. tracking jitter does not measure th e variation in pll output period, which is covered by the period jitter parameter. proasic3 dc and switching characteristics v1.1 2-81 note: peak-to-peak jitter measurements are defined by t peak-to-peak = t period_max ? t period_min . figure 2-28 ? peak-to-peak jitter definition t perio d _max t perio d _min output s i g nal proasic3 dc and switching characteristics 2-82 v1.1 embedded sram and fifo characteristics sram figure 2-29 ? ram models addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset proasic3 dc and switching characteristics v1.1 2-83 timing waveforms figure 2-30 ? ram read for pass-through output figure 2-31 ? ram read for pipelined output clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 d 2 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh1 t bkh d n t ckq1 clk add blk_b wen_b do a 0 a 1 a 2 d 0 d 1 t cyc t ckh t ckl t as t ah t bks t ens t enh t doh2 t ckq2 t bkh d n proasic3 dc and switching characteristics 2-84 v1.1 figure 2-32 ? ram write, output retained (wmode = 0) figure 2-33 ? ram write, output as write data (wmode = 1) t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t enh t ds t dh clk blk_b wen_b add di d n do t bkh d 2 t cyc t ckh t ckl a 0 a 1 a 2 di 0 di 1 t as t ah t bks t ens t ds t dh clk blk_b wen_b add di t bkh do (pass-through) di 1 d n di 0 do (pipelined) di 0 di 1 d n di 2 proasic3 dc and switching characteristics v1.1 2-85 figure 2-34 ? write access after write onto same address c lk1 c lk2 wen_b1 wen_b2 add1 add2 di1 di2 do2 (pass-throu g h) do2 (pipeline d ) a 0 t ah t a s t ah t a s t dh t cc kh t d s t c kq1 t c kq2 d 1 a 1 d 2 a 3 d 3 a 0 d 0 d n d 0 d n d 0 a 0 a 4 d 4 proasic3 dc and switching characteristics 2-86 v1.1 figure 2-35 ? read access after write onto same address c lk1 c lk2 wen_b1 wen_b2 add1 add2 di1 do2 (pass-throu g h) do2 (pipeline d ) a 0 t ah t a s t ah t a s t dh t d s t wro t c kq1 t c kq2 d 0 a 0 a 1 a 4 d n d n d 0 d 0 d 1 a 2 d 2 a 3 d 3 proasic3 dc and switching characteristics v1.1 2-87 figure 2-36 ? write access after read onto same address figure 2-37 ? ram reset a 0 a 1 a 0 a 0 a 1 a 3 d 1 d 2 d 3 t ah t a s t ah t a s t c kq1 t c kq1 t c kq2 t cc kh c lk1 add1 wen_b1 do1 (pass-throu g h) do1 (pipeline d ) c lk2 add2 di2 wen_b2 d n d n d 0 d 1 d 0 clk reset_b do d n t cyc t ckh t ckl t rstbq d m proasic3 dc and switching characteristics 2-88 v1.1 timing characteristics table 2-102 ? ram4k9 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t as address setup time 0.25 0.28 0.33 0.40 ns t ah address hold time 0.00 0.00 0.00 0.00 ns t ens ren_b, wen_b setup time 0.14 0.16 0.19 0.23 ns t enh ren_b, wen_b hold time 0.10 0.11 0.13 0.16 ns t bks blk_b setup time 0. 23 0.27 0.31 0.37 ns t bkh blk_b hold time 0.02 0.02 0.02 0.03 ns t ds input data (di) setup time 0.18 0.21 0.25 0.29 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 2.36 2.68 3.15 3.79 ns clock high to new data valid on do (flow-t hrough, wmode = 1) 1.79 2.03 2.39 2.87 ns t ckq2 clock high to new data valid on do (pipelined) 0.89 1.02 1.20 1.44 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbdtbdtbdtbd ns t cckh address collision clk-to-clk delay for reliable write access after write/read on same address tbdtbdtbdtbd ns t rstbq reset_b low to data out low on do (flow-through) 0. 92 1.05 1.23 1.48 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 1.48 ns t remrstb reset_b removal 0.29 0.33 0.38 0.46 ns t recrstb reset_b recovery 1. 50 1.71 2.01 2.41 ns t mpwrstb reset_b minimum pulse widt h 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 3.23 3.68 4.32 5.19 ns f max maximum frequency 310 272 231 193 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-89 table 2-103 ? ram512x18 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. ?f units t as address setup time 0.25 0.28 0.33 0.40 ns t ah address hold time 0.00 0.00 0.00 0.00 ns t ens ren_b, wen_b setup time 0.13 0.15 0.17 0.21 ns t enh ren_b, wen_b hold time 0.10 0.11 0.13 0.16 ns t ds input data (di) setup time 0.18 0.21 0.25 0.29 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (output retained, wmode = 0) 2.16 2.46 2.89 3.47 ns t ckq2 clock high to new data valid on do (pipelined) 0.90 1.02 1.20 1.44 ns t wro address collision clk-to-clk delay for reliable read access after write on same address tbdtbdtbdtbd ns t cckh address collision clk-to-clk delay for reliable write access after write/read on same address tbdtbdtbdtbd ns t rstbq reset_b low to data out low on do (flow-through) 0. 92 1.05 1.23 1.48 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 1.48 ns t remrstb reset_b removal 0.29 0.33 0.38 0.46 ns t recrstb reset_b recovery 1. 50 1.71 2.01 2.41 ns t mpwrstb reset_b minimum pulse widt h 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 3.23 3.68 4.32 5.19 ns f max maximum frequency 310 272 231 193 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-90 v1.1 fifo figure 2-38 ? fifo model fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset proasic3 dc and switching characteristics v1.1 2-91 timing waveforms figure 2-39 ? fifo reset figure 2-40 ? fifo empty flag and aempty flag assertion match (a 0 ) t mpwrstb t rstfg t rstck t rstaf rclk/ wclk reset_b empty aempty wa/ra (address counter) t rstfg t rstaf full afull rclk no match no match dist = aef_th match (empty) t ckaf t rckef empty aempty t cyc wa/ra (address counter) proasic3 dc and switching characteristics 2-92 v1.1 figure 2-41 ? fifo full flag and afull flag assertion figure 2-42 ? fifo empty flag and ae mpty flag deassertion figure 2-43 ? fifo full flag and afull flag deassertion no match no match dist = aff_th match (full) t ckaf t wckff t cyc wclk full afull wa/ra (address counter) wclk wa/ra (address counter) match (empty) no match no match no match dist = aef_th + 1 no match rclk empty 1st rising edge after 1st write 2nd rising edge after 1st write t rckef t ckaf aempty dist = aff_th ? 1 match (full) no match no match no match no match t wckf t ckaf 1st rising edge after 1st read 1st rising edge after 2nd read rclk wa/ra (address counter) wclk full afull proasic3 dc and switching characteristics v1.1 2-93 timing characteristics table 2-104 ? fifo (for all dies except a3p250) worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ens ren_b, wen_b setup ti me 1.34 1.52 1.79 2.15 ns t enh ren_b, wen_b hold ti me 0.00 0.00 0.00 0.00 ns t bks blk_b setup time 0.19 0.22 0.26 0.31 ns t bkh blk_b hold time 0. 00 0.00 0.00 0.00 ns t ds input data (di) setup time 0.18 0.21 0.25 0.29 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.17 2.47 2.90 3.48 ns t ckq2 clock high to new data valid on do (pipelined) 0.94 1.07 1.26 1.52 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 2.76 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 2.62 ns t ckaf clock high to almost empty/full flag valid 6.19 7.05 8.29 9.96 ns t rstfg reset_b low to empty/full flag valid 1.69 1.93 2.27 2.72 ns t rstaf reset_b low to almost empty/full flag valid 6.13 6.98 8.20 9.85 ns t rstbq reset_b low to data out low on do (flow-through) 0.9 21.051.231.48 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 1.48 ns t remrstb reset_b removal 0.29 0.33 0.38 0.46 ns t recrstb reset_b recovery 1. 50 1.71 2.01 2.41 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 3. 23 3.68 4.32 5.19 ns f max maximum frequency for fifo 310 272 231 193 mhz note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics 2-94 v1.1 table 2-105 ? fifo (for a3p250 only, aspect-ratio-dependent) worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ens ren_b, wen_b setup ti me 3.26 3.71 4.36 5.24 ns t enh ren_b, wen_b hold ti me 0.00 0.00 0.00 0.00 ns t bks blk_b setup time 0.19 0.22 0.26 0.31 ns t bkh blk_b hold time 0. 00 0.00 0.00 0.00 ns t ds input data (di) setup time 0.18 0.21 0.25 0.29 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.17 2.47 2.90 3.48 ns t ckq2 clock high to new data valid on do (pipelined) 0.94 1.07 1.26 1.52 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 2.76 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 2.62 ns t ckaf clock high to almost empty/full flag valid 6.19 7.05 8.29 9.96 ns t rstfg reset_b low to empty/full flag valid 1.69 1.93 2.27 2.72 ns t rstaf reset_b low to almost empty/full flag valid 6.13 6.98 8.20 9.85 ns t rstbq reset_b low to data out low on do (flow-through) 0.9 21.051.231.48 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 1.48 ns t remrstb reset_b removal 0.29 0.33 0.38 0.46 ns t recrstb reset_b recovery 1. 50 1.71 2.01 2.41 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 3. 23 3.68 4.32 5.19 ns f max maximum frequency for fifo 310 272 231 193 mhz proasic3 dc and switching characteristics v1.1 2-95 table 2-106 ? a3p250 fifo 5128 worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ens ren_b, wen_b setup ti me 3.75 4.27 5.02 6.04 ns t enh ren_b, wen_b hold ti me 0.00 0.00 0.00 0.00 ns t bks blk_b setup time 0.19 0.22 0.26 0.31 ns t bkh blk_b hold time 0. 00 0.00 0.00 0.00 ns t ds input data (di) setup time 0.18 0.21 0.25 0.29 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.17 2.47 2.90 3.48 ns t ckq2 clock high to new data valid on do (pipelined) 0.94 1.07 1.26 1.52 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 2.76 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 2.62 ns t ckaf clock high to almost empty/full flag valid 6.19 7.05 8.29 9.96 ns t rstfg reset_b low to empty/full flag valid 1.69 1.93 2.27 2.72 ns t rstaf reset_b low to almost empty/full flag valid 6.13 6.98 8.20 9.85 ns t rstbq reset_b low to data out low on do (flow-through) 0.9 21.051.231.48 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 1.48 ns t remrstb reset_b removal 0.29 0.33 0.38 0.46 ns t recrstb reset_b recovery 1. 50 1.71 2.01 2.41 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 3. 23 3.68 4.32 5.19 ns f max maximum frequency for fifo 310 272 231 193 mhz proasic3 dc and switching characteristics 2-96 v1.1 table 2-107 ? a3p250 fifo 1k4 worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ens ren_b, wen_b setup time 4.05 4.61 5.42 6.52 ns t enh ren_b, wen_b hold time 0.00 0.00 0.00 0.00 ns t bks blk_b setup time 0.19 0.22 0.26 0.31 ns t bkh blk_b hold time 0.00 0.00 0.00 0.00 ns t ds input data (di) setup time 0.18 0.21 0.25 0.29 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.36 2.68 3.15 3.79 ns t ckq2 clock high to new data valid on do (pipelined) 0.89 1.02 1.20 1.44 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 2.76 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 2.62 ns t ckaf clock high to almost empty/full flag valid 6.19 7.05 8.29 9.96 ns t rstfg reset_b low to empty/full fl ag valid 1.69 1.93 2.27 2.72 ns t rstaf reset_b low to almost empty/full flag valid 6.13 6.98 8.20 9.85 ns t rstbq reset_b low to data out low on do (flow-through) 0.92 1.05 1.23 1.48 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 1.48 ns t remrstb reset_b removal 0.29 0.33 0.38 0.46 ns t recrstb reset_b recovery 1.50 1.71 2.01 2.41 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 3.23 3.68 4.32 5.19 ns f max maximum frequency for fifo 310 272 231 193 mhz proasic3 dc and switching characteristics v1.1 2-97 table 2-108 ? a3p250 fifo 2k2 worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ens ren_b, wen_b setup ti me 4.39 5.00 5.88 7.06 ns t enh ren_b, wen_b hold ti me 0.00 0.00 0.00 0.00 ns t bks blk_b setup time 0.19 0.22 0.26 0.31 ns t bkh blk_b hold time 0.00 0.00 0.00 0.00 ns t ds input data (di) setup time 0.18 0.21 0.25 0.29 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.36 2.68 3.15 3.79 ns t ckq2 clock high to new data valid on do (pipelined) 0.89 1.02 1.20 1.44 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 2.76 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 2.62 ns t ckaf clock high to almost empty/full flag valid 6.19 7.05 8.29 9.96 ns t rstfg reset_b low to empty/full flag valid 1.69 1.93 2.27 2.72 ns t rstaf reset_b low to almost empty/full flag valid 6.13 6.98 8.20 9.85 ns t rstbq reset_b low to data out low on do (flow-through) 0.92 1.05 1.23 1.48 ns reset_b low to data out low on do (pipelined) 0.92 1.05 1.23 1.48 ns t remrstb reset_b removal 0.29 0.33 0.38 0.46 ns t recrstb reset_b recovery 1.50 1.71 2.01 2.41 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 3.23 3.68 4.32 5.19 ns f max maximum frequency for fifo 310 272 231 193 mhz proasic3 dc and switching characteristics 2-98 v1.1 table 2-109 ? a3p250 fifo 4k1 worst commercial-case conditions: t j = 70c, v cc = 1.425 v parameter description ?2 ?1 std. ?f units t ens ren_b, wen_b setup time 4.86 5.53 6.50 7.81 ns t enh ren_b, wen_b hold time 0.00 0.00 0.00 0.00 ns t bks blk_b setup time 0.19 0.22 0.26 0.31 ns t bkh blk_b hold time 0.00 0.00 0.00 0.00 ns t ds input data (di) setup time 0.18 0.21 0.25 0.29 ns t dh input data (di) hold time 0.00 0.00 0.00 0.00 ns t ckq1 clock high to new data valid on do (flow-through) 2.36 2.68 3.15 3.79 ns t ckq2 clock high to new data valid on do (pipelined) 0.89 1.02 1.20 1.44 ns t rckef rclk high to empty flag valid 1.72 1.96 2.30 2.76 ns t wckff wclk high to full flag valid 1.63 1.86 2.18 2.62 ns t ckaf clock high to almost empty/fu ll flag valid 6.19 7.05 8.29 9.96 ns t rstfg reset_b low to empt y/full flag valid 1.69 1.93 2.27 2.72 ns t rstaf reset_b low to al most empty/full flag valid 6.13 6.98 8.20 9.85 ns t rstbq reset_b low to data ou t low on do (pass-through) 0.92 1.05 1.23 1.48 ns reset_b low to data ou t low on do (pipelined) 0.92 1.05 1.23 1.48 ns t remrstb reset_b removal 0.29 0.33 0.38 0.46 ns t recrstb reset_b recovery 1.50 1.71 2.01 2.41 ns t mpwrstb reset_b minimum pulse width 0.21 0.24 0.29 0.34 ns t cyc clock cycle time 3.23 3.68 4.32 5.19 ns f max maximum frequency 310 272 231 193 mhz proasic3 dc and switching characteristics v1.1 2-99 embedded flashrom characteristics timing characteristics figure 2-44 ? timing diagram a 0 a 1 t s u t hold t s u t hold t s u t hold t c kq2 t c kq2 t c kq2 c lk a dd ress data d 0 d 0 d 1 table 2-110 ? embedded flashrom access time parameter description ?2 ?1 std. units t su address setup time 0.53 0.61 0.71 ns t hold address hold time 0.00 0.00 0.00 ns t ck2q clock to out 21.42 24.40 28.68 ns f max maximum clock frequency 15 15 15 mhz proasic3 dc and switching characteristics 2-100 v1.1 jtag 1532 characteristics jtag timing delays do not include jtag i/os. to obtain complete jtag timing, add i/o buffer delays to the corresponding standard selected; refer to the i/o timing ch aracteristics in the "user i/o characteristics" section on page 2-13 for more details. timing characteristics table 2-111 ? jtag 1532 commercial-case conditions: t j = 70c, worst-case v cc = 1.425 v parameter description ?2 ?1 std. units t disu test data input setup time 0.50 0.57 0.67 ns t dihd test data input hold time 1.00 1.13 1.33 ns t tmssu test mode select setup time 0.50 0.57 0.67 ns t tmdhd test mode select hold time 1.00 1.13 1.33 ns t tck2q clock to q (data out) 6.00 6.80 8.00 ns t rstb2q reset to q (data out) 20.00 22.67 26.67 ns f tckmax tck maximum frequency 25.00 22.00 19.00 mhz t trstrem resetb removal time 0.00 0.00 0.00 ns t trstrec resetb recovery time 0.20 0.23 0.27 ns t trstmpw resetb minimum pulse tbd tbd tbd ns note: for specific junction temperature and voltage supply levels, refer to table 2-6 on page 2-6 for derating values. proasic3 dc and switching characteristics v1.1 2-101 part number and revision date part number 51700097-002-1 revised january 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) in table 2-2 recommended operating conditions , t j was listed in the symbol column and was incorrect. it wa s corrected and changed to t a . 2-2 in table 2-3 flash programming limits ? retention, storage and operating temperature1 , maximum operating junction temperature was changed from 110c to 100c for both commer cial and industrial grades. 2-2 the "pll behavior at browno ut condition" section is new. 2-3 in the "pll contribution?ppll" section , the following was deleted: fclkin is the input clock frequency. 2-11 in table 2-17 summary of maximum and minimum dc input levels , the note was incorrect. it previously said t j and it was corrected and changed to t a . 2-18 in table 2-101 proasic3 cc c/pll specification , the sclk parameter and note 1 are new. 2-80 table 2-111 jtag 1532 was populated with the parameter data, which was not in the previous version of the document. 2-100 v2.2 (july 2007) this document was previously in datash eet v2.2. as a result of moving to the handbook format, actel restarted the version numbers so the new version number is v1.0. n/a v2.1 (may 2007) the t j parameter in table 3-2 ? recomme nded operating conditions was changed to t a , ambient temperature, and table notes 4?6 were added. 3-2 v2.0 (april 2007) table 3-5 ? package thermal resist ivities was updated with a3p1000 information. the note belo w the table is also new. 3-5 the timing characteristics tables were updated. n/a the "pll macro" section was updated to add information on the vco and pll outputs during power-up. 2-15 advanced v0.7 (january 2007) the "pll macro" section was updated to include power-up information. 2-15 table 2-11 ? proasic3 ccc/pll specification was updated. 2-29 figure 2-19 ? peak-to-peak ji tter definition is new. 2-18 the "sram and fifo" section was updated with operation and timing requirement information. 2-21 the "reset" section was updated with read and write information. 2-25 the "reset" section was updated with read and write information. 2-25 the"introduction" in the "advanced i/os" section was updated to include information on input and outp ut buffers being disabled. 2-28 pci-x 3.3 v was added to table 2-11 ? vcci voltages and compatible standards. 2-29 in the table 2-15 ? levels of hot-swap support, the proasic3 compliance descriptions were upda ted for levels 3 and 4. 2-34 proasic3 dc and switching characteristics 2-102 v1.1 advanced v0.7 (continued) table 2-43 ? i/o hot-swap and 5 v input tolerance capabilities in proasic3 devices was updated. 2-64 notes 3, 4, and 5 were added to table 2-17 ? comparison table for 5 v? compliant receiver scheme . 5 x 52.72 was changed to 52.7 and the maximum current was updated from 4 x 52.7 to 5 x 52.7. 2-40 the "vccplf pll supply volt age" section was updated. 2-50 the "vpump programming supply voltage" section was updated. 2-50 the "gl globals" section was updated to include information about direct input into quadrant clocks. 2-51 v jtag was deleted from the "tck test clock" section. 2-51 in table 2-22 ? recommended tie-off va lues for the tck and trst pins, tsk was changed to tck in note 2. note 3 was also updated. 2-51 ambient was deleted from table 3-2 ? recommended operating conditions. vpump programming mode was changed fro m "3.0 to 3.6" to "3.15 to 3.45". 3-2 note 3 is new in table 3-4 ? overshoot and undershoot limits (as measured on quiet i/os)1. 3-2 in eq 3-2, 150 was changed to 110 and th e result changed from 3.9 to 1.951. 3-5 table 3-6 ? temperature and voltage dera ting factors for timing delays was updated. 3-6 table 3-5 ? package thermal resi stivities was updated. 3-5 table 3-14 ? summary of maximum and minimum dc input and output levels applicable to commercial and industrial conditions ?software default settings (advanced) and table 3-17 ? summary of maximum and minimum dc input levels applicable to commercial and in dustrial conditions (standard plus) were updated. 3-17 to 3-17 table 3-20 ? summary of i/o timing ch aracteristics?software default settings (advanced) and table 3-21 ? summary of i/o timing characteristics?software default settings (standard plus) were updated. 3-20 to 3-20 table 3-11 ? different components contributing to dynamic power consumption in proasic3 devices was updated. 3-9 table 3-24 ? i/o output buffer maximum resistances1 (advan ced) and table 3- 25 ? i/o output buffer maximum resist ances1 (standard plus) were updated. 3-22 to 3-22 table 3-17 ? summary of maximum and mi nimum dc input levels applicable to commercial and industrial conditions was updated. 3-18 table 3-28 ? i/o short currents iosh /iosl (advanced) and table 3-29 ? i/o short currents iosh/iosl (sta ndard plus) were updated. 3-24 to 3-26 the note in table 3-32 ? i/o input ri se time, fall time, and related i/o reliability was updated. 3-27 figure 3-33 ? write access after write onto same address, figure 3-34 ? read access after write onto same address, and figure 3-35 ? write access after read onto same address are new. 3-82 to 3-84 figure 3-43 ? timing diagram was updated. 3-96 previous version changes in current version (v1.1) page proasic3 dc and switching characteristics v1.1 2-103 advanced v0.5 (january 2006) blvds and m-ldvs are new i/o standards added to the datasheet. n/a the term flow-through was changed to pass-through. n/a figure 2-7 ? efficient long-lin e resources was updated. 2-7 the footnotes in figure 2-15 ? clock input sources including clkbuf, clkbuf_lvds/lvpecl, and clkint were updated. 2-16 the delay increments in the programmabl e delay blocks specification in figure 2-24 ? proasic3e ccc options. 2-24 the "sram and fifo" section was updated. 2-21 the "reset" section was updated. 2-25 the "wclk and rclk" section was updated. 2-25 the "reset" section was updated. 2-25 the "reset" section was updated. 2-27 the "introduction" of the "advan ced i/os" section was updated. 2-28 the "i/o banks" section is new. this section explains the following types of i/os: advanced standard+ standard table 2-12 ? automotive proasic3 bank types definition and differences is new. this table describes the standards listed above. 2-29 pci-x 3.3 v was added to the compatib le standards for 3.3 v in table 2- 11 ? vcci voltages and compatible standards 2-29 table 2-13 ? proasic3 i/o features was updated. 2-30 the "double data rate (ddr) suppo rt" section was updated to include information concerning implementation of the feature. 2-32 the "electrostatic discharge (esd) protec tion" section was up dated to include testing information. 2-35 level 3 and 4 descriptions were updated in table 2-43 ? i/o hot-swap and 5 v input tolerance capabilities in proasic3 devices. 2-64 the notes in table 2-43 ? i/o hot-swap and 5 v input tolerance capabilities in proasic3 devices were updated. 2-64 the "simultaneous switching outputs (sso s) and printed circuit board layout" section is new. 2-41 a footnote was added to table 2-14 ? m aximum i/o frequency for single-ended and differential i/os in all banks in automotive proasic3 devices (maximum drive strength and high slew selected). 2-30 table 2-18 ? automotive proasic3 i/o attribu tes vs. i/o standard applications 2-45 previous version changes in current version (v1.1) page proasic3 dc and switching characteristics 2-104 v1.1 advanced v0.5 (january 2006) (continued) table 2-50 ? proasic3 output drive (out _drive) for standard i/o bank type (a3p030 device) 2-83 table 2-51 ? proasic3 output drive for st andard+ i/o bank ty pe was updated. 2-84 table 2-54 ? proasic3 output drive for advanced i/o bank type was updated. 2-84 the "x" was updated in the "user i/o naming convention" section. 2-48 the "v cc core supply voltage" pin description was updated. 2-50 the "vmvx i/o supply voltage (quiet)" pin description was updated to include information concerning leaving the pin unconnected. 2-50 the "v jtag jtag supply voltage" pin description was updated. 2-50 the "v pump programming supply voltage" pin description was updated to include information on what happens when the pin is tied to ground. 2-50 the "i/o user input/output" pin descript ion was updated to include information on what happens when the pin is unused. 2-50 the "jtag pins" section was updated to include information on what happens when the pin is unused. 2-51 the "programming" section was update d to include info rmation concerning serialization. 2-53 the "jtag 1532" section was upda ted to include sample/preload information. 2-54 "dc and switching characteristics" chapter was updated with new information. starting on page 3-1 advanced v0.3 m7 device information is new. n/a table 2-4 ? proasic3 globals/ spines/rows by device was updated to include the number or rows in each top or bottom spine. 2-16 extfb was removed from figure 2-24 ? proasic3e ccc options. 2-24 the "pll macro" section was updated. extfb information was removed from this section. 2-15 the ccc output peak-to- peak period jitter f ccc_out was updated in table 2- 11 ? proasic3 ccc/pll specification 2-29 extfb was removed from figure 2-27 ? ccc/pll macro. 2-28 table 2-13 ? proasic3 i/o features was updated. 2-30 the "hot-swap support" section was updated. 2-33 the "cold-sparing support" section was updated. 2-34 "electrostatic discharge (esd) prot ection" section was updated. 2-35 the lvpecl specification in table 2-43 ? i/o hot-swap and 5 v input tolerance capabilities in proasic3 devices was updated. 2-64 in the bank 1 area of figure 2-72 , vmv2 was changed to vmv1 and v cci b2 was changed to v cci b1. 2-97 the vjtag and i/o pin descriptions were updated in the "pin descriptions" section. 2-50 the "jtag pins" section was updated. 2-51 previous version changes in current version (v1.1) page proasic3 dc and switching characteristics v1.1 2-105 advanced v0.3 (continued) "128-bit aes decryption" section wa s updated to include m7 device information. 2-53 table 3-6 was updated. 3-6 table 3-7 was updated. 3-6 in table 3-11, pac4 was updated. 3-93-8 table 3-20 was updated. 3-20 the note in table 3-32 was updated. 3-27 all timing characteristics tables were upda ted from lvttl to register delays 3-31 to 3-73 the timing characteristics for ram4k9, ra m512x18, and fifo were updated. 3-85 to 3-90 f tckmax was updated in table 3-110. 3-97 advanced v0.2 figure 2-11 was updated. 2-9 the "clock resources (versanets)" section was updated. 2-9 the "versanet global networks and sp ine access" section was updated. 2-9 the "pll macro" sect ion was updated. 2-15 figure 2-27 was updated. 2-28 figure 2-20 was updated. 2-19 table 2-5 was updated. 2-25 table 2-6 was updated. 2-25 the "fifo flag usage considerations" sectio n was updated. 2-27 table 2-13 was updated. 2-30 figure 2-24 was updated. 2-31 the "cold-sparing support" section is new. 2-34 table 2-43 was updated. 2-64 table 2-18 was updated. 2-45 pin descriptions in the "jtag pins" section were updated. 2-51 the "user i/o naming convention" section was updated. 2-48 table 3-7 was updated. 3-6 the "methodology" section was updated. 3-10 table 3-40 and table 3-39 were updated. 3-33, 3-32 previous version changes in current version (v1.1) page proasic3 dc and switching characteristics 2-106 v1.1 actel safety critical, life support, and high-reliability applications policy the actel products described in this advanced status datasheet may not have completed actel?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functional ity or performance. it is the responsibility of each customer to ensure the fitn ess of any actel product (but especially a new product) for a particular purpose, including appr opriateness for safety-cri tical, life-s upport, and other high-reliability applicatio ns. consult actel?s terms and cond itions for specific liability exclusions relating to life-support applications. a reliabilit y report covering all of actel?s products is available on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local actel sales office for addi tional reliability information. v1.3 3-1 proasic3 packaging 3 ? package pin assignments 68-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . notes: 1. this is the bottom view of the package. 2. the die attach paddle center of th e package is tied to ground (gnd). pin a1 mark 1 6 8 package pin assignments 3-2 v1.3 68-pin qfn pin number a3p015 function 1 io82rsb1 2 io80rsb1 3 io78rsb1 4 io76rsb1 5 gec0/io73rsb1 6 gea0/io72rsb1 7 geb0/io71rsb1 8v cc 9 gnd 10 v cci b1 11 io68rsb1 12 io67rsb1 13 io66rsb1 14 io65rsb1 15 io64rsb1 16 io63rsb1 17 io62rsb1 18 io60rsb1 19 io58rsb1 20 io56rsb1 21 io54rsb1 22 io52rsb1 23 io51rsb1 24 v cc 25 gnd 26 v cci b1 27 io50rsb1 28 io48rsb1 29 io46rsb1 30 io44rsb1 31 io42rsb1 32 tck 33 tdi 34 tms 35 v pump 36 tdo 37 trst 38 v jtag 39 io40rsb0 40 io37rsb0 41 gdb0/io34rsb0 42 gda0/io33rsb0 43 gdc0/io32rsb0 44 v cci b0 45 gnd 46 v cc 47 io31rsb0 48 io29rsb0 49 io28rsb0 50 io27rsb0 51 io25rsb0 52 io24rsb0 53 io22rsb0 54 io21rsb0 55 io19rsb0 56 io17rsb0 57 io15rsb0 58 io14rsb0 59 v cci b0 60 gnd 61 v cc 62 io12rsb0 63 io10rsb0 64 io08rsb0 65 io06rsb0 66 io04rsb0 67 io02rsb0 68 io00rsb0 68-pin qfn pin number a3p015 function proasic3 packaging v1.3 3-3 132-pin qfn note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . notes: 1. this is the bottom view of the package. 2. the die attach paddle center of th e package is tied to ground (gnd). a37 a1 a12 a36 d4 d3 d1 d2 a25 a48 a24 a13 b34 b1 b11 b44 b22 b12 c31 c1 c10 b33 b23 c30 c21 c40 c20 c11 optional corner pad (4x) pin a1mark package pin assignments 3-4 v1.3 132-pin qfn pin number a3p030 function a1 io01rsb1 a2 io81rsb1 a3 nc a4 io80rsb1 a5 gec0/io77rsb1 a6 nc a7 geb0/io75rsb1 a8 io73rsb1 a9 nc a10 v cc a11 io71rsb1 a12 io68rsb1 a13 io63rsb1 a14 io60rsb1 a15 nc a16 io59rsb1 a17 io57rsb1 a18 v cc a19 io54rsb1 a20 io52rsb1 a21 io49rsb1 a22 io48rsb1 a23 io47rsb1 a24 tdi a25 trst a26 io44rsb0 a27 nc a28 io43rsb0 a29 io42rsb0 a30 io40rsb0 a31 io39rsb0 a32 gdc0/io36rsb0 a33 nc a34 v cc a35 io34rsb0 a36 io31rsb0 a37 io26rsb0 a38 io23rsb0 a39 nc a40 io22rsb0 a41 io20rsb0 a42 io18rsb0 a43 v cc a44 io15rsb0 a45 io12rsb0 a46 io10rsb0 a47 io09rsb0 a48 io06rsb0 b1 io02rsb1 b2 io82rsb1 b3 gnd b4 io79rsb1 b5 nc b6 gnd b7 io74rsb1 b8 nc b9 gnd b10 io70rsb1 b11 io67rsb1 b12 io64rsb1 b13 io61rsb1 b14 gnd b15 io58rsb1 b16 io56rsb1 b17 gnd b18 io53rsb1 b19 io50rsb1 b20 gnd b21 io46rsb1 b22 tms b23 tdo b24 io45rsb0 132-pin qfn pin number a3p030 function b25 gnd b26 nc b27 io41rsb0 b28 gnd b29 gda0/io37rsb0 b30 nc b31 gnd b32 io33rsb0 b33 io30rsb0 b34 io27rsb0 b35 io24rsb0 b36 gnd b37 io21rsb0 b38 io19rsb0 b39 gnd b40 io16rsb0 b41 io13rsb0 b42 gnd b43 io08rsb0 b44 io05rsb0 c1 io03rsb1 c2 io00rsb1 c3 nc c4 io78rsb1 c5 gea0/io76rsb1 c6 nc c7 nc c8 v cci b1 c9 io69rsb1 c10 io66rsb1 c11 io65rsb1 c12 io62rsb1 c13 nc c14 nc c15 io55rsb1 c16 v cci b1 132-pin qfn pin number a3p030 function proasic3 packaging v1.3 3-5 c17 io51rsb1 c18 nc c19 tck c20 nc c21 v pump c22 v jtag c23 nc c24 nc c25 nc c26 gdb0/io38rsb0 c27 nc c28 v cci b0 c29 io32rsb0 c30 io29rsb0 c31 io28rsb0 c32 io25rsb0 c33 nc c34 nc c35 v cci b0 c36 io17rsb0 c37 io14rsb0 c38 io11rsb0 c39 io07rsb0 c40 io04rsb0 d1 gnd d2 gnd d3 gnd d4 gnd 132-pin qfn pin number a3p030 function package pin assignments 3-6 v1.3 132-pin qfn pin number a3p060 function a1 gab2/io00rsb1 a2 io93rsb1 a3 v cci b1 a4 gfc1/io89rsb1 a5 gfb0/io86rsb1 a6 v ccplf a7 gfa1/io84rsb1 a8 gfc2/io81rsb1 a9 io78rsb1 a10 v cc a11 geb1/io75rsb1 a12 gea0/io72rsb1 a13 gec2/io69rsb1 a14 io65rsb1 a15 v cc a16 io64rsb1 a17 io63rsb1 a18 io62rsb1 a19 io61rsb1 a20 io58rsb1 a21 gdb2/io55rsb1 a22 nc a23 gda2/io54rsb1 a24 tdi a25 trst a26 gdc1/io48rsb0 a27 v cc a28 io47rsb0 a29 gcc2/io46rsb0 a30 gca2/io44rsb0 a31 gca0/io43rsb0 a32 gcb1/io40rsb0 a33 io36rsb0 a34 v cc a35 io31rsb0 a36 gba2/io28rsb0 a37 gbb1/io25rsb0 a38 gbc0/io22rsb0 a39 v cci b0 a40 io21rsb0 a41 io18rsb0 a42 io15rsb0 a43 io14rsb0 a44 io11rsb0 a45 gab1/io08rsb0 a46 nc a47 gab0/io07rsb0 a48 io04rsb0 b1 io01rsb1 b2 gac2/io94rsb1 b3 gnd b4 gfc0/io88rsb1 b5 v complf b6 gnd b7 gfb2/io82rsb1 b8 io79rsb1 b9 gnd b10 geb0/io74rsb1 b11 vmv1 b12 geb2/io70rsb1 b13 io67rsb1 b14 gnd b15 nc b16 nc b17 gnd b18 io59rsb1 b19 gdc2/io56rsb1 b20 gnd b21 gndq b22 tms b23 tdo b24 gdc0/io49rsb0 132-pin qfn pin number a3p060 function b25 gnd b26 nc b27 gcb2/io45rsb0 b28 gnd b29 gcb0/io41rsb0 b30 gcc1/io38rsb0 b31 gnd b32 gbb2/io30rsb0 b33 vmv0 b34 gba0/io26rsb0 b35 gbc1/io23rsb0 b36 gnd b37 io20rsb0 b38 io17rsb0 b39 gnd b40 io12rsb0 b41 gac0/io09rsb0 b42 gnd b43 gaa1/io06rsb0 b44 gndq c1 gaa2/io02rsb1 c2 io95rsb1 c3 v cc c4 gfb1/io87rsb1 c5 gfa0/io85rsb1 c6 gfa2/io83rsb1 c7 io80rsb1 c8 v cci b1 c9 gea1/io73rsb1 c10 gndq c11 gea2/io71rsb1 c12 io68rsb1 c13 v cci b1 c14 nc c15 nc c16 io60rsb1 132-pin qfn pin number a3p060 function proasic3 packaging v1.3 3-7 c17 io57rsb1 c18 nc c19 tck c20 vmv1 c21 v pump c22 v jtag c23 v cci b0 c24 nc c25 nc c26 gca1/io42rsb0 c27 gcc0/io39rsb0 c28 v cci b0 c29 io29rsb0 c30 gndq c31 gba1/io27rsb0 c32 gbb0/io24rsb0 c33 v cc c34 io19rsb0 c35 io16rsb0 c36 io13rsb0 c37 gac1/io10rsb0 c38 nc c39 gaa0/io05rsb0 c40 vmv0 d1 gnd d2 gnd d3 gnd d4 gnd 132-pin qfn pin number a3p060 function package pin assignments 3-8 v1.3 132-pin qfn pin number a3p125 function a1 gab2/io69rsb1 a2 io130rsb1 a3 v cci b1 a4 gfc1/io126rsb1 a5 gfb0/io123rsb1 a6 v ccplf a7 gfa1/io121rsb1 a8 gfc2/io118rsb1 a9 io115rsb1 a10 v cc a11 geb1/io110rsb1 a12 gea0/io107rsb1 a13 gec2/io104rsb1 a14 io100rsb1 a15 v cc a16 io99rsb1 a17 io96rsb1 a18 io94rsb1 a19 io91rsb1 a20 io85rsb1 a21 io79rsb1 a22 v cc a23 gdb2/io71rsb1 a24 tdi a25 trst a26 gdc1/io61rsb0 a27 v cc a28 io60rsb0 a29 gcc2/io59rsb0 a30 gca2/io57rsb0 a31 gca0/io56rsb0 a32 gcb1/io53rsb0 a33 io49rsb0 a34 v cc a35 io44rsb0 a36 gba2/io41rsb0 a37 gbb1/io38rsb0 a38 gbc0/io35rsb0 a39 v cci b0 a40 io28rsb0 a41 io22rsb0 a42 io18rsb0 a43 io14rsb0 a44 io11rsb0 a45 io07rsb0 a46 v cc a47 gac1/io05rsb0 a48 gab0/io02rsb0 b1 io68rsb1 b2 gac2/io131rsb1 b3 gnd b4 gfc0/io125rsb1 b5 v complf b6 gnd b7 gfb2/io119rsb1 b8 io116rsb1 b9 gnd b10 geb0/io109rsb1 b11 vmv1 b12 geb2/io105rsb1 b13 io101rsb1 b14 gnd b15 io98rsb1 b16 io95rsb1 b17 gnd b18 io87rsb1 b19 io81rsb1 b20 gnd b21 gndq b22 tms b23 tdo b24 gdc0/io62rsb0 132-pin qfn pin number a3p125 function b25 gnd b26 nc b27 gcb2/io58rsb0 b28 gnd b29 gcb0/io54rsb0 b30 gcc1/io51rsb0 b31 gnd b32 gbb2/io43rsb0 b33 vmv0 b34 gba0/io39rsb0 b35 gbc1/io36rsb0 b36 gnd b37 io26rsb0 b38 io21rsb0 b39 gnd b40 io13rsb0 b41 io08rsb0 b42 gnd b43 gac0/io04rsb0 b44 gndq c1 gaa2/io67rsb1 c2 io132rsb1 c3 v cc c4 gfb1/io124rsb1 c5 gfa0/io122rsb1 c6 gfa2/io120rsb1 c7 io117rsb1 c8 v cci b1 c9 gea1/io108rsb1 c10 gndq c11 gea2/io106rsb1 c12 io103rsb1 c13 v cci b1 c14 io97rsb1 c15 io93rsb1 c16 io89rsb1 132-pin qfn pin number a3p125 function proasic3 packaging v1.3 3-9 c17 io83rsb1 c18 v cci b1 c19 tck c20 vmv1 c21 v pump c22 v jtag c23 v cci b0 c24 nc c25 nc c26 gca1/io55rsb0 c27 gcc0/io52rsb0 c28 v cci b0 c29 io42rsb0 c30 gndq c31 gba1/io40rsb0 c32 gbb0/io37rsb0 c33 v cc c34 io24rsb0 c35 io19rsb0 c36 io16rsb0 c37 io10rsb0 c38 v cci b0 c39 gab1/io03rsb0 c40 vmv0 d1 gnd d2 gnd d3 gnd d4 gnd 132-pin qfn pin number a3p125 function package pin assignments 3-10 v1.3 132-pin qfn pin number a3p250 function a1 gab2/io117upb3 a2 io117vpb3 a3 v cci b3 a4 gfc1/io110pdb3 a5 gfb0/io109npb3 a6 v ccplf a7 gfa1/io108ppb3 a8 gfc2/io105ppb3 a9 io103ndb3 a10 v cc a11 gea1/io98ppb3 a12 gea0/io98npb3 a13 gec2/io95rsb2 a14 io91rsb2 a15 v cc a16 io90rsb2 a17 io87rsb2 a18 io85rsb2 a19 io82rsb2 a20 io76rsb2 a21 io70rsb2 a22 v cc a23 gdb2/io62rsb2 a24 tdi a25 trst a26 gdc1/io58udb1 a27 v cc a28 io54ndb1 a29 io52ndb1 a30 gca2/io51ppb1 a31 gca0/io50npb1 a32 gcb1/io49pdb1 a33 io47nsb1 a34 v cc a35 io41npb1 a36 gba2/io41ppb1 a37 gbb1/io38rsb0 a38 gbc0/io35rsb0 a39 v cci b0 a40 io28rsb0 a41 io22rsb0 a42 io18rsb0 a43 io14rsb0 a44 io11rsb0 a45 io07rsb0 a46 v cc a47 gac1/io05rsb0 a48 gab0/io02rsb0 b1 io118vdb3 b2 gac2/io116udb3 b3 gnd b4 gfc0/io110ndb3 b5 v complf b6 gnd b7 gfb2/io106psb3 b8 io103pdb3 b9 gnd b10 geb0/io99ndb3 b11 vmv3 b12 geb2/io96rsb2 b13 io92rsb2 b14 gnd b15 io89rsb2 b16 io86rsb2 b17 gnd b18 io78rsb2 b19 io72rsb2 b20 gnd b21 gndq b22 tms b23 tdo b24 gdc0/io58vdb1 132-pin qfn pin number a3p250 function b25 gnd b26 io54pdb1 b27 gcb2/io52pdb1 b28 gnd b29 gcb0/io49ndb1 b30 gcc1/io48pdb1 b31 gnd b32 gbb2/io42pdb1 b33 vmv1 b34 gba0/io39rsb0 b35 gbc1/io36rsb0 b36 gnd b37 io26rsb0 b38 io21rsb0 b39 gnd b40 io13rsb0 b41 io08rsb0 b42 gnd b43 gac0/io04rsb0 b44 gndq c1 gaa2/io118udb3 c2 io116vdb3 c3 v cc c4 gfb1/io109ppb3 c5 gfa0/io108npb3 c6 gfa2/io107psb3 c7 io105npb3 c8 v cci b3 c9 geb1/io99pdb3 c10 gndq c11 gea2/io97rsb2 c12 io94rsb2 c13 v cci b2 c14 io88rsb2 c15 io84rsb2 c16 io80rsb2 132-pin qfn pin number a3p250 function proasic3 packaging v1.3 3-11 c17 io74rsb2 c18 v cci b2 c19 tck c20 vmv2 c21 v pump c22 v jtag c23 v cci b1 c24 io53nsb1 c25 io51npb1 c26 gca1/io50ppb1 c27 gcc0/io48ndb1 c28 v cci b1 c29 io42ndb1 c30 gndq c31 gba1/io40rsb0 c32 gbb0/io37rsb0 c33 v cc c34 io24rsb0 c35 io19rsb0 c36 io16rsb0 c37 io10rsb0 c38 v cci b0 c39 gab1/io03rsb0 c40 vmv0 d1 gnd d2 gnd d3 gnd d4 gnd 132-pin qfn pin number a3p250 function package pin assignments 3-12 v1.3 100-pin vqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the top view of the package. 1 100-pin vqfp 100 proasic3 packaging v1.3 3-13 100-pin vqfp pin number a3p030 function 1gnd 2 io82rsb1 3 io81rsb1 4 io80rsb1 5 io79rsb1 6 io78rsb1 7 io77rsb1 8 io76rsb1 9gnd 10 io75rsb1 11 io74rsb1 12 gec0/io73rsb1 13 gea0/io72rsb1 14 geb0/io71rsb1 15 io70rsb1 16 io69rsb1 17 v cc 18 v cci b1 19 io68rsb1 20 io67rsb1 21 io66rsb1 22 io65rsb1 23 io64rsb1 24 io63rsb1 25 io62rsb1 26 io61rsb1 27 io60rsb1 28 io59rsb1 29 io58rsb1 30 io57rsb1 31 io56rsb1 32 io55rsb1 33 io54rsb1 34 io53rsb1 35 io52rsb1 36 io51rsb1 37 v cc 38 gnd 39 v cci b1 40 io49rsb1 41 io47rsb1 42 io46rsb1 43 io45rsb1 44 io44rsb1 45 io43rsb1 46 io42rsb1 47 tck 48 tdi 49 tms 50 nc 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 io41rsb0 58 io40rsb0 59 io39rsb0 60 io38rsb0 61 io37rsb0 62 io36rsb0 63 gdb0/io34rsb0 64 gda0/io33rsb0 65 gdc0/io32rsb0 66 v cci b0 67 gnd 68 v cc 69 io31rsb0 70 io30rsb0 71 io29rsb0 72 io28rsb0 100-pin vqfp pin number a3p030 function 73 io27rsb0 74 io26rsb0 75 io25rsb0 76 io24rsb0 77 io23rsb0 78 io22rsb0 79 io21rsb0 80 io20rsb0 81 io19rsb0 82 io18rsb0 83 io17rsb0 84 io16rsb0 85 io15rsb0 86 io14rsb0 87 v cci b0 88 gnd 89 v cc 90 io12rsb0 91 io10rsb0 92 io08rsb0 93 io07rsb0 94 io06rsb0 95 io05rsb0 96 io04rsb0 97 io03rsb0 98 io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp pin number a3p030 function package pin assignments 3-14 v1.3 100-pin vqfp pin number a3p060 function 1gnd 2 gaa2/io51rsb1 3 io52rsb1 4 gab2/io53rsb1 5 io95rsb1 6 gac2/io94rsb1 7 io93rsb1 8 io92rsb1 9gnd 10 gfb1/io87rsb1 11 gfb0/io86rsb1 12 v complf 13 gfa0/io85rsb1 14 v ccplf 15 gfa1/io84rsb1 16 gfa2/io83rsb1 17 v cc 18 v cci b1 19 gec1/io77rsb1 20 geb1/io75rsb1 21 geb0/io74rsb1 22 gea1/io73rsb1 23 gea0/io72rsb1 24 vmv1 25 gndq 26 gea2/io71rsb1 27 geb2/io70rsb1 28 gec2/io69rsb1 29 io68rsb1 30 io67rsb1 31 io66rsb1 32 io65rsb1 33 io64rsb1 34 io63rsb1 35 io62rsb1 36 io61rsb1 37 v cc 38 gnd 39 v cci b1 40 io60rsb1 41 io59rsb1 42 io58rsb1 43 io57rsb1 44 gdc2/io56rsb1 45 gdb2/io55rsb1 46 gda2/io54rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io49rsb0 58 gdc0/io46rsb0 59 gdc1/io45rsb0 60 gcc2/io43rsb0 61 gcb2/io42rsb0 62 gca0/io40rsb0 63 gca1/io39rsb0 64 gcc0/io36rsb0 65 gcc1/io35rsb0 66 v cci b0 67 gnd 68 v cc 69 io31rsb0 70 gbc2/io29rsb0 71 gbb2/io27rsb0 72 io26rsb0 100-pin vqfp pin number a3p060 function 73 gba2/io25rsb0 74 vmv0 75 gndq 76 gba1/io24rsb0 77 gba0/io23rsb0 78 gbb1/io22rsb0 79 gbb0/io21rsb0 80 gbc1/io20rsb0 81 gbc0/io19rsb0 82 io18rsb0 83 io17rsb0 84 io15rsb0 85 io13rsb0 86 io11rsb0 87 v cci b0 88 gnd 89 v cc 90 io10rsb0 91 io09rsb0 92 io08rsb0 93 gac1/io07rsb0 94 gac0/io06rsb0 95 gab1/io05rsb0 96 gab0/io04rsb0 97 gaa1/io03rsb0 98 gaa0/io02rsb0 99 io01rsb0 100 io00rsb0 100-pin vqfp pin number a3p060 function proasic3 packaging v1.3 3-15 100-pin vqfp pin number a3p125 function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5io132rsb1 6 gac2/io131rsb1 7io130rsb1 8io129rsb1 9gnd 10 gfb1/io124rsb1 11 gfb0/io123rsb1 12 v complf 13 gfa0/io122rsb1 14 v ccplf 15 gfa1/io121rsb1 16 gfa2/io120rsb1 17 v cc 18 v cci b1 19 gec0/io111rsb1 20 geb1/io110rsb1 21 geb0/io109rsb1 22 gea1/io108rsb1 23 gea0/io107rsb1 24 vmv1 25 gndq 26 gea2/io106rsb1 27 geb2/io105rsb1 28 gec2/io104rsb1 29 io102rsb1 30 io100rsb1 31 io99rsb1 32 io97rsb1 33 io96rsb1 34 io95rsb1 35 io94rsb1 36 io93rsb1 37 v cc 38 gnd 39 v cci b1 40 io87rsb1 41 io84rsb1 42 io81rsb1 43 io75rsb1 44 gdc2/io72rsb1 45 gdb2/io71rsb1 46 gda2/io70rsb1 47 tck 48 tdi 49 tms 50 vmv1 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io65rsb0 58 gdc0/io62rsb0 59 gdc1/io61rsb0 60 gcc2/io59rsb0 61 gcb2/io58rsb0 62 gca0/io56rsb0 63 gca1/io55rsb0 64 gcc0/io52rsb0 65 gcc1/io51rsb0 66 v cci b0 67 gnd 68 v cc 69 io47rsb0 70 gbc2/io45rsb0 71 gbb2/io43rsb0 72 io42rsb0 100-pin vqfp pin number a3p125 function 73 gba2/io41rsb0 74 vmv0 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io32rsb0 83 io28rsb0 84 io25rsb0 85 io22rsb0 86 io19rsb0 87 v cci b0 88 gnd 89 v cc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 io09rsb0 94 io07rsb0 95 gac1/io05rsb0 96 gac0/io04rsb0 97 gab1/io03rsb0 98 gab0/io02rsb0 99 gaa1/io01rsb0 100 gaa0/io00rsb0 100-pin vqfp pin number a3p125 function package pin assignments 3-16 v1.3 100-pin vqfp pin number a3p250 function 1 gnd 2 gaa2/io118udb3 3io118vdb3 4 gab2/io117udb3 5io117vdb3 6 gac2/io116udb3 7io116vdb3 8 io112psb3 9 gnd 10 gfb1/io109pdb3 11 gfb0/io109ndb3 12 v complf 13 gfa0/io108npb3 14 v ccplf 15 gfa1/io108ppb3 16 gfa2/io107psb3 17 v cc 18 v cci b3 19 gfc2/io105psb3 20 gec1/io100pdb3 21 gec0/io100ndb3 22 gea1/io98pdb3 23 gea0/io98ndb3 24 vmv3 25 gndq 26 gea2/io97rsb2 27 geb2/io96rsb2 28 gec2/io95rsb2 29 io93rsb2 30 io92rsb2 31 io91rsb2 32 io90rsb2 33 io88rsb2 34 io86rsb2 35 io85rsb2 36 io84rsb2 37 v cc 38 gnd 39 v cci b2 40 io77rsb2 41 io74rsb2 42 io71rsb2 43 gdc2/io63rsb2 44 gdb2/io62rsb2 45 gda2/io61rsb2 46 gndq 47 tck 48 tdi 49 tms 50 vmv2 51 gnd 52 v pump 53 nc 54 tdo 55 trst 56 v jtag 57 gda1/io60usb1 58 gdc0/io58vdb1 59 gdc1/io58udb1 60 io52ndb1 61 gcb2/io52pdb1 62 gca1/io50pdb1 63 gca0/io50ndb1 64 gcc0/io48ndb1 65 gcc1/io48pdb1 66 v cci b1 67 gnd 68 v cc 69 io43ndb1 70 gbc2/io43pdb1 71 gbb2/io42psb1 72 io41ndb1 100-pin vqfp pin number a3p250 function 73 gba2/io41pdb1 74 vmv1 75 gndq 76 gba1/io40rsb0 77 gba0/io39rsb0 78 gbb1/io38rsb0 79 gbb0/io37rsb0 80 gbc1/io36rsb0 81 gbc0/io35rsb0 82 io29rsb0 83 io27rsb0 84 io25rsb0 85 io23rsb0 86 io21rsb0 87 v cci b0 88 gnd 89 v cc 90 io15rsb0 91 io13rsb0 92 io11rsb0 93 gac1/io05rsb0 94 gac0/io04rsb0 95 gab1/io03rsb0 96 gab0/io02rsb0 97 gaa1/io01rsb0 98 gaa0/io00rsb0 99 gndq 100 vmv0 100-pin vqfp pin number a3p250 function proasic3 packaging v1.3 3-17 144-pin tqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the top view of the package. 1 144 144-pin tqfp package pin assignments 3-18 v1.3 144-pin tqfp pin number a3p060 function 1 gaa2/io51rsb1 2 io52rsb1 3 gab2/io53rsb1 4 io95rsb1 5 gac2/io94rsb1 6 io93rsb1 7 io92rsb1 8 io91rsb1 9v cc 10 gnd 11 v cci b1 12 io90rsb1 13 gfc1/io89rsb1 14 gfc0/io88rsb1 15 gfb1/io87rsb1 16 gfb0/io86rsb1 17 v complf 18 gfa0/io85rsb1 19 v ccplf 20 gfa1/io84rsb1 21 gfa2/io83rsb1 22 gfb2/io82rsb1 23 gfc2/io81rsb1 24 io80rsb1 25 io79rsb1 26 io78rsb1 27 gnd 28 v cci b1 29 gec1/io77rsb1 30 gec0/io76rsb1 31 geb1/io75rsb1 32 geb0/io74rsb1 33 gea1/io73rsb1 34 gea0/io72rsb1 35 vmv1 36 gndq 37 nc 38 gea2/io71rsb1 39 geb2/io70rsb1 40 gec2/io69rsb1 41 io68rsb1 42 io67rsb1 43 io66rsb1 44 io65rsb1 45 v cc 46 gnd 47 v cci b1 48 nc 49 io64rsb1 50 nc 51 io63rsb1 52 nc 53 io62rsb1 54 nc 55 io61rsb1 56 nc 57 nc 58 io60rsb1 59 io59rsb1 60 io58rsb1 61 io57rsb1 62 nc 63 gnd 64 nc 65 gdc2/io56rsb1 66 gdb2/io55rsb1 67 gda2/io54rsb1 68 gndq 69 tck 70 tdi 71 tms 72 vmv1 144-pin tqfp pin number a3p060 function 73 v pump 74 nc 75 tdo 76 trst 77 v jtag 78 gda0/io50rsb0 79 gdb0/io48rsb0 80 gdb1/io47rsb0 81 v cci b0 82 gnd 83 io44rsb0 84 gcc2/io43rsb0 85 gcb2/io42rsb0 86 gca2/io41rsb0 87 gca0/io40rsb0 88 gca1/io39rsb0 89 gcb0/io38rsb0 90 gcb1/io37rsb0 91 gcc0/io36rsb0 92 gcc1/io35rsb0 93 io34rsb0 94 io33rsb0 95 nc 96 nc 97 nc 98 v cci b0 99 gnd 100 v cc 101 io30rsb0 102 gbc2/io29rsb0 103 io28rsb0 104 gbb2/io27rsb0 105 io26rsb0 106 gba2/io25rsb0 107 vmv0 108 gndq 144-pin tqfp pin number a3p060 function proasic3 packaging v1.3 3-19 109 nc 110 nc 111 gba1/io24rsb0 112 gba0/io23rsb0 113 gbb1/io22rsb0 114 gbb0/io21rsb0 115 gbc1/io20rsb0 116 gbc0/io19rsb0 117 v cci b0 118 gnd 119 v cc 120 io18rsb0 121 io17rsb0 122 io16rsb0 123 io15rsb0 124 io14rsb0 125 io13rsb0 126 io12rsb0 127 io11rsb0 128 nc 129 io10rsb0 130 io09rsb0 131 io08rsb0 132 gac1/io07rsb0 133 gac0/io06rsb0 134 nc 135 gnd 136 nc 137 gab1/io05rsb0 138 gab0/io04rsb0 139 gaa1/io03rsb0 140 gaa0/io02rsb0 141 io01rsb0 142 io00rsb0 143 gndq 144 vmv0 144-pin tqfp pin number a3p060 function package pin assignments 3-20 v1.3 144-pin tqfp pin number a3p125 function 1 gaa2/io67rsb1 2 io68rsb1 3 gab2/io69rsb1 4io132rsb1 5 gac2/io131rsb1 6io130rsb1 7io129rsb1 8io128rsb1 9v cc 10 gnd 11 v cci b1 12 io127rsb1 13 gfc1/io126rsb1 14 gfc0/io125rsb1 15 gfb1/io124rsb1 16 gfb0/io123rsb1 17 v complf 18 gfa0/io122rsb1 19 v ccplf 20 gfa1/io121rsb1 21 gfa2/io120rsb1 22 gfb2/io119rsb1 23 gfc2/io118rsb1 24 io117rsb1 25 io116rsb1 26 io115rsb1 27 gnd 28 v cci b1 29 gec1/io112rsb1 30 gec0/io111rsb1 31 geb1/io110rsb1 32 geb0/io109rsb1 33 gea1/io108rsb1 34 gea0/io107rsb1 35 vmv1 36 gndq 37 nc 38 gea2/io106rsb1 39 geb2/io105rsb1 40 gec2/io104rsb1 41 io103rsb1 42 io102rsb1 43 io101rsb1 44 io100rsb1 45 v cc 46 gnd 47 v cci b1 48 io99rsb1 49 io97rsb1 50 io95rsb1 51 io93rsb1 52 io92rsb1 53 io90rsb1 54 io88rsb1 55 io86rsb1 56 io84rsb1 57 io83rsb1 58 io82rsb1 59 io81rsb1 60 io80rsb1 61 io79rsb1 62 v cc 63 gnd 64 v cci b1 65 gdc2/io72rsb1 66 gdb2/io71rsb1 67 gda2/io70rsb1 68 gndq 69 tck 70 tdi 71 tms 72 vmv1 144-pin tqfp pin number a3p125 function 73 v pump 74 nc 75 tdo 76 trst 77 v jtag 78 gda0/io66rsb0 79 gdb0/io64rsb0 80 gdb1/io63rsb0 81 v cci b0 82 gnd 83 io60rsb0 84 gcc2/io59rsb0 85 gcb2/io58rsb0 86 gca2/io57rsb0 87 gca0/io56rsb0 88 gca1/io55rsb0 89 gcb0/io54rsb0 90 gcb1/io53rsb0 91 gcc0/io52rsb0 92 gcc1/io51rsb0 93 io50rsb0 94 io49rsb0 95 nc 96 nc 97 nc 98 v cci b0 99 gnd 100 v cc 101 io47rsb0 102 gbc2/io45rsb0 103 io44rsb0 104 gbb2/io43rsb0 105 io42rsb0 106 gba2/io41rsb0 107 vmv0 108 gndq 144-pin tqfp pin number a3p125 function proasic3 packaging v1.3 3-21 109 gba1/io40rsb0 110 gba0/io39rsb0 111 gbb1/io38rsb0 112 gbb0/io37rsb0 113 gbc1/io36rsb0 114 gbc0/io35rsb0 115 io34rsb0 116 io33rsb0 117 v cci b0 118 gnd 119 v cc 120 io29rsb0 121 io28rsb0 122 io27rsb0 123 io25rsb0 124 io23rsb0 125 io21rsb0 126 io19rsb0 127 io17rsb0 128 io16rsb0 129 io14rsb0 130 io12rsb0 131 io10rsb0 132 io08rsb0 133 io06rsb0 134 v cci b0 135 gnd 136 v cc 137 gac1/io05rsb0 138 gac0/io04rsb0 139 gab1/io03rsb0 140 gab0/io02rsb0 141 gaa1/io01rsb0 142 gaa0/io00rsb0 143 gndq 144 vmv0 144-pin tqfp pin number a3p125 function package pin assignments 3-22 v1.3 208-pin pqfp note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the top view of the package. 208-pin pqfp 1 208 proasic3 packaging v1.3 3-23 208-pin pqfp pin number a3p125 function 1gnd 2 gaa2/io67rsb1 3 io68rsb1 4 gab2/io69rsb1 5io132rsb1 6 gac2/io131rsb1 7nc 8nc 9io130rsb1 10 io129rsb1 11 nc 12 io128rsb1 13 nc 14 nc 15 nc 16 v cc 17 gnd 18 v cci b1 19 io127rsb1 20 nc 21 gfc1/io126rsb1 22 gfc0/io125rsb1 23 gfb1/io124rsb1 24 gfb0/io123rsb1 25 v complf 26 gfa0/io122rsb1 27 v ccplf 28 gfa1/io121rsb1 29 gnd 30 gfa2/io120rsb1 31 nc 32 gfb2/io119rsb1 33 nc 34 gfc2/io118rsb1 35 io117rsb1 36 nc 37 io116rsb1 38 io115rsb1 39 nc 40 v cci b1 41 gnd 42 io114rsb1 43 io113rsb1 44 gec1/io112rsb1 45 gec0/io111rsb1 46 geb1/io110rsb1 47 geb0/io109rsb1 48 gea1/io108rsb1 49 gea0/io107rsb1 50 vmv1 51 gndq 52 gnd 53 nc 54 nc 55 gea2/io106rsb1 56 geb2/io105rsb1 57 gec2/io104rsb1 58 io103rsb1 59 io102rsb1 60 io101rsb1 61 io100rsb1 62 v cci b1 63 io99rsb1 64 io98rsb1 65 gnd 66 io97rsb1 67 io96rsb1 68 io95rsb1 69 io94rsb1 70 io93rsb1 71 v cc 72 v cci b1 208-pin pqfp pin number a3p125 function 73 io92rsb1 74 io91rsb1 75 io90rsb1 76 io89rsb1 77 io88rsb1 78 io87rsb1 79 io86rsb1 80 io85rsb1 81 gnd 82 io84rsb1 83 io83rsb1 84 io82rsb1 85 io81rsb1 86 io80rsb1 87 io79rsb1 88 v cc 89 v cci b1 90 io78rsb1 91 io77rsb1 92 io76rsb1 93 io75rsb1 94 io74rsb1 95 io73rsb1 96 gdc2/io72rsb1 97 gnd 98 gdb2/io71rsb1 99 gda2/io70rsb1 100 gndq 101 tck 102 tdi 103 tms 104 vmv1 105 gnd 106 v pump 107 nc 108 tdo 208-pin pqfp pin number a3p125 function package pin assignments 3-24 v1.3 109 trst 110 v jtag 111 gda0/io66rsb0 112 gda1/io65rsb0 113 gdb0/io64rsb0 114 gdb1/io63rsb0 115 gdc0/io62rsb0 116 gdc1/io61rsb0 117 nc 118 nc 119 nc 120 nc 121 nc 122 gnd 123 v cci b0 124 nc 125 nc 126 v cc 127 io60rsb0 128 gcc2/io59rsb0 129 gcb2/io58rsb0 130 gnd 131 gca2/io57rsb0 132 gca0/io56rsb0 133 gca1/io55rsb0 134 gcb0/io54rsb0 135 gcb1/io53rsb0 136 gcc0/io52rsb0 137 gcc1/io51rsb0 138 io50rsb0 139 io49rsb0 140 v cci b0 141 gnd 142 v cc 143 io48rsb0 144 io47rsb0 208-pin pqfp pin number a3p125 function 145 io46rsb0 146 nc 147 nc 148 nc 149 gbc2/io45rsb0 150 io44rsb0 151 gbb2/io43rsb0 152 io42rsb0 153 gba2/io41rsb0 154 vmv0 155 gndq 156 gnd 157 nc 158 gba1/io40rsb0 159 gba0/io39rsb0 160 gbb1/io38rsb0 161 gbb0/io37rsb0 162 gnd 163 gbc1/io36rsb0 164 gbc0/io35rsb0 165 io34rsb0 166 io33rsb0 167 io32rsb0 168 io31rsb0 169 io30rsb0 170 v cci b0 171 v cc 172 io29rsb0 173 io28rsb0 174 io27rsb0 175 io26rsb0 176 io25rsb0 177 io24rsb0 178 gnd 179 io23rsb0 180 io22rsb0 208-pin pqfp pin number a3p125 function 181 io21rsb0 182 io20rsb0 183 io19rsb0 184 io18rsb0 185 io17rsb0 186 v cci b0 187 v cc 188 io16rsb0 189 io15rsb0 190 io14rsb0 191 io13rsb0 192 io12rsb0 193 io11rsb0 194 io10rsb0 195 gnd 196 io09rsb0 197 io08rsb0 198 io07rsb0 199 io06rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp pin number a3p125 function proasic3 packaging v1.3 3-25 208-pin pqfp pin number a3p250 function 1gnd 2 gaa2/io118udb3 3 io118vdb3 4 gab2/io117udb3 5 io117vdb3 6 gac2/io116udb3 7 io116vdb3 8 io115udb3 9 io115vdb3 10 io114udb3 11 io114vdb3 12 io113pdb3 13 io113ndb3 14 io112pdb3 15 io112ndb3 16 v cc 17 gnd 18 v cci b3 19 io111pdb3 20 io111ndb3 21 gfc1/io110pdb3 22 gfc0/io110ndb3 23 gfb1/io109pdb3 24 gfb0/io109ndb3 25 v complf 26 gfa0/io108npb3 27 v ccplf 28 gfa1/io108ppb3 29 gnd 30 gfa2/io107pdb3 31 io107ndb3 32 gfb2/io106pdb3 33 io106ndb3 34 gfc2/io105pdb3 35 io105ndb3 36 nc 37 io104pdb3 38 io104ndb3 39 io103psb3 40 v cci b3 41 gnd 42 io101pdb3 43 io101ndb3 44 gec1/io100pdb3 45 gec0/io100ndb3 46 geb1/io99pdb3 47 geb0/io99ndb3 48 gea1/io98pdb3 49 gea0/io98ndb3 50 vmv3 51 gndq 52 gnd 53 nc 54 nc 55 gea2/io97rsb2 56 geb2/io96rsb2 57 gec2/io95rsb2 58 io94rsb2 59 io93rsb2 60 io92rsb2 61 io91rsb2 62 v cci b2 63 io90rsb2 64 io89rsb2 65 gnd 66 io88rsb2 67 io87rsb2 68 io86rsb2 69 io85rsb2 70 io84rsb2 71 v cc 72 v cci b2 208-pin pqfp pin number a3p250 function 73 io83rsb2 74 io82rsb2 75 io81rsb2 76 io80rsb2 77 io79rsb2 78 io78rsb2 79 io77rsb2 80 io76rsb2 81 gnd 82 io75rsb2 83 io74rsb2 84 io73rsb2 85 io72rsb2 86 io71rsb2 87 io70rsb2 88 v cc 89 v cci b2 90 io69rsb2 91 io68rsb2 92 io67rsb2 93 io66rsb2 94 io65rsb2 95 io64rsb2 96 gdc2/io63rsb2 97 gnd 98 gdb2/io62rsb2 99 gda2/io61rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 v pump 107 nc 108 tdo 208-pin pqfp pin number a3p250 function package pin assignments 3-26 v1.3 109 trst 110 v jtag 111 gda0/io60vdb1 112 gda1/io60udb1 113 gdb0/io59vdb1 114 gdb1/io59udb1 115 gdc0/io58vdb1 116 gdc1/io58udb1 117 io57vdb1 118 io57udb1 119 io56ndb1 120 io56pdb1 121 io55rsb1 122 gnd 123 v cci b1 124 nc 125 nc 126 v cc 127 io53ndb1 128 gcc2/io53pdb1 129 gcb2/io52psb1 130 gnd 131 gca2/io51psb1 132 gca1/io50pdb1 133 gca0/io50ndb1 134 gcb0/io49ndb1 135 gcb1/io49pdb1 136 gcc0/io48ndb1 137 gcc1/io48pdb1 138 io47ndb1 139 io47pdb1 140 v cci b1 141 gnd 142 v cc 143 io46rsb1 144 io45ndb1 208-pin pqfp pin number a3p250 function 145 io45pdb1 146 io44ndb1 147 io44pdb1 148 io43ndb1 149 gbc2/io43pdb1 150 io42ndb1 151 gbb2/io42pdb1 152 io41ndb1 153 gba2/io41pdb1 154 vmv1 155 gndq 156 gnd 157 nc 158 gba1/io40rsb0 159 gba0/io39rsb0 160 gbb1/io38rsb0 161 gbb0/io37rsb0 162 gnd 163 gbc1/io36rsb0 164 gbc0/io35rsb0 165 io34rsb0 166 io33rsb0 167 io32rsb0 168 io31rsb0 169 io30rsb0 170 v cci b0 171 v cc 172 io29rsb0 173 io28rsb0 174 io27rsb0 175 io26rsb0 176 io25rsb0 177 io24rsb0 178 gnd 179 io23rsb0 180 io22rsb0 208-pin pqfp pin number a3p250 function 181 io21rsb0 182 io20rsb0 183 io19rsb0 184 io18rsb0 185 io17rsb0 186 v cci b0 187 v cc 188 io16rsb0 189 io15rsb0 190 io14rsb0 191 io13rsb0 192 io12rsb0 193 io11rsb0 194 io10rsb0 195 gnd 196 io09rsb0 197 io08rsb0 198 io07rsb0 199 io06rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp pin number a3p250 function proasic3 packaging v1.3 3-27 208-pin pqfp pin number a3p400 function 1gnd 2 gaa2/io155udb3 3 io155vdb3 4 gab2/io154udb3 5 io154vdb3 6 gac2/io153udb3 7 io153vdb3 8 io152udb3 9 io152vdb3 10 io151udb3 11 io151vdb3 12 io150pdb3 13 io150ndb3 14 io149pdb3 15 io149ndb3 16 v cc 17 gnd 18 v cci b3 19 io148pdb3 20 io148ndb3 21 gfc1/io147pdb3 22 gfc0/io147ndb3 23 gfb1/io146pdb3 24 gfb0/io146ndb3 25 v complf 26 gfa0/io145npb3 27 v ccplf 28 gfa1/io145ppb3 29 gnd 30 gfa2/io144pdb3 31 io144ndb3 32 gfb2/io143pdb3 33 io143ndb3 34 gfc2/io142pdb3 35 io142ndb3 36 nc 37 io141psb3 38 io140pdb3 39 io140ndb3 40 v cci b3 41 gnd 42 io138pdb3 43 io138ndb3 44 gec1/io137pdb3 45 gec0/io137ndb3 46 geb1/io136pdb3 47 geb0/io136ndb3 48 gea1/io135pdb3 49 gea0/io135ndb3 50 vmv3 51 gndq 52 gnd 53 vmv2 54 nc 55 gea2/io134rsb2 56 geb2/io133rsb2 57 gec2/io132rsb2 58 io131rsb2 59 io130rsb2 60 io129rsb2 61 io128rsb2 62 v cci b2 63 io125rsb2 64 io123rsb2 65 gnd 66 io121rsb2 67 io119rsb2 68 io117rsb2 69 io115rsb2 70 io113rsb2 71 v cc 72 v cci b2 208-pin pqfp pin number a3p400 function 73 io112rsb2 74 io111rsb2 75 io110rsb2 76 io109rsb2 77 io108rsb2 78 io107rsb2 79 io106rsb2 80 io104rsb2 81 gnd 82 io102rsb2 83 io101rsb2 84 io100rsb2 85 io99rsb2 86 io98rsb2 87 io97rsb2 88 v cc 89 v cci b2 90 io94rsb2 91 io92rsb2 92 io90rsb2 93 io88rsb2 94 io86rsb2 95 io84rsb2 96 gdc2/io82rsb2 97 gnd 98 gdb2/io81rsb2 99 gda2/io80rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 v pump 107 nc 108 tdo 208-pin pqfp pin number a3p400 function package pin assignments 3-28 v1.3 109 trst 110 v jtag 111 gda0/io79vdb1 112 gda1/io79udb1 113 gdb0/io78vdb1 114 gdb1/io78udb1 115 gdc0/io77vdb1 116 gdc1/io77udb1 117 io76vdb1 118 io76udb1 119 io75ndb1 120 io75pdb1 121 io74rsb1 122 gnd 123 v cci b1 124 nc 125 nc 126 v cc 127 io72ndb1 128 gcc2/io72pdb1 129 gcb2/io71psb1 130 gnd 131 gca2/io70psb1 132 gca1/io69pdb1 133 gca0/io69ndb1 134 gcb0/io68ndb1 135 gcb1/io68pdb1 136 gcc0/io67ndb1 137 gcc1/io67pdb1 138 io66ndb1 139 io66pdb1 140 v cci b1 141 gnd 142 v cc 143 io65rsb1 144 io64ndb1 208-pin pqfp pin number a3p400 function 145 io64pdb1 146 io63ndb1 147 io63pdb1 148 io62ndb1 149 gbc2/io62pdb1 150 io61ndb1 151 gbb2/io61pdb1 152 io60ndb1 153 gba2/io60pdb1 154 vmv1 155 gndq 156 gnd 157 vmv0 158 gba1/io59rsb0 159 gba0/io58rsb0 160 gbb1/io57rsb0 161 gbb0/io56rsb0 162 gnd 163 gbc1/io55rsb0 164 gbc0/io54rsb0 165 io52rsb0 166 io49rsb0 167 io46rsb0 168 io43rsb0 169 io40rsb0 170 v cci b0 171 v cc 172 io36rsb0 173 io35rsb0 174 io34rsb0 175 io33rsb0 176 io32rsb0 177 io31rsb0 178 gnd 179 io29rsb0 180 io28rsb0 208-pin pqfp pin number a3p400 function 181 io27rsb0 182 io26rsb0 183 io25rsb0 184 io24rsb0 185 io23rsb0 186 v cci b0 187 v cc 188 io21rsb0 189 io20rsb0 190 io19rsb0 191 io18rsb0 192 io17rsb0 193 io16rsb0 194 io15rsb0 195 gnd 196 io13rsb0 197 io11rsb0 198 io09rsb0 199 io07rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp pin number a3p400 function proasic3 packaging v1.3 3-29 208-pin pqfp pin number a3p600 function 1 gnd 2 gaa2/io174pdb3 3 io174ndb3 4 gab2/io173pdb3 5 io173ndb3 6 gac2/io172pdb3 7 io172ndb3 8 io171pdb3 9 io171ndb3 10 io170pdb3 11 io170ndb3 12 io169pdb3 13 io169ndb3 14 io168pdb3 15 io168ndb3 16 v cc 17 gnd 18 v cci b3 19 io166pdb3 20 io166ndb3 21 gfc1/io164pdb3 22 gfc0/io164ndb3 23 gfb1/io163pdb3 24 gfb0/io163ndb3 25 v complf 26 gfa0/io162npb3 27 v ccplf 28 gfa1/io162ppb3 29 gnd 30 gfa2/io161pdb3 31 io161ndb3 32 gfb2/io160pdb3 33 io160ndb3 34 gfc2/io159pdb3 35 io159ndb3 36 v cc 37 io152pdb3 38 io152ndb3 39 io150psb3 40 v cci b3 41 gnd 42 io147pdb3 43 io147ndb3 44 gec1/io146pdb3 45 gec0/io146ndb3 46 geb1/io145pdb3 47 geb0/io145ndb3 48 gea1/io144pdb3 49 gea0/io144ndb3 50 vmv3 51 gndq 52 gnd 53 vmv2 54 gea2/io143rsb2 55 geb2/io142rsb2 56 gec2/io141rsb2 57 io140rsb2 58 io139rsb2 59 io138rsb2 60 io137rsb2 61 io136rsb2 62 v cci b2 63 io135rsb2 64 io133rsb2 65 gnd 66 io131rsb2 67 io129rsb2 68 io127rsb2 69 io125rsb2 70 io123rsb2 71 v cc 72 v cci b2 208-pin pqfp pin number a3p600 function 73 io120rsb2 74 io119rsb2 75 io118rsb2 76 io117rsb2 77 io116rsb2 78 io115rsb2 79 io114rsb2 80 io112rsb2 81 gnd 82 io111rsb2 83 io110rsb2 84 io109rsb2 85 io108rsb2 86 io107rsb2 87 io106rsb2 88 v cc 89 v cci b2 90 io104rsb2 91 io102rsb2 92 io100rsb2 93 io98rsb2 94 io96rsb2 95 io92rsb2 96 gdc2/io91rsb2 97 gnd 98 gdb2/io90rsb2 99 gda2/io89rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 v pump 107 gndq 108 tdo 208-pin pqfp pin number a3p600 function package pin assignments 3-30 v1.3 109 trst 110 v jtag 111 gda0/io88ndb1 112 gda1/io88pdb1 113 gdb0/io87ndb1 114 gdb1/io87pdb1 115 gdc0/io86ndb1 116 gdc1/io86pdb1 117 io84ndb1 118 io84pdb1 119 io82ndb1 120 io82pdb1 121 io81psb1 122 gnd 123 v cci b1 124 io77ndb1 125 io77pdb1 126 nc 127 io74ndb1 128 gcc2/io74pdb1 129 gcb2/io73psb1 130 gnd 131 gca2/io72psb1 132 gca1/io71pdb1 133 gca0/io71ndb1 134 gcb0/io70ndb1 135 gcb1/io70pdb1 136 gcc0/io69ndb1 137 gcc1/io69pdb1 138 io67ndb1 139 io67pdb1 140 v cci b1 141 gnd 142 v cc 143 io65psb1 144 io64ndb1 208-pin pqfp pin number a3p600 function 145 io64pdb1 146 io63ndb1 147 io63pdb1 148 io62ndb1 149 gbc2/io62pdb1 150 io61ndb1 151 gbb2/io61pdb1 152 io60ndb1 153 gba2/io60pdb1 154 vmv1 155 gndq 156 gnd 157 vmv0 158 gba1/io59rsb0 159 gba0/io58rsb0 160 gbb1/io57rsb0 161 gbb0/io56rsb0 162 gnd 163 gbc1/io55rsb0 164 gbc0/io54rsb0 165 io52rsb0 166 io50rsb0 167 io48rsb0 168 io46rsb0 169 io44rsb0 170 v cci b0 171 v cc 172 io36rsb0 173 io35rsb0 174 io34rsb0 175 io33rsb0 176 io32rsb0 177 io31rsb0 178 gnd 179 io29rsb0 180 io28rsb0 208-pin pqfp pin number a3p600 function 181 io27rsb0 182 io26rsb0 183 io25rsb0 184 io24rsb0 185 io23rsb0 186 v cci b0 187 v cc 188 io20rsb0 189 io19rsb0 190 io18rsb0 191 io17rsb0 192 io16rsb0 193 io14rsb0 194 io12rsb0 195 gnd 196 io10rsb0 197 io09rsb0 198 io08rsb0 199 io07rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp pin number a3p600 function proasic3 packaging v1.3 3-31 208-pin pqfp pin number a3p1000 function 1 gnd 2 gaa2/io225pdb3 3 io225ndb3 4 gab2/io224pdb3 5 io224ndb3 6 gac2/io223pdb3 7 io223ndb3 8 io222pdb3 9 io222ndb3 10 io220pdb3 11 io220ndb3 12 io218pdb3 13 io218ndb3 14 io216pdb3 15 io216ndb3 16 v cc 17 gnd 18 v cci b3 19 io212pdb3 20 io212ndb3 21 gfc1/io209pdb3 22 gfc0/io209ndb3 23 gfb1/io208pdb3 24 gfb0/io208ndb3 25 v complf 26 gfa0/io207npb3 27 v ccplf 28 gfa1/io207ppb3 29 gnd 30 gfa2/io206pdb3 31 io206ndb3 32 gfb2/io205pdb3 33 io205ndb3 34 gfc2/io204pdb3 35 io204ndb3 36 v cc 37 io199pdb3 38 io199ndb3 39 io197psb3 40 v cci b3 41 gnd 42 io191pdb3 43 io191ndb3 44 gec1/io190pdb3 45 gec0/io190ndb3 46 geb1/io189pdb3 47 geb0/io189ndb3 48 gea1/io188pdb3 49 gea0/io188ndb3 50 vmv3 51 gndq 52 gnd 53 vmv2 54 gea2/io187rsb2 55 geb2/io186rsb2 56 gec2/io185rsb2 57 io184rsb2 58 io183rsb2 59 io182rsb2 60 io181rsb2 61 io180rsb2 62 v cci b2 63 io178rsb2 64 io176rsb2 65 gnd 66 io174rsb2 67 io172rsb2 68 io170rsb2 69 io168rsb2 70 io166rsb2 71 v cc 72 v cci b2 208-pin pqfp pin number a3p1000 function 73 io162rsb2 74 io160rsb2 75 io158rsb2 76 io156rsb2 77 io154rsb2 78 io152rsb2 79 io150rsb2 80 io148rsb2 81 gnd 82 io143rsb2 83 io141rsb2 84 io139rsb2 85 io137rsb2 86 io135rsb2 87 io133rsb2 88 v cc 89 v cci b2 90 io128rsb2 91 io126rsb2 92 io124rsb2 93 io122rsb2 94 io120rsb2 95 io118rsb2 96 gdc2/io116rsb2 97 gnd 98 gdb2/io115rsb2 99 gda2/io114rsb2 100 gndq 101 tck 102 tdi 103 tms 104 vmv2 105 gnd 106 v pump 107 gndq 108 tdo 208-pin pqfp pin number a3p1 000 function package pin assignments 3-32 v1.3 109 trst 110 v jtag 111 gda0/io113ndb1 112 gda1/io113pdb1 113 gdb0/io112ndb1 114 gdb1/io112pdb1 115 gdc0/io111ndb1 116 gdc1/io111pdb1 117 io109ndb1 118 io109pdb1 119 io106ndb1 120 io106pdb1 121 io104psb1 122 gnd 123 v cci b1 124 io99ndb1 125 io99pdb1 126 nc 127 io96ndb1 128 gcc2/io96pdb1 129 gcb2/io95psb1 130 gnd 131 gca2/io94psb1 132 gca1/io93pdb1 133 gca0/io93ndb1 134 gcb0/io92ndb1 135 gcb1/io92pdb1 136 gcc0/io91ndb1 137 gcc1/io91pdb1 138 io88ndb1 139 io88pdb1 140 v cci b1 141 gnd 142 v cc 143 io86psb1 144 io84ndb1 208-pin pqfp pin number a3p1000 function 145 io84pdb1 146 io82ndb1 147 io82pdb1 148 io80ndb1 149 gbc2/io80pdb1 150 io79ndb1 151 gbb2/io79pdb1 152 io78ndb1 153 gba2/io78pdb1 154 vmv1 155 gndq 156 gnd 157 vmv0 158 gba1/io77rsb0 159 gba0/io76rsb0 160 gbb1/io75rsb0 161 gbb0/io74rsb0 162 gnd 163 gbc1/io73rsb0 164 gbc0/io72rsb0 165 io70rsb0 166 io67rsb0 167 io63rsb0 168 io60rsb0 169 io57rsb0 170 v cci b0 171 v cc 172 io54rsb0 173 io51rsb0 174 io48rsb0 175 io45rsb0 176 io42rsb0 177 io40rsb0 178 gnd 179 io38rsb0 180 io35rsb0 208-pin pqfp pin number a3p1000 function 181 io33rsb0 182 io31rsb0 183 io29rsb0 184 io27rsb0 185 io25rsb0 186 v cci b0 187 v cc 188 io22rsb0 189 io20rsb0 190 io18rsb0 191 io16rsb0 192 io15rsb0 193 io14rsb0 194 io13rsb0 195 gnd 196 io12rsb0 197 io11rsb0 198 io10rsb0 199 io09rsb0 200 v cci b0 201 gac1/io05rsb0 202 gac0/io04rsb0 203 gab1/io03rsb0 204 gab0/io02rsb0 205 gaa1/io01rsb0 206 gaa0/io00rsb0 207 gndq 208 vmv0 208-pin pqfp pin number a3p1 000 function proasic3 packaging v1.3 3-33 144-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the bottom view of the package. 1 2 3 4 5 6 7 8 9 10 11 12 a b c d e f g h j k l m a1 ball pad corner package pin assignments 3-34 v1.3 144-pin fbga pin number a3p060 function a1 gndq a2 vmv0 a3 gab0/io04rsb0 a4 gab1/io05rsb0 a5 io08rsb0 a6 gnd a7 io11rsb0 a8 v cc a9 io16rsb0 a10 gba0/io23rsb0 a11 gba1/io24rsb0 a12 gndq b1 gab2/io53rsb1 b2 gnd b3 gaa0/io02rsb0 b4 gaa1/io03rsb0 b5 io00rsb0 b6 io10rsb0 b7 io12rsb0 b8 io14rsb0 b9 gbb0/io21rsb0 b10 gbb1/io22rsb0 b11 gnd b12 vmv0 c1 io95rsb1 c2 gfa2/io83rsb1 c3 gac2/io94rsb1 c4 v cc c5 io01rsb0 c6 io09rsb0 c7 io13rsb0 c8 io15rsb0 c9 io17rsb0 c10 gba2/io25rsb0 c11 io26rsb0 c12 gbc2/io29rsb0 d1 io91rsb1 d2 io92rsb1 d3 io93rsb1 d4 gaa2/io51rsb1 d5 gac0/io06rsb0 d6 gac1/io07rsb0 d7 gbc0/io19rsb0 d8 gbc1/io20rsb0 d9 gbb2/io27rsb0 d10 io18rsb0 d11 io28rsb0 d12 gcb1/io37rsb0 e1 v cc e2 gfc0/io88rsb1 e3 gfc1/io89rsb1 e4 v cci b1 e5 io52rsb1 e6 v cci b0 e7 v cci b0 e8 gcc1/io35rsb0 e9 v cci b0 e10 v cc e11 gca0/io40rsb0 e12 io30rsb0 f1 gfb0/io86rsb1 f2 v complf f3 gfb1/io87rsb1 f4 io90rsb1 f5 gnd f6 gnd f7 gnd f8 gcc0/io36rsb0 f9 gcb0/io38rsb0 f10 gnd f11 gca1/io39rsb0 f12 gca2/io41rsb0 144-pin fbga pin number a3p060 function g1 gfa1/io84rsb1 g2 gnd g3 v ccplf g4 gfa0/io85rsb1 g5 gnd g6 gnd g7 gnd g8 gdc1/io45rsb0 g9 io32rsb0 g10 gcc2/io43rsb0 g11 io31rsb0 g12 gcb2/io42rsb0 h1 v cc h2 gfb2/io82rsb1 h3 gfc2/io81rsb1 h4 gec1/io77rsb1 h5 v cc h6 io34rsb0 h7 io44rsb0 h8 gdb2/io55rsb1 h9 gdc0/io46rsb0 h10 v cci b0 h11 io33rsb0 h12 v cc j1 geb1/io75rsb1 j2 io78rsb1 j3 v cci b1 j4 gec0/io76rsb1 j5 io79rsb1 j6 io80rsb1 j7 v cc j8 tck j9 gda2/io54rsb1 j10 tdo j11 gda1/io49rsb0 j12 gdb1/io47rsb0 144-pin fbga pin number a3p060 function proasic3 packaging v1.3 3-35 k1 geb0/io74rsb1 k2 gea1/io73rsb1 k3 gea0/io72rsb1 k4 gea2/io71rsb1 k5 io65rsb1 k6 io64rsb1 k7 gnd k8 io57rsb1 k9 gdc2/io56rsb1 k10 gnd k11 gda0/io50rsb0 k12 gdb0/io48rsb0 l1 gnd l2 vmv1 l3 geb2/io70rsb1 l4 io67rsb1 l5 v cci b1 l6 io62rsb1 l7 io59rsb1 l8 io58rsb1 l9 tms l10 v jtag l11 vmv1 l12 trst m1 gndq m2 gec2/io69rsb1 m3 io68rsb1 m4 io66rsb1 m5 io63rsb1 m6 io61rsb1 m7 io60rsb1 m8 nc m9 tdi m10 v cci b1 m11 v pump m12 gndq 144-pin fbga pin number a3p060 function package pin assignments 3-36 v1.3 144-pin fbga pin number a3p125 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io11rsb0 a6 gnd a7 io18rsb0 a8 v cc a9 io25rsb0 a10 gba0/io39rsb0 a11 gba1/io40rsb0 a12 gndq b1 gab2/io69rsb1 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io08rsb0 b6 io14rsb0 b7 io19rsb0 b8 io22rsb0 b9 gbb0/io37rsb0 b10 gbb1/io38rsb0 b11 gnd b12 vmv0 c1 io132rsb1 c2 gfa2/io120rsb1 c3 gac2/io131rsb1 c4 v cc c5 io10rsb0 c6 io12rsb0 c7 io21rsb0 c8 io24rsb0 c9 io27rsb0 c10 gba2/io41rsb0 c11 io42rsb0 c12 gbc2/io45rsb0 d1 io128rsb1 d2 io129rsb1 d3 io130rsb1 d4 gaa2/io67rsb1 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io35rsb0 d8 gbc1/io36rsb0 d9 gbb2/io43rsb0 d10 io28rsb0 d11 io44rsb0 d12 gcb1/io53rsb0 e1 v cc e2 gfc0/io125rsb1 e3 gfc1/io126rsb1 e4 v cci b1 e5 io68rsb1 e6 v cci b0 e7 v cci b0 e8 gcc1/io51rsb0 e9 v cci b0 e10 v cc e11 gca0/io56rsb0 e12 io46rsb0 f1 gfb0/io123rsb1 f2 v complf f3 gfb1/io124rsb1 f4 io127rsb1 f5 gnd f6 gnd f7 gnd f8 gcc0/io52rsb0 f9 gcb0/io54rsb0 f10 gnd f11 gca1/io55rsb0 f12 gca2/io57rsb0 144-pin fbga pin number a3p125 function g1 gfa1/io121rsb1 g2 gnd g3 v ccplf g4 gfa0/io122rsb1 g5 gnd g6 gnd g7 gnd g8 gdc1/io61rsb0 g9 io48rsb0 g10 gcc2/io59rsb0 g11 io47rsb0 g12 gcb2/io58rsb0 h1 v cc h2 gfb2/io119rsb1 h3 gfc2/io118rsb1 h4 gec1/io112rsb1 h5 v cc h6 io50rsb0 h7 io60rsb0 h8 gdb2/io71rsb1 h9 gdc0/io62rsb0 h10 v cci b0 h11 io49rsb0 h12 v cc j1 geb1/io110rsb1 j2 io115rsb1 j3 v cci b1 j4 gec0/io111rsb1 j5 io116rsb1 j6 io117rsb1 j7 v cc j8 tck j9 gda2/io70rsb1 j10 tdo j11 gda1/io65rsb0 j12 gdb1/io63rsb0 144-pin fbga pin number a3p125 function proasic3 packaging v1.3 3-37 k1 geb0/io109rsb1 k2 gea1/io108rsb1 k3 gea0/io107rsb1 k4 gea2/io106rsb1 k5 io100rsb1 k6 io98rsb1 k7 gnd k8 io73rsb1 k9 gdc2/io72rsb1 k10 gnd k11 gda0/io66rsb0 k12 gdb0/io64rsb0 l1 gnd l2 vmv1 l3 geb2/io105rsb1 l4 io102rsb1 l5 v cci b1 l6 io95rsb1 l7 io85rsb1 l8 io74rsb1 l9 tms l10 v jtag l11 vmv1 l12 trst m1 gndq m2 gec2/io104rsb1 m3 io103rsb1 m4 io101rsb1 m5 io97rsb1 m6 io94rsb1 m7 io86rsb1 m8 io75rsb1 m9 tdi m10 v cci b1 m11 v pump m12 gndq 144-pin fbga pin number a3p125 function package pin assignments 3-38 v1.3 144-pin fbga pin number a3p250 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io16rsb0 a6 gnd a7 io29rsb0 a8 v cc a9 io33rsb0 a10 gba0/io39rsb0 a11 gba1/io40rsb0 a12 gndq b1 gab2/io117udb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io14rsb0 b6 io19rsb0 b7 io22rsb0 b8 io30rsb0 b9 gbb0/io37rsb0 b10 gbb1/io38rsb0 b11 gnd b12 vmv1 c1 io117vdb3 c2 gfa2/io107ppb3 c3 gac2/io116udb3 c4 v cc c5 io12rsb0 c6 io17rsb0 c7 io24rsb0 c8 io31rsb0 c9 io34rsb0 c10 gba2/io41pdb1 c11 io41ndb1 c12 gbc2/io43ppb1 d1 io112ndb3 d2 io112pdb3 d3 io116vdb3 d4 gaa2/io118upb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io35rsb0 d8 gbc1/io36rsb0 d9 gbb2/io42pdb1 d10 io42ndb1 d11 io43npb1 d12 gcb1/io49ppb1 e1 v cc e2 gfc0/io110ndb3 e3 gfc1/io110pdb3 e4 v cci b3 e5 io118vpb3 e6 v cci b0 e7 v cci b0 e8 gcc1/io48pdb1 e9 v cci b1 e10 v cc e11 gca0/io50ndb1 e12 io51ndb1 f1 gfb0/io109npb3 f2 v complf f3 gfb1/io109ppb3 f4 io107npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io48ndb1 f9 gcb0/io49npb1 f10 gnd f11 gca1/io50pdb1 f12 gca2/io51pdb1 144-pin fbga pin number a3p250 function g1 gfa1/io108ppb3 g2 gnd g3 v ccplf g4 gfa0/io108npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io58upb1 g9 io53ndb1 g10 gcc2/io53pdb1 g11 io52ndb1 g12 gcb2/io52pdb1 h1 v cc h2 gfb2/io106pdb3 h3 gfc2/io105psb3 h4 gec1/io100pdb3 h5 v cc h6 io79rsb2 h7 io65rsb2 h8 gdb2/io62rsb2 h9 gdc0/io58vpb1 h10 v cci b1 h11 io54psb1 h12 v cc j1 geb1/io99pdb3 j2 io106ndb3 j3 v cci b3 j4 gec0/io100ndb3 j5 io88rsb2 j6 io81rsb2 j7 v cc j8 tck j9 gda2/io61rsb2 j10 tdo j11 gda1/io60udb1 j12 gdb1/io59udb1 144-pin fbga pin number a3p250 function proasic3 packaging v1.3 3-39 k1 geb0/io99ndb3 k2 gea1/io98pdb3 k3 gea0/io98ndb3 k4 gea2/io97rsb2 k5 io90rsb2 k6 io84rsb2 k7 gnd k8 io66rsb2 k9 gdc2/io63rsb2 k10 gnd k11 gda0/io60vdb1 k12 gdb0/io59vdb1 l1 gnd l2 vmv3 l3 geb2/io96rsb2 l4 io91rsb2 l5 v cci b2 l6 io82rsb2 l7 io80rsb2 l8 io72rsb2 l9 tms l10 v jtag l11 vmv2 l12 trst m1 gndq m2 gec2/io95rsb2 m3 io92rsb2 m4 io89rsb2 m5 io87rsb2 m6 io85rsb2 m7 io78rsb2 m8 io76rsb2 m9 tdi m10 v cci b2 m11 v pump m12 gndq 144-pin fbga pin number a3p250 function package pin assignments 3-40 v1.3 144-pin fbga pin number a3p400 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io16rsb0 a6 gnd a7 io30rsb0 a8 v cc a9 io34rsb0 a10 gba0/io58rsb0 a11 gba1/io59rsb0 a12 gndq b1 gab2/io154udb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io14rsb0 b6 io19rsb0 b7 io23rsb0 b8 io31rsb0 b9 gbb0/io56rsb0 b10 gbb1/io57rsb0 b11 gnd b12 vmv1 c1 io154vdb3 c2 gfa2/io144ppb3 c3 gac2/io153udb3 c4 v cc c5 io12rsb0 c6 io17rsb0 c7 io25rsb0 c8 io32rsb0 c9 io53rsb0 c10 gba2/io60pdb1 c11 io60ndb1 c12 gbc2/io62ppb1 d1 io149ndb3 d2 io149pdb3 d3 io153vdb3 d4 gaa2/io155upb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io54rsb0 d8 gbc1/io55rsb0 d9 gbb2/io61pdb1 d10 io61ndb1 d11 io62npb1 d12 gcb1/io68ppb1 e1 v cc e2 gfc0/io147ndb3 e3 gfc1/io147pdb3 e4 v cci b3 e5 io155vpb3 e6 v cci b0 e7 v cci b0 e8 gcc1/io67pdb1 e9 v cci b1 e10 v cc e11 gca0/io69ndb1 e12 io70ndb1 f1 gfb0/io146npb3 f2 v complf f3 gfb1/io146ppb3 f4 io144npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io67ndb1 f9 gcb0/io68npb1 f10 gnd f11 gca1/io69pdb1 f12 gca2/io70pdb1 144-pin fbga pin number a3p400 function g1 gfa1/io145ppb3 g2 gnd g3 v ccplf g4 gfa0/io145npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io77upb1 g9 io72ndb1 g10 gcc2/io72pdb1 g11 io71ndb1 g12 gcb2/io71pdb1 h1 v cc h2 gfb2/io143pdb3 h3 gfc2/io142psb3 h4 gec1/io137pdb3 h5 v cc h6 io75pdb1 h7 io75ndb1 h8 gdb2/io81rsb2 h9 gdc0/io77vpb1 h10 v cci b1 h11 io73psb1 h12 v cc j1 geb1/io136pdb3 j2 io143ndb3 j3 v cci b3 j4 gec0/io137ndb3 j5 io125rsb2 j6 io116rsb2 j7 v cc j8 tck j9 gda2/io80rsb2 j10 tdo j11 gda1/io79udb1 j12 gdb1/io78udb1 144-pin fbga pin number a3p400 function proasic3 packaging v1.3 3-41 k1 geb0/io136ndb3 k2 gea1/io135pdb3 k3 gea0/io135ndb3 k4 gea2/io134rsb2 k5 io127rsb2 k6 io121rsb2 k7 gnd k8 io104rsb2 k9 gdc2/io82rsb2 k10 gnd k11 gda0/io79vdb1 k12 gdb0/io78vdb1 l1 gnd l2 vmv3 l3 geb2/io133rsb2 l4 io128rsb2 l5 v cci b2 l6 io119rsb2 l7 io114rsb2 l8 io110rsb2 l9 tms l10 v jtag l11 vmv2 l12 trst m1 gndq m2 gec2/io132rsb2 m3 io129rsb2 m4 io126rsb2 m5 io124rsb2 m6 io122rsb2 m7 io117rsb2 m8 io115rsb2 m9 tdi m10 v cci b2 m11 v pump m12 gndq 144-pin fbga pin number a3p400 function package pin assignments 3-42 v1.3 144-pin fbga pin number a3p600 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io10rsb0 a6 gnd a7 io34rsb0 a8 v cc a9 io50rsb0 a10 gba0/io58rsb0 a11 gba1/io59rsb0 a12 gndq b1 gab2/io173pdb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io13rsb0 b6 io19rsb0 b7 io31rsb0 b8 io39rsb0 b9 gbb0/io56rsb0 b10 gbb1/io57rsb0 b11 gnd b12 vmv1 c1 io173ndb3 c2 gfa2/io161ppb3 c3 gac2/io172pdb3 c4 v cc c5 io16rsb0 c6 io25rsb0 c7 io28rsb0 c8 io42rsb0 c9 io45rsb0 c10 gba2/io60pdb1 c11 io60ndb1 c12 gbc2/io62ppb1 d1 io169pdb3 d2 io169ndb3 d3 io172ndb3 d4 gaa2/io174ppb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io54rsb0 d8 gbc1/io55rsb0 d9 gbb2/io61pdb1 d10 io61ndb1 d11 io62npb1 d12 gcb1/io70ppb1 e1 v cc e2 gfc0/io164ndb3 e3 gfc1/io164pdb3 e4 v cci b3 e5 io174npb3 e6 v cci b0 e7 v cci b0 e8 gcc1/io69pdb1 e9 v cci b1 e10 v cc e11 gca0/io71ndb1 e12 io72ndb1 f1 gfb0/io163npb3 f2 v complf f3 gfb1/io163ppb3 f4 io161npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io69ndb1 f9 gcb0/io70npb1 f10 gnd f11 gca1/io71pdb1 f12 gca2/io72pdb1 144-pin fbga pin number a3p600 function g1 gfa1/io162ppb3 g2 gnd g3 v ccplf g4 gfa0/io162npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io86ppb1 g9 io74ndb1 g10 gcc2/io74pdb1 g11 io73ndb1 g12 gcb2/io73pdb1 h1 v cc h2 gfb2/io160pdb3 h3 gfc2/io159psb3 h4 gec1/io146pdb3 h5 v cc h6 io80pdb1 h7 io80ndb1 h8 gdb2/io90rsb2 h9 gdc0/io86npb1 h10 v cci b1 h11 io84psb1 h12 v cc j1 geb1/io145pdb3 j2 io160ndb3 j3 v cci b3 j4 gec0/io146ndb3 j5 io129rsb2 j6 io131rsb2 j7 v cc j8 tck j9 gda2/io89rsb2 j10 tdo j11 gda1/io88pdb1 j12 gdb1/io87pdb1 144-pin fbga pin number a3p600 function proasic3 packaging v1.3 3-43 k1 geb0/io145ndb3 k2 gea1/io144pdb3 k3 gea0/io144ndb3 k4 gea2/io143rsb2 k5 io119rsb2 k6 io111rsb2 k7 gnd k8 io94rsb2 k9 gdc2/io91rsb2 k10 gnd k11 gda0/io88ndb1 k12 gdb0/io87ndb1 l1 gnd l2 vmv3 l3 geb2/io142rsb2 l4 io136rsb2 l5 v cci b2 l6 io115rsb2 l7 io103rsb2 l8 io97rsb2 l9 tms l10 v jtag l11 vmv2 l12 trst m1 gndq m2 gec2/io141rsb2 m3 io138rsb2 m4 io123rsb2 m5 io126rsb2 m6 io134rsb2 m7 io108rsb2 m8 io99rsb2 m9 tdi m10 v cci b2 m11 v pump m12 gndq 144-pin fbga pin number a3p600 function package pin assignments 3-44 v1.3 144-pin fbga pin number a3p1000 function a1 gndq a2 vmv0 a3 gab0/io02rsb0 a4 gab1/io03rsb0 a5 io10rsb0 a6 gnd a7 io44rsb0 a8 v cc a9 io69rsb0 a10 gba0/io76rsb0 a11 gba1/io77rsb0 a12 gndq b1 gab2/io224pdb3 b2 gnd b3 gaa0/io00rsb0 b4 gaa1/io01rsb0 b5 io13rsb0 b6 io26rsb0 b7 io35rsb0 b8 io60rsb0 b9 gbb0/io74rsb0 b10 gbb1/io75rsb0 b11 gnd b12 vmv1 c1 io224ndb3 c2 gfa2/io206ppb3 c3 gac2/io223pdb3 c4 v cc c5 io16rsb0 c6 io29rsb0 c7 io32rsb0 c8 io63rsb0 c9 io66rsb0 c10 gba2/io78pdb1 c11 io78ndb1 c12 gbc2/io80ppb1 d1 io213pdb3 d2 io213ndb3 d3 io223ndb3 d4 gaa2/io225ppb3 d5 gac0/io04rsb0 d6 gac1/io05rsb0 d7 gbc0/io72rsb0 d8 gbc1/io73rsb0 d9 gbb2/io79pdb1 d10 io79ndb1 d11 io80npb1 d12 gcb1/io92ppb1 e1 v cc e2 gfc0/io209ndb3 e3 gfc1/io209pdb3 e4 vccib3 e5 io225npb3 e6 v cci b0 e7 v cci b0 e8 gcc1/io91pdb1 e9 v cci b1 e10 v cc e11 gca0/io93ndb1 e12 io94ndb1 f1 gfb0/io208npb3 f2 v complf f3 gfb1/io208ppb3 f4 io206npb3 f5 gnd f6 gnd f7 gnd f8 gcc0/io91ndb1 f9 gcb0/io92npb1 f10 gnd f11 gca1/io93pdb1 f12 gca2/io94pdb1 144-pin fbga pin number a3p1000 function g1 gfa1/io207ppb3 g2 gnd g3 v ccplf g4 gfa0/io207npb3 g5 gnd g6 gnd g7 gnd g8 gdc1/io111ppb1 g9 io96ndb1 g10 gcc2/io96pdb1 g11 io95ndb1 g12 gcb2/io95pdb1 h1 v cc h2 gfb2/io205pdb3 h3 gfc2/io204psb3 h4 gec1/io190pdb3 h5 v cc h6 io105pdb1 h7 io105ndb1 h8 gdb2/io115rsb2 h9 gdc0/io111npb1 h10 v cci b1 h11 io101psb1 h12 v cc j1 geb1/io189pdb3 j2 io205ndb3 j3 v cci b3 j4 gec0/io190ndb3 j5 io160rsb2 j6 io157rsb2 j7 v cc j8 tck j9 gda2/io114rsb2 j10 tdo j11 gda1/io113pdb1 j12 gdb1/io112pdb1 144-pin fbga pin number a3p1000 function proasic3 packaging v1.3 3-45 k1 geb0/io189ndb3 k2 gea1/io188pdb3 k3 gea0/io188ndb3 k4 gea2/io187rsb2 k5 io169rsb2 k6 io152rsb2 k7 gnd k8 io117rsb2 k9 gdc2/io116rsb2 k10 gnd k11 gda0/io113ndb1 k12 gdb0/io112ndb1 l1 gnd l2 vmv3 l3 geb2/io186rsb2 l4 io172rsb2 l5 v cci b2 l6 io153rsb2 l7 io144rsb2 l8 io140rsb2 l9 tms l10 v jtag l11 vmv2 l12 trst m1 gndq m2 gec2/io185rsb2 m3 io173rsb2 m4 io168rsb2 m5 io161rsb2 m6 io156rsb2 m7 io145rsb2 m8 io141rsb2 m9 tdi m10 v cci b2 m11 v pump m12 gndq 144-pin fbga pin number a3p1000 function package pin assignments 3-46 v1.3 256-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the bottom view of the package. 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 c e g j l n r d f h k m p t b a a1 ball pad corner proasic3 packaging v1.3 3-47 256-pin fbga pin number a3p250 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io07rsb0 a6 io10rsb0 a7 io11rsb0 a8 io15rsb0 a9 io20rsb0 a10 io25rsb0 a11 io29rsb0 a12 io33rsb0 a13 gbb1/io38rsb0 a14 gba0/io39rsb0 a15 gba1/io40rsb0 a16 gnd b1 gab2/io117udb3 b2 gaa2/io118udb3 b3 nc b4 gab1/io03rsb0 b5 io06rsb0 b6 io09rsb0 b7 io12rsb0 b8 io16rsb0 b9 io21rsb0 b10 io26rsb0 b11 io30rsb0 b12 gbc1/io36rsb0 b13 gbb0/io37rsb0 b14 nc b15 gba2/io41pdb1 b16 io41ndb1 c1 io117vdb3 c2 io118vdb3 c3 nc c4 nc c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io13rsb0 c8 io17rsb0 c9 io22rsb0 c10 io27rsb0 c11 io31rsb0 c12 gbc0/io35rsb0 c13 io34rsb0 c14 nc c15 io42npb1 c16 io44pdb1 d1 io114vdb3 d2 io114udb3 d3 gac2/io116udb3 d4 nc d5 gndq d6 io08rsb0 d7 io14rsb0 d8 io18rsb0 d9 io23rsb0 d10 io28rsb0 d11 io32rsb0 d12 gndq d13 nc d14 gbb2/io42ppb1 d15 nc d16 io44ndb1 e1 io113pdb3 e2 nc e3 io116vdb3 e4 io115udb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io19rsb0 256-pin fbga pin number a3p250 function e9 io24rsb0 e10 v cci b0 e11 v cci b0 e12 vmv1 e13 gbc2/io43pdb1 e14 io46rsb1 e15 nc e16 io45pdb1 f1 io113ndb3 f2 io112ppb3 f3 nc f4 io115vdb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io43ndb1 f14 nc f15 io47ppb1 f16 io45ndb1 g1 io111ndb3 g2 io111pdb3 g3 io112npb3 g4 gfc1/io110ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 256-pin fbga pin number a3p250 function package pin assignments 3-48 v1.3 g13 gcc1/io48ppb1 g14 io47npb1 g15 io54pdb1 g16 io54ndb1 h1 gfb0/io109npb3 h2 gfa0/io108ndb3 h3 gfb1/io109ppb3 h4 v complf h5 gfc0/io110npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io48npb1 h13 gcb1/io49ppb1 h14 gca0/io50npb1 h15 nc h16 gcb0/io49npb1 j1 gfa2/io107ppb3 j2 gfa1/io108pdb3 j3 v ccplf j4 io106ndb3 j5 gfb2/io106pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io52ppb1 j13 gca1/io50ppb1 j14 gcc2/io53ppb1 j15 nc j16 gca2/io51pdb1 256-pin fbga pin number a3p250 function k1 gfc2/io105pdb3 k2 io107npb3 k3 io104ppb3 k4 nc k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io52npb1 k14 io55rsb1 k15 io53npb1 k16 io51ndb1 l1 io105ndb3 l2 io104npb3 l3 nc l4 io102rsb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io59vpb1 l14 io57vdb1 l15 io57udb1 l16 io56pdb1 m1 io103pdb3 m2 nc m3 io101npb3 m4 gec0/io100npb3 256-pin fbga pin number a3p250 function m5 vmv3 m6 v cci b2 m7 v cci b2 m8 nc m9 io74rsb2 m10 v cci b2 m11 v cci b2 m12 vmv2 m13 nc m14 gdb1/io59upb1 m15 gdc1/io58udb1 m16 io56ndb1 n1 io103ndb3 n2 io101ppb3 n3 gec1/io100ppb3 n4 nc n5 gndq n6 gea2/io97rsb2 n7 io86rsb2 n8 io82rsb2 n9 io75rsb2 n10 io69rsb2 n11 io64rsb2 n12 gndq n13 nc n14 v jtag n15 gdc0/io58vdb1 n16 gda1/io60udb1 p1 geb1/io99pdb3 p2 geb0/io99ndb3 p3 nc p4 nc p5 io92rsb2 p6 io89rsb2 p7 io85rsb2 p8 io81rsb2 256-pin fbga pin number a3p250 function proasic3 packaging v1.3 3-49 p9 io76rsb2 p10 io71rsb2 p11 io66rsb2 p12 nc p13 tck p14 v pump p15 trst p16 gda0/io60vdb1 r1 gea1/io98pdb3 r2 gea0/io98ndb3 r3 nc r4 gec2/io95rsb2 r5 io91rsb2 r6 io88rsb2 r7 io84rsb2 r8 io80rsb2 r9 io77rsb2 r10 io72rsb2 r11 io68rsb2 r12 io65rsb2 r13 gdb2/io62rsb2 r14 tdi r15 nc r16 tdo t1 gnd t2 io94rsb2 t3 geb2/io96rsb2 t4 io93rsb2 t5 io90rsb2 t6 io87rsb2 t7 io83rsb2 t8 io79rsb2 t9 io78rsb2 t10 io73rsb2 t11 io70rsb2 t12 gdc2/io63rsb2 256-pin fbga pin number a3p250 function t13 io67rsb2 t14 gda2/io61rsb2 t15 tms t16 gnd 256-pin fbga pin number a3p250 function package pin assignments 3-50 v1.3 256-pin fbga pin number a3p400 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io16rsb0 a6 io17rsb0 a7 io22rsb0 a8 io28rsb0 a9 io34rsb0 a10 io37rsb0 a11 io41rsb0 a12 io43rsb0 a13 gbb1/io57rsb0 a14 gba0/io58rsb0 a15 gba1/io59rsb0 a16 gnd b1 gab2/io154udb3 b2 gaa2/io155udb3 b3 io12rsb0 b4 gab1/io03rsb0 b5 io13rsb0 b6 io14rsb0 b7 io21rsb0 b8 io27rsb0 b9 io32rsb0 b10 io38rsb0 b11 io42rsb0 b12 gbc1/io55rsb0 b13 gbb0/io56rsb0 b14 io44rsb0 b15 gba2/io60pdb1 b16 io60ndb1 c1 io154vdb3 c2 io155vdb3 c3 io11rsb0 c4 io07rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io20rsb0 c8 io24rsb0 c9 io33rsb0 c10 io39rsb0 c11 io45rsb0 c12 gbc0/io54rsb0 c13 io48rsb0 c14 vmv0 c15 io61npb1 c16 io63pdb1 d1 io151vdb3 d2 io151udb3 d3 gac2/io153udb3 d4 io06rsb0 d5 gndq d6 io10rsb0 d7 io19rsb0 d8 io26rsb0 d9 io30rsb0 d10 io40rsb0 d11 io46rsb0 d12 gndq d13 io47rsb0 d14 gbb2/io61ppb1 d15 io53rsb0 d16 io63ndb1 e1 io150pdb3 e2 io08rsb0 e3 io153vdb3 e4 io152vdb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io25rsb0 256-pin fbga pin number a3p400 function e9 io31rsb0 e10 v cci b0 e11 v cci b0 e12 vmv1 e13 gbc2/io62pdb1 e14 io65rsb1 e15 io52rsb0 e16 io66pdb1 f1 io150ndb3 f2 io149npb3 f3 io09rsb0 f4 io152udb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io62ndb1 f14 io49rsb0 f15 io64ppb1 f16 io66ndb1 g1 io148ndb3 g2 io148pdb3 g3 io149ppb3 g4 gfc1/io147ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 256-pin fbga pin number a3p400 function proasic3 packaging v1.3 3-51 g13 gcc1/io67ppb1 g14 io64npb1 g15 io73pdb1 g16 io73ndb1 h1 gfb0/io146npb3 h2 gfa0/io145ndb3 h3 gfb1/io146ppb3 h4 v complf h5 gfc0/io147npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io67npb1 h13 gcb1/io68ppb1 h14 gca0/io69npb1 h15 nc h16 gcb0/io68npb1 j1 gfa2/io144ppb3 j2 gfa1/io145pdb3 j3 v ccplf j4 io143ndb3 j5 gfb2/io143pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io71ppb1 j13 gca1/io69ppb1 j14 gcc2/io72ppb1 j15 nc j16 gca2/io70pdb1 256-pin fbga pin number a3p400 function k1 gfc2/io142pdb3 k2 io144npb3 k3 io141ppb3 k4 io120rsb2 k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io71npb1 k14 io74rsb1 k15 io72npb1 k16 io70ndb1 l1 io142ndb3 l2 io141npb3 l3 io125rsb2 l4 io139rsb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io78vpb1 l14 io76vdb1 l15 io76udb1 l16 io75pdb1 m1 io140pdb3 m2 io130rsb2 m3 io138npb3 m4 gec0/io137npb3 256-pin fbga pin number a3p400 function m5 vmv3 m6 v cci b2 m7 v cci b2 m8 io108rsb2 m9 io101rsb2 m10 v cci b2 m11 v cci b2 m12 vmv2 m13 io83rsb2 m14 gdb1/io78upb1 m15 gdc1/io77udb1 m16 io75ndb1 n1 io140ndb3 n2 io138ppb3 n3 gec1/io137ppb3 n4 io131rsb2 n5 gndq n6 gea2/io134rsb2 n7 io117rsb2 n8 io111rsb2 n9 io99rsb2 n10 io94rsb2 n11 io87rsb2 n12 gndq n13 io93rsb2 n14 v jtag n15 gdc0/io77vdb1 n16 gda1/io79udb1 p1 geb1/io136pdb3 p2 geb0/io136ndb3 p3 vmv2 p4 io129rsb2 p5 io128rsb2 p6 io122rsb2 p7 io115rsb2 p8 io110rsb2 256-pin fbga pin number a3p400 function package pin assignments 3-52 v1.3 p9 io98rsb2 p10 io95rsb2 p11 io88rsb2 p12 io84rsb2 p13 tck p14 v pump p15 trst p16 gda0/io79vdb1 r1 gea1/io135pdb3 r2 gea0/io135ndb3 r3 io127rsb2 r4 gec2/io132rsb2 r5 io123rsb2 r6 io118rsb2 r7 io112rsb2 r8 io106rsb2 r9 io100rsb2 r10 io96rsb2 r11 io89rsb2 r12 io85rsb2 r13 gdb2/io81rsb2 r14 tdi r15 nc r16 tdo t1 gnd t2 io126rsb2 t3 geb2/io133rsb2 t4 io124rsb2 t5 io116rsb2 t6 io113rsb2 t7 io107rsb2 t8 io105rsb2 t9 io102rsb2 t10 io97rsb2 t11 io92rsb2 t12 gdc2/io82rsb2 256-pin fbga pin number a3p400 function t13 io86rsb2 t14 gda2/io80rsb2 t15 tms t16 gnd 256-pin fbga pin number a3p400 function proasic3 packaging v1.3 3-53 256-pin fbga pin number a3p600 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io11rsb0 a6 io16rsb0 a7 io18rsb0 a8 io28rsb0 a9 io34rsb0 a10 io37rsb0 a11 io41rsb0 a12 io43rsb0 a13 gbb1/io57rsb0 a14 gba0/io58rsb0 a15 gba1/io59rsb0 a16 gnd b1 gab2/io173pdb3 b2 gaa2/io174pdb3 b3 gndq b4 gab1/io03rsb0 b5 io13rsb0 b6 io14rsb0 b7 io21rsb0 b8 io27rsb0 b9 io32rsb0 b10 io38rsb0 b11 io42rsb0 b12 gbc1/io55rsb0 b13 gbb0/io56rsb0 b14 io52rsb0 b15 gba2/io60pdb1 b16 io60ndb1 c1 io173ndb3 c2 io174ndb3 c3 vmv3 c4 io07rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io20rsb0 c8 io24rsb0 c9 io33rsb0 c10 io39rsb0 c11 io44rsb0 c12 gbc0/io54rsb0 c13 io51rsb0 c14 vmv0 c15 io61npb1 c16 io63pdb1 d1 io171ndb3 d2 io171pdb3 d3 gac2/io172pdb3 d4 io06rsb0 d5 gndq d6 io10rsb0 d7 io19rsb0 d8 io26rsb0 d9 io30rsb0 d10 io40rsb0 d11 io45rsb0 d12 gndq d13 io50rsb0 d14 gbb2/io61ppb1 d15 io53rsb0 d16 io63ndb1 e1 io166pdb3 e2 io167npb3 e3 io172ndb3 e4 io169ndb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io25rsb0 256-pin fbga pin number a3p600 function e9 io31rsb0 e10 v cci b0 e11 v cci b0 e12 vmv1 e13 gbc2/io62pdb1 e14 io67ppb1 e15 io64ppb1 e16 io66pdb1 f1 io166ndb3 f2 io168npb3 f3 io167ppb3 f4 io169pdb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io62ndb1 f14 io64npb1 f15 io65ppb1 f16 io66ndb1 g1 io165ndb3 g2 io165pdb3 g3 io168ppb3 g4 gfc1/io164ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 256-pin fbga pin number a3p600 function package pin assignments 3-54 v1.3 g13 gcc1/io69ppb1 g14 io65npb1 g15 io75pdb1 g16 io75ndb1 h1 gfb0/io163npb3 h2 gfa0/io162ndb3 h3 gfb1/io163ppb3 h4 v complf h5 gfc0/io164npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io69npb1 h13 gcb1/io70ppb1 h14 gca0/io71npb1 h15 io67npb1 h16 gcb0/io70npb1 j1 gfa2/io161ppb3 j2 gfa1/io162pdb3 j3 v ccplf j4 io160ndb3 j5 gfb2/io160pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io73ppb1 j13 gca1/io71ppb1 j14 gcc2/io74ppb1 j15 io80ppb1 j16 gca2/io72pdb1 256-pin fbga pin number a3p600 function k1 gfc2/io159pdb3 k2 io161npb3 k3 io156ppb3 k4 io129rsb2 k5 v cci b3 k6 v cc k7 gnd k8 gnd k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io73npb1 k14 io80npb1 k15 io74npb1 k16 io72ndb1 l1 io159ndb3 l2 io156npb3 l3 io151ppb3 l4 io158psb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io87npb1 l14 io85ndb1 l15 io85pdb1 l16 io84pdb1 m1 io150pdb3 m2 io151npb3 m3 io147npb3 m4 gec0/io146npb3 256-pin fbga pin number a3p600 function m5 vmv3 m6 v cci b2 m7 v cci b2 m8 io117rsb2 m9 io110rsb2 m10 v cci b2 m11 v cci b2 m12 vmv2 m13 io94rsb2 m14 gdb1/io87ppb1 m15 gdc1/io86pdb1 m16 io84ndb1 n1 io150ndb3 n2 io147ppb3 n3 gec1/io146ppb3 n4 io140rsb2 n5 gndq n6 gea2/io143rsb2 n7 io126rsb2 n8 io120rsb2 n9 io108rsb2 n10 io103rsb2 n11 io99rsb2 n12 gndq n13 io92rsb2 n14 v jtag n15 gdc0/io86ndb1 n16 gda1/io88pdb1 p1 geb1/io145pdb3 p2 geb0/io145ndb3 p3 vmv2 p4 io138rsb2 p5 io136rsb2 p6 io131rsb2 p7 io124rsb2 p8 io119rsb2 256-pin fbga pin number a3p600 function proasic3 packaging v1.3 3-55 p9 io107rsb2 p10 io104rsb2 p11 io97rsb2 p12 vmv1 p13 tck p14 v pump p15 trst p16 gda0/io88ndb1 r1 gea1/io144pdb3 r2 gea0/io144ndb3 r3 io139rsb2 r4 gec2/io141rsb2 r5 io132rsb2 r6 io127rsb2 r7 io121rsb2 r8 io114rsb2 r9 io109rsb2 r10 io105rsb2 r11 io98rsb2 r12 io96rsb2 r13 gdb2/io90rsb2 r14 tdi r15 gndq r16 tdo t1 gnd t2 io137rsb2 t3 geb2/io142rsb2 t4 io134rsb2 t5 io125rsb2 t6 io123rsb2 t7 io118rsb2 t8 io115rsb2 t9 io111rsb2 t10 io106rsb2 t11 io102rsb2 t12 gdc2/io91rsb2 256-pin fbga pin number a3p600 function t13 io93rsb2 t14 gda2/io89rsb2 t15 tms t16 gnd 256-pin fbga pin number a3p600 function package pin assignments 3-56 v1.3 256-pin fbga pin number a3p1000 function a1 gnd a2 gaa0/io00rsb0 a3 gaa1/io01rsb0 a4 gab0/io02rsb0 a5 io16rsb0 a6 io22rsb0 a7 io28rsb0 a8 io35rsb0 a9 io45rsb0 a10 io50rsb0 a11 io55rsb0 a12 io61rsb0 a13 gbb1/io75rsb0 a14 gba0/io76rsb0 a15 gba1/io77rsb0 a16 gnd b1 gab2/io224pdb3 b2 gaa2/io225pdb3 b3 gndq b4 gab1/io03rsb0 b5 io17rsb0 b6 io21rsb0 b7 io27rsb0 b8 io34rsb0 b9 io44rsb0 b10 io51rsb0 b11 io57rsb0 b12 gbc1/io73rsb0 b13 gbb0/io74rsb0 b14 io71rsb0 b15 gba2/io78pdb1 b16 io81pdb1 c1 io224ndb3 c2 io225ndb3 c3 vmv3 c4 io11rsb0 c5 gac0/io04rsb0 c6 gac1/io05rsb0 c7 io25rsb0 c8 io36rsb0 c9 io42rsb0 c10 io49rsb0 c11 io56rsb0 c12 gbc0/io72rsb0 c13 io62rsb0 c14 vmv0 c15 io78ndb1 c16 io81ndb1 d1 io222ndb3 d2 io222pdb3 d3 gac2/io223pdb3 d4 io223ndb3 d5 gndq d6 io23rsb0 d7 io29rsb0 d8 io33rsb0 d9 io46rsb0 d10 io52rsb0 d11 io60rsb0 d12 gndq d13 io80ndb1 d14 gbb2/io79pdb1 d15 io79ndb1 d16 io82nsb1 e1 io217pdb3 e2 io218pdb3 e3 io221ndb3 e4 io221pdb3 e5 vmv0 e6 v cci b0 e7 v cci b0 e8 io38rsb0 e9 io47rsb0 e10 v cci b0 e11 v cci b0 e12 vmv1 256-pin fbga pin number a3p1000 function e13 gbc2/io80pdb1 e14 io83ppb1 e15 io86ppb1 e16 io87pdb1 f1 io217ndb3 f2 io218ndb3 f3 io216pdb3 f4 io216ndb3 f5 v cci b3 f6 gnd f7 v cc f8 v cc f9 v cc f10 v cc f11 gnd f12 v cci b1 f13 io83npb1 f14 io86npb1 f15 io90ppb1 f16 io87ndb1 g1 io210psb3 g2 io213ndb3 g3 io213pdb3 g4 gfc1/io209ppb3 g5 v cci b3 g6 v cc g7 gnd g8 gnd g9 gnd g10 gnd g11 v cc g12 v cci b1 g13 gcc1/io91ppb1 g14 io90npb1 g15 io88pdb1 g16 io88ndb1 h1 gfb0/io208npb3 h2 gfa0/io207ndb3 256-pin fbga pin number a3p1000 function proasic3 packaging v1.3 3-57 h3 gfb1/io208ppb3 h4 v complf h5 gfc0/io209npb3 h6 v cc h7 gnd h8 gnd h9 gnd h10 gnd h11 v cc h12 gcc0/io91npb1 h13 gcb1/io92ppb1 h14 gca0/io93npb1 h15 io96npb1 h16 gcb0/io92npb1 j1 gfa2/io206psb3 j2 gfa1/io207pdb3 j3 v ccplf j4 io205ndb3 j5 gfb2/io205pdb3 j6 v cc j7 gnd j8 gnd j9 gnd j10 gnd j11 v cc j12 gcb2/io95ppb1 j13 gca1/io93ppb1 j14 gcc2/io96ppb1 j15 io100ppb1 j16 gca2/io94psb1 k1 gfc2/io204pdb3 k2 io204ndb3 k3 io203ndb3 k4 io203pdb3 k5 v cci b3 k6 v cc k7 gnd k8 gnd 256-pin fbga pin number a3p1000 function k9 gnd k10 gnd k11 v cc k12 v cci b1 k13 io95npb1 k14 io100npb1 k15 io102ndb1 k16 io102pdb1 l1 io202ndb3 l2 io202pdb3 l3 io196ppb3 l4 io193ppb3 l5 v cci b3 l6 gnd l7 v cc l8 v cc l9 v cc l10 v cc l11 gnd l12 v cci b1 l13 gdb0/io112npb1 l14 io106ndb1 l15 io106pdb1 l16 io107pdb1 m1 io197nsb3 m2 io196npb3 m3 io193npb3 m4 gec0/io190npb3 m5 vmv3 m6 v cci b2 m7 v cci b2 m8 io147rsb2 m9 io136rsb2 m10 v cci b2 m11 v cci b2 m12 vmv2 m13 io110ndb1 m14 gdb1/io112ppb1 256-pin fbga pin number a3p1000 function m15 gdc1/io111pdb1 m16 io107ndb1 n1 io194psb3 n2 io192ppb3 n3 gec1/io190ppb3 n4 io192npb3 n5 gndq n6 gea2/io187rsb2 n7 io161rsb2 n8 io155rsb2 n9 io141rsb2 n10 io129rsb2 n11 io124rsb2 n12 gndq n13 io110pdb1 n14 v jtag n15 gdc0/io111ndb1 n16 gda1/io113pdb1 p1 geb1/io189pdb3 p2 geb0/io189ndb3 p3 vmv2 p4 io179rsb2 p5 io171rsb2 p6 io165rsb2 p7 io159rsb2 p8 io151rsb2 p9 io137rsb2 p10 io134rsb2 p11 io128rsb2 p12 vmv1 p13 tck p14 v pump p15 trst p16 gda0/io113ndb1 r1 gea1/io188pdb3 r2 gea0/io188ndb3 r3 io184rsb2 r4 gec2/io185rsb2 256-pin fbga pin number a3p1000 function package pin assignments 3-58 v1.3 r5 io168rsb2 r6 io163rsb2 r7 io157rsb2 r8 io149rsb2 r9 io143rsb2 r10 io138rsb2 r11 io131rsb2 r12 io125rsb2 r13 gdb2/io115rsb2 r14 tdi r15 gndq r16 tdo t1 gnd t2 io183rsb2 t3 geb2/io186rsb2 t4 io172rsb2 t5 io170rsb2 t6 io164rsb2 t7 io158rsb2 t8 io153rsb2 t9 io142rsb2 t10 io135rsb2 t11 io130rsb2 t12 gdc2/io116rsb2 t13 io120rsb2 t14 gda2/io114rsb2 t15 tms t16 gnd 256-pin fbga pin number a3p1000 function proasic3 packaging v1.3 3-59 484-pin fbga note for package manufacturing and environmental information, visit the resource center at http://www.actel.com/products/ solutions/pac kage/docs.aspx . note: this is the bottom view of the package. a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a1 ball pad corner package pin assignments 3-60 v1.3 484-pin fbga pin number a3p400 function a1 gnd a2 gnd a3 v cci b0 a4 nc a5 nc a6 io15rsb0 a7 io18rsb0 a8 nc a9 nc a10 io23rsb0 a11 io29rsb0 a12 io35rsb0 a13 io36rsb0 a14 nc a15 nc a16 io50rsb0 a17 io51rsb0 a18 nc a19 nc a20 v cci b0 a21 gnd a22 gnd b1 gnd b2 v cci b3 b3 nc b4 nc b5 nc b6 nc b7 nc b8 nc b9 nc b10 nc b11 nc b12 nc b13 nc b14 nc b15 nc b16 nc b17 nc b18 nc b19 nc b20 nc b21 v cci b1 b22 gnd c1 v cci b3 c2 nc c3 nc c4 nc c5 gnd c6 nc c7 nc c8 v cc c9 v cc c10 nc c11 nc c12 nc c13 nc c14 v cc c15 v cc c16 nc c17 nc c18 gnd c19 nc c20 nc c21 nc c22 v cci b1 d1 nc d2 nc d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 484-pin fbga pin number a3p400 function d7 gab0/io02rsb0 d8 io16rsb0 d9 io17rsb0 d10 io22rsb0 d11 io28rsb0 d12 io34rsb0 d13 io37rsb0 d14 io41rsb0 d15 io43rsb0 d16 gbb1/io57rsb0 d17 gba0/io58rsb0 d18 gba1/io59rsb0 d19 gnd d20 nc d21 nc d22 nc e1 nc e2 nc e3 gnd e4 gab2/io154udb3 e5 gaa2/io155udb3 e6 io12rsb0 e7 gab1/io03rsb0 e8 io13rsb0 e9 io14rsb0 e10 io21rsb0 e11 io27rsb0 e12 io32rsb0 e13 io38rsb0 e14 io42rsb0 e15 gbc1/io55rsb0 e16 gbb0/io56rsb0 e17 io44rsb0 e18 gba2/io60pdb1 e19 io60ndb1 e20 gnd 484-pin fbga pin number a3p400 function proasic3 packaging v1.3 3-61 e21 nc e22 nc f1 nc f2 nc f3 nc f4 io154vdb3 f5 io155vdb3 f6 io11rsb0 f7 io07rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io20rsb0 f11 io24rsb0 f12 io33rsb0 f13 io39rsb0 f14 io45rsb0 f15 gbc0/io54rsb0 f16 io48rsb0 f17 vmv0 f18 io61npb1 f19 io63pdb1 f20 nc f21 nc f22 nc g1 nc g2 nc g3 nc g4 io151vdb3 g5 io151udb3 g6 gac2/io153udb3 g7 io06rsb0 g8 gndq g9 io10rsb0 g10 io19rsb0 g11 io26rsb0 g12 io30rsb0 484-pin fbga pin number a3p400 function g13 io40rsb0 g14 io46rsb0 g15 gndq g16 io47rsb0 g17 gbb2/io61ppb1 g18 io53rsb0 g19 io63ndb1 g20 nc g21 nc g22 nc h1 nc h2 nc h3 v cc h4 io150pdb3 h5 io08rsb0 h6 io153vdb3 h7 io152vdb3 h8 vmv0 h9 v cci b0 h10 v cci b0 h11 io25rsb0 h12 io31rsb0 h13 v cci b0 h14 v cci b0 h15 vmv1 h16 gbc2/io62pdb1 h17 io65rsb1 h18 io52rsb0 h19 io66pdb1 h20 v cc h21 nc h22 nc j1 nc j2 nc j3 nc j4 io150ndb3 484-pin fbga pin number a3p400 function j5 io149npb3 j6 io09rsb0 j7 io152udb3 j8 v cci b3 j9 gnd j10 v cc j11 v cc j12 v cc j13 v cc j14 gnd j15 v cci b1 j16 io62ndb1 j17 io49rsb0 j18 io64ppb1 j19 io66ndb1 j20 nc j21 nc j22 nc k1 nc k2 nc k3 nc k4 io148ndb3 k5 io148pdb3 k6 io149ppb3 k7 gfc1/io147ppb3 k8 v cci b3 k9 v cc k10 gnd k11 gnd k12 gnd k13 gnd k14 v cc k15 v cci b1 k16 gcc1/io67ppb1 k17 io64npb1 k18 io73pdb1 484-pin fbga pin number a3p400 function package pin assignments 3-62 v1.3 k19 io73ndb1 k20 nc k21 nc k22 nc l1 nc l2 nc l3 nc l4 gfb0/io146npb3 l5 gfa0/io145ndb3 l6 gfb1/io146ppb3 l7 v complf l8 gfc0/io147npb3 l9 v cc l10 gnd l11 gnd l12 gnd l13 gnd l14 v cc l15 gcc0/io67npb1 l16 gcb1/io68ppb1 l17 gca0/io69npb1 l18 nc l19 gcb0/io68npb1 l20 nc l21 nc l22 nc m1 nc m2 nc m3 nc m4 gfa2/io144ppb3 m5 gfa1/io145pdb3 m6 v ccplf m7 io143ndb3 m8 gfb2/io143pdb3 m9 v cc m10 gnd 484-pin fbga pin number a3p400 function m11 gnd m12 gnd m13 gnd m14 v cc m15 gcb2/io71ppb1 m16 gca1/io69ppb1 m17 gcc2/io72ppb1 m18 nc m19 gca2/io70pdb1 m20 nc m21 nc m22 nc n1 nc n2 nc n3 nc n4 gfc2/io142pdb3 n5 io144npb3 n6 io141ppb3 n7 io120rsb2 n8 v cci b3 n9 v cc n10 gnd n11 gnd n12 gnd n13 gnd n14 v cc n15 v cci b1 n16 io71npb1 n17 io74rsb1 n18 io72npb1 n19 io70ndb1 n20 nc n21 nc n22 nc p1 nc p2 nc 484-pin fbga pin number a3p400 function p3 nc p4 io142ndb3 p5 io141npb3 p6 io125rsb2 p7 io139rsb3 p8 v cci b3 p9 gnd p10 v cc p11 v cc p12 v cc p13 v cc p14 gnd p15 v cci b1 p16 gdb0/io78vpb1 p17 io76vdb1 p18 io76udb1 p19 io75pdb1 p20 nc p21 nc p22 nc r1 nc r2 nc r3 v cc r4 io140pdb3 r5 io130rsb2 r6 io138npb3 r7 gec0/io137npb3 r8 vmv3 r9 v cci b2 r10 v cci b2 r11 io108rsb2 r12 io101rsb2 r13 v cci b2 r14 v cci b2 r15 vmv2 r16 io83rsb2 484-pin fbga pin number a3p400 function proasic3 packaging v1.3 3-63 r17 gdb1/io78upb1 r18 gdc1/io77udb1 r19 io75ndb1 r20 v cc r21 nc r22 nc t1 nc t2 nc t3 nc t4 io140ndb3 t5 io138ppb3 t6 gec1/io137ppb3 t7 io131rsb2 t8 gndq t9 gea2/io134rsb2 t10 io117rsb2 t11 io111rsb2 t12 io99rsb2 t13 io94rsb2 t14 io87rsb2 t15 gndq t16 io93rsb2 t17 v jtag t18 gdc0/io77vdb1 t19 gda1/io79udb1 t20 nc t21 nc t22 nc u1 nc u2 nc u3 nc u4 geb1/io136pdb3 u5 geb0/io136ndb3 u6 vmv2 u7 io129rsb2 u8 io128rsb2 484-pin fbga pin number a3p400 function u9 io122rsb2 u10 io115rsb2 u11 io110rsb2 u12 io98rsb2 u13 io95rsb2 u14 io88rsb2 u15 io84rsb2 u16 tck u17 v pump u18 trst u19 gda0/io79vdb1 u20 nc u21 nc u22 nc v1 nc v2 nc v3 gnd v4 gea1/io135pdb3 v5 gea0/io135ndb3 v6 io127rsb2 v7 gec2/io132rsb2 v8 io123rsb2 v9 io118rsb2 v10 io112rsb2 v11 io106rsb2 v12 io100rsb2 v13 io96rsb2 v14 io89rsb2 v15 io85rsb2 v16 gdb2/io81rsb2 v17 tdi v18 nc v19 tdo v20 gnd v21 nc v22 nc 484-pin fbga pin number a3p400 function w1 nc w2 nc w3 nc w4 gnd w5 io126rsb2 w6 geb2/io133rsb2 w7 io124rsb2 w8 io116rsb2 w9 io113rsb2 w10 io107rsb2 w11 io105rsb2 w12 io102rsb2 w13 io97rsb2 w14 io92rsb2 w15 gdc2/io82rsb2 w16 io86rsb2 w17 gda2/io80rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 v cci b3 y2 nc y3 nc y4 nc y5 gnd y6 nc y7 nc y8 v cc y9 v cc y10 nc y11 nc y12 nc y13 nc y14 v cc 484-pin fbga pin number a3p400 function package pin assignments 3-64 v1.3 y15 v cc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 v cci b1 aa1 gnd aa2 v cci b3 aa3 nc aa4 nc aa5 nc aa6 nc aa7 nc aa8 nc aa9 nc aa10 nc aa11 nc aa12 nc aa13 nc aa14 nc aa15 nc aa16 nc aa17 nc aa18 nc aa19 nc aa20 nc aa21 v cci b1 aa22 gnd ab1 gnd ab2 gnd ab3 v cci b2 ab4 nc ab5 nc ab6 io121rsb2 484-pin fbga pin number a3p400 function ab7 io119rsb2 ab8 io114rsb2 ab9 io109rsb2 ab10 nc ab11 nc ab12 io104rsb2 ab13 io103rsb2 ab14 nc ab15 nc ab16 io91rsb2 ab17 io90rsb2 ab18 nc ab19 nc ab20 v cci b2 ab21 gnd ab22 gnd 484-pin fbga pin number a3p400 function proasic3 packaging v1.3 3-65 484-pin fbga pin number a3p600 function a1 gnd a2 gnd a3 vccib0 a4 nc a5 nc a6 io09rsb0 a7 io15rsb0 a8 nc a9 nc a10 io22rsb0 a11 io23rsb0 a12 io29rsb0 a13 io35rsb0 a14 nc a15 nc a16 io46rsb0 a17 io48rsb0 a18 nc a19 nc a20 v cci b0 a21 gnd a22 gnd b1 gnd b2 v cci b3 b3 nc b4 nc b5 nc b6 io08rsb0 b7 io12rsb0 b8 nc b9 nc b10 io17rsb0 b11 nc b12 nc b13 io36rsb0 b14 nc b15 nc b16 io47rsb0 b17 io49rsb0 b18 nc b19 nc b20 nc b21 v cci b1 b22 gnd c1 v cci b3 c2 nc c3 nc c4 nc c5 gnd c6 nc c7 nc c8 v cc c9 v cc c10 nc c11 nc c12 nc c13 nc c14 v cc c15 v cc c16 nc c17 nc c18 gnd c19 nc c20 nc c21 nc c22 v cci b1 d1 nc d2 nc d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 484-pin fbga pin number a3p600 function d7 gab0/io02rsb0 d8 io11rsb0 d9 io16rsb0 d10 io18rsb0 d11 io28rsb0 d12 io34rsb0 d13 io37rsb0 d14 io41rsb0 d15 io43rsb0 d16 gbb1/io57rsb0 d17 gba0/io58rsb0 d18 gba1/io59rsb0 d19 gnd d20 nc d21 nc d22 nc e1 nc e2 nc e3 gnd e4 gab2/io173pdb3 e5 gaa2/io174pdb3 e6 gndq e7 gab1/io03rsb0 e8 io13rsb0 e9 io14rsb0 e10 io21rsb0 e11 io27rsb0 e12 io32rsb0 e13 io38rsb0 e14 io42rsb0 e15 gbc1/io55rsb0 e16 gbb0/io56rsb0 e17 io52rsb0 e18 gba2/io60pdb1 e19 io60ndb1 e20 gnd 484-pin fbga pin number a3p600 function package pin assignments 3-66 v1.3 e21 nc e22 nc f1 nc f2 nc f3 nc f4 io173ndb3 f5 io174ndb3 f6 vmv3 f7 io07rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io20rsb0 f11 io24rsb0 f12 io33rsb0 f13 io39rsb0 f14 io44rsb0 f15 gbc0/io54rsb0 f16 io51rsb0 f17 vmv0 f18 io61npb1 f19 io63pdb1 f20 nc f21 nc f22 nc g1 io170ndb3 g2 io170pdb3 g3 nc g4 io171ndb3 g5 io171pdb3 g6 gac2/io172pdb3 g7 io06rsb0 g8 gndq g9 io10rsb0 g10 io19rsb0 g11 io26rsb0 g12 io30rsb0 484-pin fbga pin number a3p600 function g13 io40rsb0 g14 io45rsb0 g15 gndq g16 io50rsb0 g17 gbb2/io61ppb1 g18 io53rsb0 g19 io63ndb1 g20 nc g21 nc g22 nc h1 nc h2 nc h3 v cc h4 io166pdb3 h5 io167npb3 h6 io172ndb3 h7 io169ndb3 h8 vmv0 h9 v cci b0 h10 v cci b0 h11 io25rsb0 h12 io31rsb0 h13 v cci b0 h14 v cci b0 h15 vmv1 h16 gbc2/io62pdb1 h17 io67ppb1 h18 io64ppb1 h19 io66pdb1 h20 v cc h21 nc h22 nc j1 nc j2 nc j3 nc j4 io166ndb3 484-pin fbga pin number a3p600 function j5 io168npb3 j6 io167ppb3 j7 io169pdb3 j8 v cci b3 j9 gnd j10 v cc j11 v cc j12 v cc j13 v cc j14 gnd j15 v cci b1 j16 io62ndb1 j17 io64npb1 j18 io65ppb1 j19 io66ndb1 j20 nc j21 io68pdb1 j22 io68ndb1 k1 io157pdb3 k2 io157ndb3 k3 nc k4 io165ndb3 k5 io165pdb3 k6 io168ppb3 k7 gfc1/io164ppb3 k8 v cci b3 k9 v cc k10 gnd k11 gnd k12 gnd k13 gnd k14 v cc k15 v cci b1 k16 gcc1/io69ppb1 k17 io65npb1 k18 io75pdb1 484-pin fbga pin number a3p600 function proasic3 packaging v1.3 3-67 k19 io75ndb1 k20 nc k21 io76ndb1 k22 io76pdb1 l1 nc l2 io155pdb3 l3 nc l4 gfb0/io163npb3 l5 gfa0/io162ndb3 l6 gfb1/io163ppb3 l7 v complf l8 gfc0/io164npb3 l9 v cc l10 gnd l11 gnd l12 gnd l13 gnd l14 v cc l15 gcc0/io69npb1 l16 gcb1/io70ppb1 l17 gca0/io71npb1 l18 io67npb1 l19 gcb0/io70npb1 l20 io77pdb1 l21 io77ndb1 l22 io78npb1 m1 nc m2 io155ndb3 m3 io158npb3 m4 gfa2/io161ppb3 m5 gfa1/io162pdb3 m6 v ccplf m7 io160ndb3 m8 gfb2/io160pdb3 m9 v cc m10 gnd 484-pin fbga pin number a3p600 function m11 gnd m12 gnd m13 gnd m14 v cc m15 gcb2/io73ppb1 m16 gca1/io71ppb1 m17 gcc2/io74ppb1 m18 io80ppb1 m19 gca2/io72pdb1 m20 io79ppb1 m21 io78ppb1 m22 nc n1 io154ndb3 n2 io154pdb3 n3 nc n4 gfc2/io159pdb3 n5 io161npb3 n6 io156ppb3 n7 io129rsb2 n8 v cci b3 n9 v cc n10 gnd n11 gnd n12 gnd n13 gnd n14 v cc n15 v cci b1 n16 io73npb1 n17 io80npb1 n18 io74npb1 n19 io72ndb1 n20 nc n21 io79npb1 n22 nc p1 nc p2 io153pdb3 484-pin fbga pin number a3p600 function p3 io153ndb3 p4 io159ndb3 p5 io156npb3 p6 io151ppb3 p7 io158ppb3 p8 v cci b3 p9 gnd p10 v cc p11 v cc p12 v cc p13 v cc p14 gnd p15 v cci b1 p16 gdb0/io87npb1 p17 io85ndb1 p18 io85pdb1 p19 io84pdb1 p20 nc p21 io81pdb1 p22 nc r1 nc r2 nc r3 v cc r4 io150pdb3 r5 io151npb3 r6 io147npb3 r7 gec0/io146npb3 r8 vmv3 r9 v cci b2 r10 v cci b2 r11 io117rsb2 r12 io110rsb2 r13 v cci b2 r14 v cci b2 r15 vmv2 r16 io94rsb2 484-pin fbga pin number a3p600 function package pin assignments 3-68 v1.3 r17 gdb1/io87ppb1 r18 gdc1/io86pdb1 r19 io84ndb1 r20 v cc r21 io81ndb1 r22 io82pdb1 t1 io152pdb3 t2 io152ndb3 t3 nc t4 io150ndb3 t5 io147ppb3 t6 gec1/io146ppb3 t7 io140rsb2 t8 gndq t9 gea2/io143rsb2 t10 io126rsb2 t11 io120rsb2 t12 io108rsb2 t13 io103rsb2 t14 io99rsb2 t15 gndq t16 io92rsb2 t17 v jtag t18 gdc0/io86ndb1 t19 gda1/io88pdb1 t20 nc t21 io83pdb1 t22 io82ndb1 u1 io149pdb3 u2 io149ndb3 u3 nc u4 geb1/io145pdb3 u5 geb0/io145ndb3 u6 vmv2 u7 io138rsb2 u8 io136rsb2 484-pin fbga pin number a3p600 function u9 io131rsb2 u10 io124rsb2 u11 io119rsb2 u12 io107rsb2 u13 io104rsb2 u14 io97rsb2 u15 vmv1 u16 tck u17 v pump u18 trst u19 gda0/io88ndb1 u20 nc u21 io83ndb1 u22 nc v1 nc v2 nc v3 gnd v4 gea1/io144pdb3 v5 gea0/io144ndb3 v6 io139rsb2 v7 gec2/io141rsb2 v8 io132rsb2 v9 io127rsb2 v10 io121rsb2 v11 io114rsb2 v12 io109rsb2 v13 io105rsb2 v14 io98rsb2 v15 io96rsb2 v16 gdb2/io90rsb2 v17 tdi v18 gndq v19 tdo v20 gnd v21 nc v22 nc 484-pin fbga pin number a3p600 function w1 nc w2 io148pdb3 w3 nc w4 gnd w5 io137rsb2 w6 geb2/io142rsb2 w7 io134rsb2 w8 io125rsb2 w9 io123rsb2 w10 io118rsb2 w11 io115rsb2 w12 io111rsb2 w13 io106rsb2 w14 io102rsb2 w15 gdc2/io91rsb2 w16 io93rsb2 w17 gda2/io89rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 v cci b3 y2 io148ndb3 y3 nc y4 nc y5 gnd y6 nc y7 nc y8 v cc y9 v cc y10 nc y11 nc y12 nc y13 nc y14 v cc 484-pin fbga pin number a3p600 function proasic3 packaging v1.3 3-69 y15 v cc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 v cci b1 aa1 gnd aa2 v cci b3 aa3 nc aa4 nc aa5 nc aa6 io135rsb2 aa7 io133rsb2 aa8 nc aa9 nc aa10 nc aa11 nc aa12 nc aa13 nc aa14 nc aa15 nc aa16 io101rsb2 aa17 nc aa18 nc aa19 nc aa20 nc aa21 v cci b1 aa22 gnd ab1 gnd ab2 gnd ab3 v cci b2 ab4 nc ab5 nc ab6 io130rsb2 484-pin fbga pin number a3p600 function ab7 io128rsb2 ab8 io122rsb2 ab9 io116rsb2 ab10 nc ab11 nc ab12 io113rsb2 ab13 io112rsb2 ab14 nc ab15 nc ab16 io100rsb2 ab17 io95rsb2 ab18 nc ab19 nc ab20 v cci b2 ab21 gnd ab22 gnd 484-pin fbga pin number a3p600 function package pin assignments 3-70 v1.3 484-pin fbga pin number a3p1000 function a1 gnd a2 gnd a3 v cci b0 a4 io07rsb0 a5 io09rsb0 a6 io13rsb0 a7 io18rsb0 a8 io20rsb0 a9 io26rsb0 a10 io32rsb0 a11 io40rsb0 a12 io41rsb0 a13 io53rsb0 a14 io59rsb0 a15 io64rsb0 a16 io65rsb0 a17 io67rsb0 a18 io69rsb0 a19 nc a20 v cci b0 a21 gnd a22 gnd b1 gnd b2 v cci b3 b3 nc b4 io06rsb0 b5 io08rsb0 b6 io12rsb0 b7 io15rsb0 b8 io19rsb0 b9 io24rsb0 b10 io31rsb0 b11 io39rsb0 b12 io48rsb0 b13 io54rsb0 b14 io58rsb0 b15 io63rsb0 b16 io66rsb0 b17 io68rsb0 b18 io70rsb0 b19 nc b20 nc b21 v cci b1 b22 gnd c1 v cci b3 c2 io220pdb3 c3 nc c4 nc c5 gnd c6 io10rsb0 c7 io14rsb0 c8 v cc c9 v cc c10 io30rsb0 c11 io37rsb0 c12 io43rsb0 c13 nc c14 v cc c15 v cc c16 nc c17 nc c18 gnd c19 nc c20 nc c21 nc c22 v cci b1 d1 io219pdb3 d2 io220ndb3 d3 nc d4 gnd d5 gaa0/io00rsb0 d6 gaa1/io01rsb0 484-pin fbga pin number a3p1000 function d7 gab0/io02rsb0 d8 io16rsb0 d9 io22rsb0 d10 io28rsb0 d11 io35rsb0 d12 io45rsb0 d13 io50rsb0 d14 io55rsb0 d15 io61rsb0 d16 gbb1/io75rsb0 d17 gba0/io76rsb0 d18 gba1/io77rsb0 d19 gnd d20 nc d21 nc d22 nc e1 io219ndb3 e2 nc e3 gnd e4 gab2/io224pdb3 e5 gaa2/io225pdb3 e6 gndq e7 gab1/io03rsb0 e8 io17rsb0 e9 io21rsb0 e10 io27rsb0 e11 io34rsb0 e12 io44rsb0 e13 io51rsb0 e14 io57rsb0 e15 gbc1/io73rsb0 e16 gbb0/io74rsb0 e17 io71rsb0 e18 gba2/io78pdb1 e19 io81pdb1 e20 gnd 484-pin fbga pin number a3p1000 function proasic3 packaging v1.3 3-71 e21 nc e22 io84pdb1 f1 nc f2 io215pdb3 f3 io215ndb3 f4 io224ndb3 f5 io225ndb3 f6 vmv3 f7 io11rsb0 f8 gac0/io04rsb0 f9 gac1/io05rsb0 f10 io25rsb0 f11 io36rsb0 f12 io42rsb0 f13 io49rsb0 f14 io56rsb0 f15 gbc0/io72rsb0 f16 io62rsb0 f17 vmv0 f18 io78ndb1 f19 io81ndb1 f20 io82ppb1 f21 nc f22 io84ndb1 g1 io214ndb3 g2 io214pdb3 g3 nc g4 io222ndb3 g5 io222pdb3 g6 gac2/io223pdb3 g7 io223ndb3 g8 gndq g9 io23rsb0 g10 io29rsb0 g11 io33rsb0 g12 io46rsb0 484-pin fbga pin number a3p1000 function g13 io52rsb0 g14 io60rsb0 g15 gndq g16 io80ndb1 g17 gbb2/io79pdb1 g18 io79ndb1 g19 io82npb1 g20 io85pdb1 g21 io85ndb1 g22 nc h1 nc h2 nc h3 v cc h4 io217pdb3 h5 io218pdb3 h6 io221ndb3 h7 io221pdb3 h8 vmv0 h9 v cci b0 h10 v cci b0 h11 io38rsb0 h12 io47rsb0 h13 v cci b0 h14 v cci b0 h15 vmv1 h16 gbc2/io80pdb1 h17 io83ppb1 h18 io86ppb1 h19 io87pdb1 h20 v cc h21 nc h22 nc j1 io212ndb3 j2 io212pdb3 j3 nc j4 io217ndb3 484-pin fbga pin number a3p1000 function j5 io218ndb3 j6 io216pdb3 j7 io216ndb3 j8 v cci b3 j9 gnd j10 v cc j11 v cc j12 v cc j13 v cc j14 gnd j15 v cci b1 j16 io83npb1 j17 io86npb1 j18 io90ppb1 j19 io87ndb1 j20 nc j21 io89pdb1 j22 io89ndb1 k1 io211pdb3 k2 io211ndb3 k3 nc k4 io210ppb3 k5 io213ndb3 k6 io213pdb3 k7 gfc1/io209ppb3 k8 v cci b3 k9 v cc k10 gnd k11 gnd k12 gnd k13 gnd k14 v cc k15 v cci b1 k16 gcc1/io91ppb1 k17 io90npb1 k18 io88pdb1 484-pin fbga pin number a3p1000 function package pin assignments 3-72 v1.3 k19 io88ndb1 k20 io94npb1 k21 io98ndb1 k22 io98pdb1 l1 nc l2 io200pdb3 l3 io210npb3 l4 gfb0/io208npb3 l5 gfa0/io207ndb3 l6 gfb1/io208ppb3 l7 v complf l8 gfc0/io209npb3 l9 v cc l10 gnd l11 gnd l12 gnd l13 gnd l14 v cc l15 gcc0/io91npb1 l16 gcb1/io92ppb1 l17 gca0/io93npb1 l18 io96npb1 l19 gcb0/io92npb1 l20 io97pdb1 l21 io97ndb1 l22 io99npb1 m1 nc m2 io200ndb3 m3 io206ndb3 m4 gfa2/io206pdb3 m5 gfa1/io207pdb3 m6 v ccplf m7 io205ndb3 m8 gfb2/io205pdb3 m9 v cc m10 gnd 484-pin fbga pin number a3p1000 function m11 gnd m12 gnd m13 gnd m14 v cc m15 gcb2/io95ppb1 m16 gca1/io93ppb1 m17 gcc2/io96ppb1 m18 io100ppb1 m19 gca2/io94ppb1 m20 io101ppb1 m21 io99ppb1 m22 nc n1 io201ndb3 n2 io201pdb3 n3 nc n4 gfc2/io204pdb3 n5 io204ndb3 n6 io203ndb3 n7 io203pdb3 n8 v cci b3 n9 v cc n10 gnd n11 gnd n12 gnd n13 gnd n14 v cc n15 v cci b1 n16 io95npb1 n17 io100npb1 n18 io102ndb1 n19 io102pdb1 n20 nc n21 io101npb1 n22 io103pdb1 p1 nc p2 io199pdb3 484-pin fbga pin number a3p1000 function p3 io199ndb3 p4 io202ndb3 p5 io202pdb3 p6 io196ppb3 p7 io193ppb3 p8 v cci b3 p9 gnd p10 v cc p11 v cc p12 v cc p13 v cc p14 gnd p15 v cci b1 p16 gdb0/io112npb1 p17 io106ndb1 p18 io106pdb1 p19 io107pdb1 p20 nc p21 io104pdb1 p22 io103ndb1 r1 nc r2 io197ppb3 r3 v cc r4 io197npb3 r5 io196npb3 r6 io193npb3 r7 gec0/io190npb3 r8 vmv3 r9 v cci b2 r10 v cci b2 r11 io147rsb2 r12 io136rsb2 r13 v cci b2 r14 v cci b2 r15 vmv2 r16 io110ndb1 484-pin fbga pin number a3p1000 function proasic3 packaging v1.3 3-73 r17 gdb1/io112ppb1 r18 gdc1/io111pdb1 r19 io107ndb1 r20 v cc r21 io104ndb1 r22 io105pdb1 t1 io198pdb3 t2 io198ndb3 t3 nc t4 io194ppb3 t5 io192ppb3 t6 gec1/io190ppb3 t7 io192npb3 t8 gndq t9 gea2/io187rsb2 t10 io161rsb2 t11 io155rsb2 t12 io141rsb2 t13 io129rsb2 t14 io124rsb2 t15 gndq t16 io110pdb1 t17 v jtag t18 gdc0/io111ndb1 t19 gda1/io113pdb1 t20 nc t21 io108pdb1 t22 io105ndb1 u1 io195pdb3 u2 io195ndb3 u3 io194npb3 u4 geb1/io189pdb3 u5 geb0/io189ndb3 u6 vmv2 u7 io179rsb2 u8 io171rsb2 484-pin fbga pin number a3p1000 function u9 io165rsb2 u10 io159rsb2 u11 io151rsb2 u12 io137rsb2 u13 io134rsb2 u14 io128rsb2 u15 vmv1 u16 tck u17 v pump u18 trst u19 gda0/io113ndb1 u20 nc u21 io108ndb1 u22 io109pdb1 v1 nc v2 nc v3 gnd v4 gea1/io188pdb3 v5 gea0/io188ndb3 v6 io184rsb2 v7 gec2/io185rsb2 v8 io168rsb2 v9 io163rsb2 v10 io157rsb2 v11 io149rsb2 v12 io143rsb2 v13 io138rsb2 v14 io131rsb2 v15 io125rsb2 v16 gdb2/io115rsb2 v17 tdi v18 gndq v19 tdo v20 gnd v21 nc v22 io109ndb1 484-pin fbga pin number a3p1000 function w1 nc w2 io191pdb3 w3 nc w4 gnd w5 io183rsb2 w6 geb2/io186rsb2 w7 io172rsb2 w8 io170rsb2 w9 io164rsb2 w10 io158rsb2 w11 io153rsb2 w12 io142rsb2 w13 io135rsb2 w14 io130rsb2 w15 gdc2/io116rsb2 w16 io120rsb2 w17 gda2/io114rsb2 w18 tms w19 gnd w20 nc w21 nc w22 nc y1 v cci b3 y2 io191ndb3 y3 nc y4 io182rsb2 y5 gnd y6 io177rsb2 y7 io174rsb2 y8 v cc y9 v cc y10 io154rsb2 y11 io148rsb2 y12 io140rsb2 y13 nc y14 v cc 484-pin fbga pin number a3p1000 function proasic3 packaging v1.3 3-74 y15 v cc y16 nc y17 nc y18 gnd y19 nc y20 nc y21 nc y22 v cci b1 aa1 gnd aa2 v cci b3 aa3 nc aa4 io181rsb2 aa5 io178rsb2 aa6 io175rsb2 aa7 io169rsb2 aa8 io166rsb2 aa9 io160rsb2 aa10 io152rsb2 aa11 io146rsb2 aa12 io139rsb2 aa13 io133rsb2 aa14 nc aa15 nc aa16 io122rsb2 aa17 io119rsb2 aa18 io117rsb2 aa19 nc aa20 nc aa21 v cci b1 aa22 gnd ab1 gnd ab2 gnd ab3 v cci b2 ab4 io180rsb2 ab5 io176rsb2 ab6 io173rsb2 484-pin fbga pin number a3p1000 function ab7 io167rsb2 ab8 io162rsb2 ab9 io156rsb2 ab10 io150rsb2 ab11 io145rsb2 ab12 io144rsb2 ab13 io132rsb2 ab14 io127rsb2 ab15 io126rsb2 ab16 io123rsb2 ab17 io121rsb2 ab18 io118rsb2 ab19 nc ab20 v cci b2 ab21 gnd ab22 gnd 484-pin fbga pin number a3p1000 function proasic3 packaging v1.3 3-75 part number and revision date part number 51700097-003-3 revised june 2008 list of changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current version (v1.3) page v1.2 (february 2008) pin numbers were added to the "68-pin qfn" package diagram. note 2 was added below the diagram. 3-1 the "132-pin qfn" package diagram was updated to include d1 to d4. in addition, note 1 was changed from top view to bottom view, and note 2 is new. 3-3 v1.1 (january 2008) the "68-pin qfn" section is new. 3-1 v1.0 (january 2008) in the "100-pin vqfp" a3p030 pin table, the function of pin 63 was incorrect and changed from io39r sb0 to gdb0/io38rsb0. 3-12 v2.2 (july 2007) this document was previously in datashee t v2.2. as a result of moving to the handbook format, actel has restarted the version numbers. the new version number is v1.0. n/a v2.0 (april 2007) the following pin tables were updated for a3p600: "208-pin pqfp", "256-pin fbga", and "484-pin fbga". the "144- pin fbga" table for a3p600 is new. 4-27 ? 4-63 advanced v0.7 (january 2007) notes were added to the package diag rams identifying if they were top or bottom view. n/a the a3p030 "132-pin qfn" table is new. 4-2 the a3p060 "132-pin qfn" table is new. 4-4 the a3p125 "132-pin qfn" table is new. 4-6 the a3p250 "132-pin qfn" table is new. 4-8 the a3p030 "100-pin vqfp" table is new. 4-11 advanced v0.5 (january 2006) the a3p060 "100-pin vqfp" pi n table was updated. 4-13 the a3p125 "100-pin vqfp" pi n table was updated. 4-13 the a3p060 "144-pin tqfp" pi n table was updated. 4-16 the a3p125 "144-pin tqfp" pi n table was updated. 4-18 the a3p125 "208-pin pqfp" pi n table was updated. 4-21 the a3p400 "208-pin pqfp" pi n table was updated. 4-25 the a3p060 "144-pin fbga" pi n table was updated. 4-32 the a3p125 "144-pin fbga" pin table is new. 4-34 the a3p400 "144-pin fbga" is new. 4-38 the a3p400 "256-pin fbga" was updated. 4-48 the a3p1000 "256-pin fbga" was updated. 4-54 the a3p400 "484-pin fbga" was updated. 4-58 the a3p1000 "484-pin fbga" was updated. 4-68 proasic3 packaging v1.3 3-76 advanced v0.2 (continued) the a3p250 "100-pin vqfp*" pi n table was updated. 4-14 the a3p250 "208-pin pqfp*" pin table was updated. 4-23 the a3p1000 "208-pin pqfp*" pin table was updated. 4-29 the a3p250 "144-pin fbga*" pi n table was updated. 4-36 the a3p1000 "144-pin fbga*" pin table was updated. 4-32 the a3p250 "256-pin fbga*" pi n table was updated. 4-45 the a3p1000 "256-pin fbga*" pin table was updated. 4-54 the a3p1000 "484-pin fbga*" pin table was updated. 4-68 previous version changes in current version (v1.3) page proasic3 packaging v1.3 3-77 datasheet categories categories in order to provide the latest information to designers, some datasheets are published before data has been fully characterized. datasheets are designated as ?product brief,? ?advanced,? and ?production?. the definition of these categories are as follows: product brief the product brief is a summarized version of a datasheet (advanced or production) and contains general product information. this document gives an overvi ew of specific device and family information. advanced this version contains initial estima ted information based on simulation, other products, devices, or speed grades. this information can be used as estimates, but no t for production. this label only applies to the dc and switching characteristics chapter of the datasheet and will only be used when the data ha s not been fully characterized. unmarked (production) this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subject to the export administration regu lations (ear). they could require an approved export license prio r to export from the united states. an export includes release of product or disclosure of technology to a foreign na tional inside or outside the united states. actel safety critical, life support, and high-reliability applications policy the actel products described in this advanced status document may not have completed acte l?s qualification process. actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functi onality or performance. it is the resp onsibility of each customer to ensure the fitness of any actel product (but especially a new product) for a particular purpose, including appropriateness for safety-cri tical, life-support, and othe r high-reliabili ty applications. consult actel?s terms and conditions for specific liability exclusions relating to lif e-support applications. a reliab ility report covering all of actel?s products is availabl e on the actel website at http://www.actel.com/documents/ort_report.pdf . actel also offers a variety of enhanced qualification and lot acceptance screen ing procedures. contact your local actel sales office for additional reliability information. section ii ? core architecture low-power flash technology and flash*freeze mode v1.1 1-1 core architecture of ig loo and proasic3 devices 1 ? core architecture of igloo and proasic3 devices device architecture advanced flash switch unlike sram fpgas, the low-power flash devices use a live-at-power- up isp flash switch as their programming element. flash cell s are distributed throug hout the device to provide nonvolatile, reconfigurable programming to connect signal lines to the appropriate versatile inputs and outputs. in the flash switch, two transistors shar e the floating gate, whic h stores the programming information ( figure 1-1 ). one is the sensing transistor, which is only used for writing and verification of the floating gate voltage. the other is the switchin g transistor. the latter is used to connect or separate routing nets, or to configure versatile logic. it is also used to erase the floating gate. dedicated high-performance li nes are connected as required using the flash switch for fast, low-skew, global signal distribution throughout the device core. maximum core utilization is possible for virtually any design. th e use of the flash switch technolo gy also removes the possibility of firm errors, which are increasingly common in sram-based fpgas. figure 1-1 ? flash-based switch sensing switching switch in switch out word floating gate core architecture of igloo and proasic3 devices 1-2 v1.1 igloo ? and proasic ? 3 core architecture support the low-power flash fa milies listed in table 1-1 support the architecture features described in this document. actel's low-power flas h devices (listed in table 1-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 1-1 . where the information applies to only one fami ly or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 1-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 1-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1. 2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher de nsity, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fpgas qualified for automotive applications automotive proasic3 dc and switching characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. core architecture of ig loo and proasic3 devices v1.1 1-3 device overview the low-power flash devices cons ist of multiple disti nct programmable architectural features ( figure 1-2 on page 1-3 through figure 1-4 on page 1-4 ): ? fpga fabric/core (versatiles) ? routing and clock resources (versanets) ?flashrom ? dedicated sram and/or fifo ? 15 k and 30 k gate devices do not support sram or fifo. ? automotive devices do not support fifo operation ? i/o structures ? flash*freeze technology and low-power modes note: flash*freeze technology only applies to igloo and proasic3l families. figure 1-2 ? igloo and proasic3/l device architecture overview with four i/o banks (agl600 device is shown) isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 core architecture of igloo and proasic3 devices 1-4 v1.1 figure 1-3 ? igloo plus device architecture overview with four i/o banks note: flash*freeze technology only applies to iglooe devices. figure 1-4 ? iglooe and proasic3e device architectu re overview (agle600 device is shown) ram block 4,608-bit dual-port sram or fifo block * versatile ccc i/os isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps bank 0 bank 1 bank 1 bank 3 bank 3 bank 2 * 4,608-bit dual-port sram or fifo block versatile ram block ccc pro i/os 4,608-bit dual-port sram or fifo block ram block isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps core architecture of ig loo and proasic3 devices v1.1 1-5 core architecture versatile the proprietary igloo and proasic3 device archit ectures provide granularity comparable to gate arrays. the device core consists of a sea-of-versatiles architecture. as illustrated in figure 1-5 , there are four inputs in a logic versatile cell, and each versatile can be configured using the appropriat e flash switch connections: ? any 3-input logic function ? latch with clear or set ? d-flip-flop with clear or set ? enable d-flip-flop with clear or set (on a 4 th input) versatiles can flexibly map the logic and sequenti al gates of a design. the inputs of the versatile can be inverted (allowing bubble pushing), and th e output of the tile can connect to high-speed, very-long-line routing resources. versatiles and larger fu nctions can be connec ted with any of the four levels of routing hierarchy. when the versatile is used as an enable d-flip-f lop, set/clr is supported by a fourth input. the set/clr signal can only be routed to this fo urth input over the versanet (global) network. however, if, in the user?s design, the set/clr si gnal is not routed over the versanet network, a compile warning message will be given, and the intended logic function will be implemented by two versatiles instead of one. the output of the versatile is f2 wh en the connection is to the ultra-fast loca l lines, or yl when the connection is to the efficient long-l ine or very-long-line resources. * this input can only be connected to the global clock distribution network. figure 1-5 ? low-power flash device core versatile switch (flash connection) ground via (hard connection) legend: y pin 1 0 1 0 1 0 1 0 1 data x3 clk x2 clr/ enable x1 clr xc * f2 yl core architecture of igloo and proasic3 devices 1-6 v1.1 array coordinates during many place-and-route operations in the ac tel designer software tool, it is possible to set constraints that requir e array coordinates. table 1-2 provides array coordinates of core cells and memory blocks for proasi c3 and igloo devices. table 1-3 provides the information for igloo plus devices. the array coordinates are measured from the lower left (0, 0) they can be used in region constraints for spec ific logic groups/b locks, designated by a wi ldcard, and can contain core cells, memories, and i/os. i/o and cell coordinates are used for placement constraints. two coordina te systems are needed because there is not a one-to-one correspondence be tween i/o cells and core cells. in addition, the i/o coordinate system changes depending on the die/package combination. it is not listed in table 1-2 . the designer chipplanner tool provides the ar ray coordinates of all i/o locations. i/o and cell coordinates are used for plac ement constraints. however, i/o placement is easier by package pin assignment. figure 1-6 on page 1-7 illustrates the array coordinates of a 600 k gate device. for more information on how to use a rray coordinates for region/pla cement constraints, see the designer user's guide or online help (available in the software) for software tools. table 1-2 ? igloo and proasic3 array coordinates device versatiles memory rows entire die min. max. bottom top min. max. proasic3/ proasic3l igloo x y x y (x, y) (x, y) (x, y) (x, y) a3p015 agl015 3 2 34 13 none none (0, 0) (37, 15) a3p030 agl030 3 3 66 13 none none (0, 0) (69, 15) a3p060 agl060 3 2 66 25 none (3, 26) (0, 0) (69, 29) a3p125 agl125 3 2 130 25 none (3, 26) (0, 0) (133, 29) a3p250/l agl250 3 2 130 49 none (3, 50) (0, 0) (133, 53) a3p400 3 2 194 49 none (3, 50) (0, 0) (197, 53) a3p600/l agl600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) a3p1000/l agl1000 3 4 258 99 (3, 2) (3, 100) (0, 0) (261, 103) a3pe600 agle600 3 4 194 75 (3, 2) (3, 76) (0, 0) (197, 79) a3pe1500 3 4 322 123 (3, 2) (3, 124) (0, 0) (325, 127) a3pe3000/l agle3000 3 6 450 173 (3, 2) or (3, 4) (3, 174) or (3, 176) (0, 0) (453, 179) table 1-3 ? igloo plus array coordinates device versatiles memory rows entire die min. max. bottom top min. max. igloo plus x y x y (x, y) (x, y) (x, y) (x, y) aglp030 2 3 67 13 none none (0, 0) (69, 15) aglp060 2 2 67 25 none (3, 26) (0, 0) (69, 29) aglp125 2 2 131 25 none (3, 26) (0, 0) (133, 29) core architecture of ig loo and proasic3 devices v1.1 1-7 note: the vertical i/o tile coordinates are not shown. west-side coordinates are {(0, 2) to (2, 2)} to {(0, 77) to (2, 77)}; east-side coordinates are {(19 5, 2) to (197, 2)} to {(195, 77) to (197, 77)}. figure 1-6 ? array coordinates for agl600, agle600, a3p600, and a3pe600 top row (5, 1) to (168, 1) bottom row (7, 0) to (165, 0) top row (169, 1) to (192, 1) i/o tile memory blocks memory blocks memory blocks ujtag flashrom top row (7, 79) to (189, 79) bottom row (5, 78) to (192, 78) i/o tile (3, 77) (3, 76) memory blocks (3, 3) (3, 2) versatile (core) (3, 75) versatile (core) (3, 4) (0, 0) (197, 0) (194, 2) (194, 3) (194, 4) versatile (core) (194, 75) versatile (core) (197, 79) (194, 77) (194, 76) (0, 79) (197, 1) core architecture of igloo and proasic3 devices 1-8 v1.1 routing architecture the routing structure of low-power flash devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast loca l resources; efficient long-line resources; high-speed, very-long-line resource s; and the high-performa nce versanet networks. the ultra-fast local resources are de dicated lines that allo w the output of each versatile to connect directly to every input of th e eight surrounding versatiles ( figure 1-7 on page 1-8 ). the exception to this is that the set/clr input of a versatile co nfigured as a d-flip-flop is driven only by the versatile global network. the efficient long-line resour ces provide routing for longer distance s and higher-fanout connections. these resour ces vary in length (spanning one, two, or four versatiles), run both vertically and horizontally, an d cover the entire device ( figure 1-8 on page 1-9 ). each versatile can drive signals onto the efficient lo ng-line resources, which can access every input of every versatile. routing software automatically inserts active buffers to limit loading effects. the high-speed, very-long-line resources, which span the entire device with minimal delay, are used to route very long or high-fanout nets: length 1 2 versatiles in the vertical direction and length 16 in the horizontal direction from a given core versatile ( figure 1-9 on page 1-9 ). very long lines in low-power flash devices have been enhanced over those in previous proasic families. this provides a significant performance boost for long-reach signals. the high-performance versanet global networks ar e low-skew, high-fanout nets that are accessible from external pins or internal lo gic. these nets are typically used to distribute clocks, resets, and other high-fanout nets requirin g minimum skew. the versanet netw orks are implemented as clock trees, and signals can be introduced at any junc tion. these can be employ ed hierarchically, with signals accessing every input of every versatil e. for more details on versanets, refer to global resources in actel lo w-power flash devices. note: input to the core cell for the d-flip-flop set a nd reset is only available via the versanet global network connection. figure 1-7 ? ultra-fast local lines connected to the eight nearest neighbors l l l l l l inputs output ultra-fast local lines (connects a versatile to the adjacent versatile, i/o buffer, or memory block) l ll long lines core architecture of ig loo and proasic3 devices v1.1 1-9 figure 1-8 ? efficient long-line resources figure 1-9 ? very-long-line resources l l llll l lllll l l llll l l llll l l llll spans 1 versatile spans 2 versatiles spans 4 versatiles spans 1 versatile spans 2 versatiles spans 4 versatiles versatile high-speed, very-long-line resources pad ring pad ring i/o ring i/o ring pad ring 1612 block of versatiles sram core architecture of igloo and proasic3 devices 1-10 v1.1 related documents handbook documents global resources in actel low-power flash devices http://www.actel.com/documents/lpd_glorbal_hbs.pdf user?s guides designer user's guide http://www.actel.com/documents/designer_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet. to improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage info rmation. no technical chan ges were made to the content unless explicitly listed. part number 51700094-002-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) table 1-1 low-power flash families and the accompanying text was updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 1-2 the "device overview" section was updated to note that 15 k devices do not support sram or fifo. 1-3 figure 1-3 igloo plus device architecture overview with four i/o banks is new. 1-4 table 1-2 igloo and proasic3 array coordinates was updated to add a3p015 and agl015. 1-6 table 1-3 igloo plus array coordinates is new. 1-6 v1.1 2-1 low-power modes in ac tel proasic3/e fpgas 2 ? low-power modes in actel proasic3/e fpgas introduction the demand for low-power syst ems and semicond uctors, combined with the strong growth observed for value-based fpgas, is driving growing demand for low-power fpgas. for portable and battery-operated applications, power consum ption has always been the greatest challenge. the battery life of a system and on-board devices has a direct impact on the success of the product. as a result, fpgas used in these applications should meet low-power co nsumption requirements. actel proasic ? 3/e fpgas offer low power consumption ca pability inherited from their nonvolatile and live-at-power-up (lapu) flash technology . this application note describes the power consumption and how to use different power saving modes to further reduce power consumption for power-conscious electronics design. power consumption overview in evaluating the power consumption of fpga techno logies, it is important to consider it from a system point of view. generally, the overall power consumption should be based on static, dynamic, inrush, and configuration power. few fpgas implement ways to reduce static power consumption utilizing sleep modes. sram-based fpgas use volatile memory for their config uration, so the device must be reconfigured after each power-up cy cle. moreover, during this initialization state, the logic could be in an indeterminate state, wh ich might cause inrush current and power spikes. more complex power supplies are required to el iminate potential system power-up failures, resulting in higher costs. for portable elec tronics requiring frequent power-up and -down cycles, this directly affects battery life, requiring more freq uent recharging or replacement. sram-based fpga total power consumption = p static + p dynamic + p inrush + p config eq 2-1 proasic3/e total power consumption = p static + p dynamic eq 2-2 unlike sram-based fpgas, actel flash-based fpgas are nonvolatile and do not require power-up configuration. additionally, actel nonvolatile flash fpgas are live at power-up and do not require additional support comp onents. total power consumption is reduced as the in rush current and configuration power comp onents are eliminated. note that the static power co mponent can be reduced in flash fpgas (such as the proasic3/e devices) by entering user low st atic mode or sleep mode. this leads to an extremely low static power component contribu tion to the total system power consumption. the following sections describe the usage of stat ic (idle) mode to redu ce the power component, user low static mode to reduce the static powe r component, and sleep mode and shutdown mode to achieve a range of power consumption when the fpga or system is idle. table 2-1 on page 2-2 summarizes the different low-power modes offered by proasic3/e devices. low-power modes in ac tel proasic3/e fpgas 2-2 v1.1 static (idle) mode in static (idle) mode, the cloc k inputs are not switching and the static power consumption is the minimum power required to keep the device powered up. in this mode, i/os are only drawing the minimum leakage current sp ecified in the datasheet. also, in static (idle) mode, embedded sram, i/os, and registers retain their va lues, so the device can enter an d exit this mode without any penalty. if the embedded plls are used as the clock sour ce, static (idle) mode can be entered easily by pulling low the pll powerdown pin (active-low). by pulling the pll powerdown pin to low, the pll is turned off. refer to figure 2-1 on page 2-3 for more information. table 2-1 ? proasic3/e low-power modes summary mode power supplies / clock status needed to start up active on ? all, clock n/a (already active) off ? none static (idle) on ? all initiate clock source. off ? no active clock in fpga no need to initialize volatile contents. optional: enter user low stat ic (idle) mode by enabling ulsicc macro to further reduce power consumption by powering down flashrom. sleep on ? v cci need to turn on core. off ? v cc core voltage load states from external memory. lapu enables immediate operation when power returns. as needed, restore volatile contents from external memory. optional: save state of volatile contents in external memory. shutdown on ? none need to turn on v cc , v cci . off ? all power supplies applicable to pa3e and a3p 030; cold-sparing and hot- insertion allow the device to be powered down without bringing down the system. lapu enables immediate operation when power returns. low-power modes in ac tel proasic3/e fpgas v1.1 2-3 user low static (idle) mode user low static (idle) mode is an advanced featur e supported by proasic3/e devices to reduce static (idle) power consumption. entering and exiting this mode is made possible using the ulsicc macro by setting its value to disable/ enable the user low static (idl e) mode. under typical operating conditions, characterization re sults show up to 25% reduction of the static (idle) power consumption. the greatest power savings in terms of percentage are seen in the smaller members of the proasic3 family. the acti ve-high control signal for user low static (idle) mode can be generated by internal or external logic. when the device is oper ating in user low static (idle) mode, flashrom functionality is temporarily disabled to save power. if flashrom functionality is needed, the device can exit user low static mo de temporarily and re-enter the mode once the functionality is no longer needed. to utilize user low static (idle) mode , simply instantiate the ulsicc macro ( table 2-2 on page 2-4 ) in your design, and connect the in put port to either an internal logic signal or a device package pin, as illustrated in figure 2-2 on page 2-4 or figure 2-3 on page 2-5 , respectively. the attribute is used so the synplify ? synthesis tool will no t optimize the instance with no output port. this mode can be used to lower standard static (idle) power consumption when the flashrom feature is not needed. configuring the device to enter user low st atic (idle) mode is beneficial when the fpga enters and exits static mode fr equently and lowering po wer consumption as much as possible is desired. the device is still functional, and data is re tained in this state so the device can enter and exit this mode quic kly, resulting in reduced total po wer consumption. the device can also stay in user low static mode when the flashrom featur e is not used in the device. figure 2-1 ? ccc/pll macro clka gla glb yb glc yc lock powerdown oadiv[4:0]* oamux[2:0]* dlygla[4:0]* obdiv[4:0]* obmux[2:0]* dlyyb[4:0]* dlyglb[4:0]* ocdiv[4:0]* ocmux[2:0]* dlyyc[4:0]* dlyglc[4:0]* findiv[6:0]* fbdiv[6:0]* fbdly[4:0]* fbsel[1:0]* xdlysel* vcosel[2:0]* low-power modes in ac tel proasic3/e fpgas 2-4 v1.1 table 2-2 ? using ulsicc macro* vhdl verilog component ulsicc port ( lsicc : in std_ulogic); end component; example: component ulsicc port ( lsicc : in std_ulogic); end component; attribute syn_noprune : boolean; attribute syn_noprune of u1 : label is true; u1: ulsicc port map(myinputsignal); module ulsicc(lsicc); input lsicc; endmodule example: ulsicc u1(.lsicc(myinputsignal)) /* synthesis syn_noprune=1 */; * supported in libero ide v7.2 and newer versions. figure 2-2 ? user low static (idle) mode ap plication?internal control signal internal signal ulsicc macro flashrom programming circuitry proasic3/e device low-power modes in ac tel proasic3/e fpgas v1.1 2-5 sleep mode actel proasic3/e fpgas support sleep mode when device functionality is not required. in sleep mode, the v cc (fpga core voltage) supply is turned off, either grounded or le ft floating, resulting in the fpga core being turned off to reduce power consumption. wh ile the proasic3/e device is in sleep mode, the rest of the system is still operat ing and driving the input buffers of the proasic3/e device. the driven inputs do not pull up power planes, and the current draw is limited to a minimal leakage current. table 2-3 shows the status of the power supplies in sleep mode. when a power supply is powered off, the corresponding power pin ca n be left floating or grounded. figure 2-3 ? user low static (idle) mode ap plication?external control signal ulsicc macro external signal any user's i/o flashrom programming circuitry proasic3/e device figure 2-4 ? user low static (idle) mode timing diagram normal operation user low static mode 1 s1 s normal operation ulsicc signal table 2-3 ? sleep mode?power supply requir ements for proasic3/e devices power supplies proasic3/e v cc powered off v cci = vmv powered on v jtag powered on v pump powered on low-power modes in ac tel proasic3/e fpgas 2-6 v1.1 table 2-4 shows the current draw in sleep mode for an a3p250 devi ce with the following test conditions: v cci = vmv; v cc = floating or gnd; v jtag = floating or gnd; v pump = floating or gnd. table 2-5 shows the current draw in sleep mode for an a3pe600 de vice with the following test conditions: v cci = vmv; v cc = floating or gnd; v jtag = floating or gnd; v pump = floating or gnd. proasic3/e devices were designed such that before device po wer-up, all i/os are in tristate mode. the i/os will remain tri stated during power-up unt il the last voltage supply (v cc or v cci ) is powered to its functional level. after the last supply reaches the functional level, the outputs will exit the tristate mode and drive the logic at the input of the output buffer . the behavior of user i/os is independent of the v cc and v cci sequence or the state of other fpga voltage supplies (v pump and v jtag ). during power-down, device i/os become tristated once the first power supply (v cc or v cci ) drops below its brownout voltage level. the i/o behavior during power-down is also independent of voltage supply sequencing. figure 2-5 on page 2-7 shows a timing diagram for the fpga core enteri ng the activation and deactivation trip points for a ty pical application when the v cc power supply ramp rate is 100 s (ramping from 0 v to 1.5 v). this is, in fact, th e timing diagram for the fpga entering and exiting sleep mode, as it is dependent on powering down or powering up v cc . depending on the ramp rate of the power supply and board-level configur ations, the user can easily calculate how long it takes for the core to become active or in active. for more information, refer to the power-up/-down behavior of proasic3/e devices application note. table 2-4 ? a3p250 current draw in sleep mode typical conditions a3p250 i cci (a) i cci (a) per bank v cci = 3.3 v 31.57 7.89 v cci = 2.5 v 23.96 5.99 v cci = 1.8 v 17.32 4.33 v cci = 1.5 v 14.46 3.62 i cc fpga core 0.0 0.0 leakage current per i/o 0.1 0.1 v pump 0.0 0.0 note: the data in this table were taken under typical conditions and are based on characterization. the data is not guaranteed. table 2-5 ? a3pe600 current draw in sleep mode typical conditions a3pe600 i cci (a) i cci (a) per bank v cci = 3.3 v 59.85 7.48 v cci = 2.5 v 45.50 5.69 v cci = 1.8 v 32.98 4.12 v cci = 1.5 v 27.66 3.46 v cci = 0 v or floating 0.0 0.0 i cc fpga core 0.0 0.0 leakage current per i/o 0.1 0.1 i pump 0.0 0.0 note: the data in this table were taken under typical conditions and are based on characterization. the data is not guaranteed. low-power modes in ac tel proasic3/e fpgas v1.1 2-7 shutdown mode for proasic3e and a3p030, shutdown mode can be entered by turning off all power supplies when device functionality is not needed. cold-sparing an d hot-insertion features enable the device to be powered down without turn ing off the entire system. when po wer returns, the live at power-up feature enables immediate operation of the device. using sleep mode or shut down mode in the system depending on the power supply and components used in an application, there are many ways to turn the power supplies connected to the device on or off. for example, figure 2-6 shows how a microprocessor is used to con trol a power fet. it is recommended that power fets with low on resistance be used to perform the switching action. figure 2-5 ? entering and exiting sleep mode?typical timing diagram v cc v cc = 1.5 v sleep mode t activation trip point va = 0.85 0.25 v deactivation trip point vd = 0.75 0.25 v figure 2-6 ? controlling power on/off state using microprocessor and power fet microprocessor proasic3/e power on/off control signal p-channel power fet 1.5 v power supply v cc pin low-power modes in ac tel proasic3/e fpgas 2-8 v1.1 alternatively, figure 2-7 shows how a microprocessor can be used with a voltage regulator's shutdown pin to turn the power supplies connected to the device on or off. though sleep mode or shutdown mode can be used to save power, the content of the sram and the state of the registers is lost when power is turn ed off if no other measure is taken. to keep the original contents of the device, a low-cost external serial eeprom ca n be used to sa ve and restore the device contents when entering and exiting sleep mode. in the embedded sram initialization using external serial eeprom application note, detailed informa tion and a reference design are provided to initialize the embedded sram using an external serial eepr om. the user can easily customize the reference de sign to save and restor e the fpga state when en tering and exiting sleep mode. the microcontrolle r will need to manage this acti vity, so before powering down v cc , the data must be read from the fpga and stored exte rnally. similarly, after the fpga is powered up, the microcontroller must allow th e fpga to load the data from external memory and restore its original state. conclusion actel proasic3/e fpgas inherit low-power consum ption capability from their nonvolatile and live- at-power-up flash-based technology. power consumption can be reduced further using the static (idle), user low static (idle), sleep, or shutdown power modes. all these features result in a low-power, cost-effective, single-chip solution desi gned specifically for po wer-sensitive electronics applications. figure 2-7 ? controlling power on/off state using microprocessor and voltage regulator microprocessor proasic3/e showdown control signal for v cc showdown control signal for v cci voltage regulator v cc power pin v cc power pin power supply low-power modes in ac tel proasic3/e fpgas v1.1 2-9 related documents application notes power-up/down behavior of proasic3/e devices http://www.actel.com/documents/ proasic3_e_powerup_hbs.pdf embedded sram initialization using external serial eeprom http://www.actel.com/documen ts/embeddedsraminit_an.pdf handbook documents sram and fifo memories in actel?s in actel?s low-power flash devices http://www.actel.com/docum ents/lpd_sramfifo_hbs.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content part number 51700094-003-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the part number for this document was changed from 51700094-002-0 to 51700094-003-1. n/a 51900138-2/10.06 the power supplies / clock status description was updated for static (idle) in table 2-1 proasic3/e lo w-power modes summary . 2-2 programming information was updated in the "user low static (idle) mode" section . 2-3 51900138-1/6.06 the "user low static (idle) mode" section was updated to include information about allowing programming in the ulsicc mode. 2-3 figure 2-2 user low static (idle) mode application?internal control signal was updated. 2-4 figure 2-3 user low static (idle) mode applicatio n?external co ntrol signal was updated. 2-5 51900138-0/6.05 in table 2-4 a3p250 current draw in sleep mode , "v cci = 1.5 v" was changed from 3.6158 to 3.62. 2-6 in table 2-5 a3pe600 current draw in sleep mode , "v cci = 2.5 v" was changed from 5.6875 to 3.69. 2-6 global resources and clock conditioning v1.1 3-1 global resources in actel low-power flash devices 3 ? global resources in actel low-power flash devices introduction actel igloo, ? fusion, and proasic ? 3 fpga devices offer a powerful, low-delay versanet global network scheme and have extensiv e support for multiple clock doma ins. in addition to the clock conditioning circuits (cccs) and phase-locked lo ops (plls), there is a co mprehensive global clock distribution network called a versanet global netw ork. each logical elemen t (versatile) input and output port has access to these global networks . the versanet global networks can be used to distribute low-skew clock signals or high-fanout ne ts. in addition, these hi ghly segmented versanet global networks offer users the flexibility to create low-skew local netw orks using spines. this document describes versanet global networks and discusses how to assign signals to these global networks and spines in a design flow. details conc erning low-power flash de vice plls are described in clock conditioning circuits in igloo and proasic3 devices . this document describes the low-power flash devices? global architecture and uses of these global networks in designs. global architecture low-power flash devices offer powerful and flexible control of circuit timing through the use of analog circuitry. each chip has up to six cccs, some with plls. ? in iglooe, proasic3el, and proasic3e devices, all cccs have plls?hence, 6 plls per device. ? in igloo, igloo plus, proasic3l, and proasic3 devices, the west ccc contains a pll core (except in 15 k and 30 k devices). each pll includes delay lines, a phase shifter (0, 90, 180, 270), and cl ock multipliers/dividers. each ccc has all the circuitry needed for the selection and interconnection of inputs to the versanet global network. the east and west cccs each have access to three versanet global lines on each side of the chip (six global lines total). the cccs at the four corners each have access to three quadrant global lines in each quadrant of the chip (except in 15 k gate and 30 k gate devices). in 15 k and 30 k gate devices, all six versanet gl obal lines are driven fr om three southern i/os, located toward the east and west si des. each of these tiles can be configured to select a central i/o on its respective side or an inte rnal routed sign al as the input signal. 15 k and 30 k gate devices do not support any clock conditioning circuitry, nor do they contain the versanet global network concept of top and bottom spines. the flexible use of the versanet global network allows the desi gner to address several design requirements. user applications th at are clock-resource-intensive can easily route external or gated internal clocks using versanet global routing netw orks. designers can also drastically reduce delay penalties and minimize resource usage by mapping critical, high-fanout nets to the versanet global network. the following sections give an overview of the versanet global network, the structure of the global network, and the clock aggregation feature that enables a design to have very low clock skew using spines. global resources in actel low-power flash devices 3-2 v1.1 global resource support in low-power devices the low-power flash families listed in table 3-1 support the global reso urces and the functions described in this document. actel's low-power flas h devices (listed in table 3-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 3-1 . where the information applies to only one fami ly or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 3-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 3-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1. 2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-perfo rmance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher density, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fp gas qualified for automotive applications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. global resources in actel low-power flash devices v1.1 3-3 versanet global network distribution one of the architectural benefits of low-power flash architecture is the set of powerful, low-delay versanet global networks that can access the versatiles, sram, an d i/o tiles of the device. each device offers a chip global networ k with six global lines that are distributed from th e center of the fpga array. in addition, each device, (except th e 15 k and 30 k gate device), has four quadrant global networks, each with three regional global line resources. these quadrant global networks can only drive a signal inside their own quadrant. each core versatile has access to nine global line resources?three quadrant and six chip-wide (main) global networks?and a total of 18 globals are available on the device (3 4 region al from each quadrant and 6 global). figure 3-1 shows simplified devi ce architecture, and figure 3-2 on page 3-4 shows an overview of the versanet global networks. the versanet global networks are segmented and consist of versanet glob al networks, spines, global ribs, and global multiplexers (muxes), as shown in figure 3-1 . the global networks are driven from the global rib at the center of the die or quadrant global networks at the north or south side of the die. the global network uses th e mux trees to access the spine, and the spine uses the clock ribs to ac cess the versatile. access is available to the chip or quadrant global networks and the spines through th e global muxes. access to the spine using the global muxes is explained in the "spine architecture" section on page 3-4 . these versanet global networks offer fast, lo w-skew routing resources for high-fanout nets, including clock signals. in addition, these high ly segmented global networks offer users the flexibility to create low-skew loca l networks using spines for up to 252 internal/external clocks or other high-fanout nets in low-power flash device s. optimal usage of these low-skew networks can result in significant improv ement in design performance. note: not applicable to 15 k and 30 k gate devices figure 3-1 ? overview of versanet global network and device architecture pa d rin g pa d rin g pa d rin g i/o rin g i/orin g c hip (main) g lo b al pa d s g lo b al pa d s hi g h-performan c e g lo b al network g lo b al s pine g lo b al ri b s sc ope of s pine (sha d e d area plus lo c al rams an d i/os) s pine- s ele c tion mux em b e dd e d ram blo c ks lo g i c tiles top s pine bottom s pine t1 b1 t2 b2 t3 b3 qua d rant g lo b al pa d s global resources in actel low-power flash devices 3-4 v1.1 spine architecture the low-power flash device archit ecture allows the versanet glob al networks to be segmented. each of these networks contains spines (the vertical branches of the global network tree) and ribs that can reach all the versatiles inside its region . the nine spines available in a vertical column reside in global networks with two separate regions of scope: the quadrant global network, which has three spines, and the chip (main) global netw ork, which has six spines. note that there are three quadrant spines in each qu adrant of the device (except in 15 k and 30 k gate devices). there are four quadrant global network regions per device. in 15 k and 30 k gate devices, there is no quadrant clock network, so there are only six spin es in each spine tree. th e spines are the vertical branches of the global network tree, shown in figure 3-2 . each spine in a vertical co lumn of a chip (main) global network is further divided into two equal- length spine segments: on e in the top and one in the bottom half of the die (except in 15 k and 30 k gate devices). top and bottom spine segments radiating from the center of a device have the same height. however, just as in the proasic plus ? family, signals assigned only to the top and bottom spine cannot access the middle two rows of the die. the spines for quadrant clock networks do not cross the middle of the die and cannot access the middle two rows of the architecture. each spine and its associated ribs cover a certain area of the device (the "scope" of the spine; see figure 3-2 ). each spine is accessed by the dedicated global networ k mux tree architecture, which defines how a particular spine is driven?either by the signal on the global network from a ccc, for example, or by another net defined by the user. details of the chip (main) global network spine- selection mux are presented in figure 3-4 on page 3-7 . the spine drivers for each spine are located in the middle of the die. quadrant spines can be driven from user i/os on th e north and south sides of the die. the ability to drive spines in the quadrant glob al networks can have a significan t effect on system performance for high-fanout inputs to a design . access to the top quadrant spine regions is from the top of the die, and access to the bottom qu adrant spine regions is from the bottom of the die. the a3pe3000 device has 28 clock trees and each tree has nine spines; this flexible global network architecture enables users to map up to 252 different inte rnal/external clocks in an a3pe3000 device. note: not applicable to 15 k and 30 k gate devices. figure 3-2 ? simplified versanet global network north quadrant global network south quadrant global network chip (main) global network 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc ccc ccc ccc ccc ccc global resources in actel low-power flash devices v1.1 3-5 spine access the physical location of each sp ine is identified by the letter 't' (top) or 'b' (bottom) and an accompanying number (t n or b n ). the number n indicates the horizontal location of the spine; 1 refers to the first spine on the left side of the die. since there are six chip spines in each spine tree, there are up to six spines available fo r each combination of 't' (or 'b') and n (for example, six t1 spines). similarly, there are three quadrant spines available for each combination of 't' (or 'b') and n (for example, four t1 spines), as shown in figure 3-3 on page 3-6 . table 3-2 ? globals/spines/rows for ig loo and proasic3 devices proasic3/ proasic3l devices igloo devices chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatile s rows in each spine a3p015 agl015 6 0 1 9 9 384 384 12 a3p030 agl030 6 0 2 9 18 384 768 12 a3p060 agl060 6 12 4 9 36 384 1,536 12 a3p125 agl125 6 12 8 9 72 384 3,072 12 a3p250/l agl250 6 12 8 9 72 768 6,144 24 a3p400 6 12 12 9 108 768 9,216 24 a3p600/l agl600 6 12 12 9 108 1,152 13,824 36 a3p1000/l agl1000 6 12 16 9 144 1,536 24,576 48 a3pe600 agle600 6 12 12 9 108 1,120 13,440 35 a3pe1500 6 12 20 9 180 1,888 37,760 59 a3pe3000/l agle3000 6 12 28 9 252 2,656 74,368 83 table 3-3 ? globals/spines/rows fo r igloo plus devices igloo plus devices chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatiles rows in each spine aglp030 6 0 2 9 18 384* 792 12 aglp060 6 12 4 9 36 384* 1,584 12 aglp125 6 12 8 9 72 384* 3,120 12 note: *clock trees that are located at far left and far right will support more versatiles. table 3-4 ? globals/spines/rows for fusion devices fusion device chip globals quadrant globals (43) clock trees globals/ spines per tree to t a l spines per device versatiles in each tree to t a l versatiles rows in each spine afs090 6 12 6 9 54 384 2,304 12 afs250 6 12 8 9 72 768 6,144 24 afs600 6 12 12 9 108 1,152 13,824 36 afs1500 6 12 20 9 180 1,920 38,400 60 global resources in actel low-power flash devices 3-6 v1.1 spines are also called local clocks, and are ac cessed by the dedicated global mux architecture. these muxes define how a particu lar spine is driven. refer to figure 3-4 on page 3-7 for the global mux architecture. the muxes for each chip global spine are located in the middle of the die. access to the top and bottom chip global spine is available from the middle of the die. there is no control dependency between the top and bottom spines. if a top spine, t1, of a chip global network is assigned to a net, b1 is not wasted and can be used by the global clock network. the signal assigned only to the top or bottom sp ine cannot access the mi ddle two rows of the architecture. however, if a spin e is using the top and bottom at the same time (t1 and b1, for instance), the previous restriction is lifted. the muxes for each quadrant global spine are located in the north and south sides of the die. access to the top and bottom quadrant global sp ines is available from th e north and south sides of the die. since the muxes for quadrant spines are located in the north and south sides of the die, you should not try to drive t1 and b1 quadrant spines from the same signal. figure 3-3 ? chip global aggregation tn tn+1 tn+2 tn+3 tn+4 a b c global network global resources in actel low-power flash devices v1.1 3-7 using clock aggregation clock aggregation allows for multi-spine cloc k domains to be assigned using hardwired connections, with out adding any extra skew . a mux tree, shown in figure 3-4 , provides the necessary flexibility to allow long lines, local reso urces, or i/os to access domains of one, two, or four global spines. signal acce ss to the clock aggregation system is achieved through long-line resources in the central rib in the center of the die, and also through loca l resources in the north and south ribs, allowing i/os to feed directly into the clock system. as figure 3-5 indicates, this access system is contiguous. there is no break in the middle of the chip fo r the north and south i/o versanet access. this is different from the quadrant clocks located in these ribs, which only reach the middle of the rib. figure 3-4 ? spine selection mu x of global tree figure 3-5 ? clock aggregation tree architecture internal/external signal internal/external signal internal/external signals spine global rib global driver mux tree node mux tree node mux internal/external signals tree node mux global spine global rib global driver and mux i/o access internal signal access i/o tiles global signal access tree node mux global resources in actel low-power flash devices 3-8 v1.1 clock aggregation architecture this clock aggregation feature allows a balanced clock tree, which improves clock skew. the physical regions for clock aggregation are defined from left to right and shift by one spine. for chip global networks, there are three types of clock aggregation available, as shown in figure 3-6 : ? long lines that can drive up to four adjacent spines ? long lines that can drive up to two adjacent spines ? long lines that can drive one spine there are three types of clock aggregation av ailable for the quadrant spines, as shown in figure 3-6 : ? i/os or local resources that can drive up to four adjacent spines ? i/os or local resources that can drive up to two adjacent spines ? i/os or local resources that can drive one spine ? as an example, a3pe600 and afs600 devices have twelve spine location s: t1, t2, t3, t4, t5, t6, b1, b2, b3, b4, b5, and b6. table 3-5 shows the clock aggreg ation you can have in a3pe600 and afs600. the clock aggregation for the quadrant spines can cross over from the left to right quadrant, but not from top to bottom. the quad rant spine assignment t1:t4 is legal, but the quadrant spine assignment t1:b1 is not legal. no te that this clock aggregation is hardwired. you can always assign signals to spine t1 and b2 by instantiating a buffer, but this may ad d skew in the signal. figure 3-6 ? four spines aggregation tn tn + 1 tn + 2 tn + 4 a b c tn + 3 table 3-5 ? spine aggregation in a3pe600 or afs600 clock aggregation spine 1 spine t1, t2, t3, t4, t5, t6, b1, b2, b3, b4, b5, b6 2 spines t1:t2, t2: t3, t3:t4, t4:t5, t5:t6, b1:b2, b2:b3, b3:b4, b4:b5, b5:b6 4 spines b1:b4, b2:b5, b3:b 6, t1:t4, t2:t5, t3:t6 global resources in actel low-power flash devices v1.1 3-9 i/o banks and global i/os the following sections give an overview of naming conventions and other related i/o information. naming of global i/os in low-power flash devices, the gl obal i/os have access to certain clock conditioning circuitry and have direct access to the global network. additionally, the global i/os can be used as regular i/os, since they have identical capabilities to thos e of regular i/os. due to the comprehensive and flexible nature of the i/os in low-p ower flash devices, a naming sche me is used to show the details of the i/o. the global i/o uses the generic name gmn/iouxwbyvz. refer to the i/o structure section of the handbook for the device that you ar e using for more information on this naming convention. figure 3-7 represents the global input pins connec tion to the northwest ccc or northwest quadrant global networks for a low-power flash device. each global buffer, as well as the pll reference clock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core since each bank can have a differ ent i/o standard, the user should be careful to choose the correct global i/o for the design. there ar e 54 global pins availa ble to access 18 global networks. for the single-ended and voltage-referenc ed i/o standards, you can use any of these three available i/os to access the global network. for di fferential i/o standards such as lvds and lvpecl, the i/o macro needs to be placed on gaa0 and gaa1 or a simi lar location. the unassi gned global i/os can be used as regular i/os. note that pin names starti ng with gf and gc are associated with the chip global networks, and ga, gb, gd, and ge are used for quadrant global networks. figure 3-7 ? global i/o overview + + source for ccc (clka or clkb or clkc) each shaded box represents an inbuf or inbuf_lvds/lvpecl macro, as appropriate. to core routed clock (from fpga core) sample pin names gaa0/io0ndb0v0 1 gaa1/io00pdb0v0 1 gaa2/io13pdb7v1 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source. 2 global resources in actel low-power flash devices 3-10 v1.1 unused global i/o configuration the unused clock inputs behave similarly to the unused pro i/ os. the actel designer software automatically conf igures the unused global pins as inputs with pull-up resistors if they are not used as regular i/o. i/o banks and global i/o standards in low-power flash devices, any i/o or internal logic can be used to drive the global network. however, only the global macro placed at the global pins will use the hardwired connection between the i/o and global network. global signal (signal driving a global macro) assignment to i/o banks is no different from regular i/o assignme nt to i/o banks with the exception that you are limited to the pin placem ent location available. only global signals compatible with both the v cci and v ref standards can be assign ed to the same bank. design recommendations the following sections provide design flow recommendations for using a global network in a design. ? "global macros and i/o standards" ? "using global macros in synplicity" on page 3-12 ? "global promotion and demoti on using pdc" on page 3-13 ? "spine assignment" on page 3-14 ? "designer flow for global assignment" on page 3-15 ? "simple design example" on page 3-17 ? "global management in pll design" on page 3-19 ? "using spines of occupied global networks" on page 3-20 global macros and i/o standards low-power flash devices have six chip global networks and four quadrant clock networks. however, the same clock macros are used for assigning signals to chip globals and quadrant globals. depending on th e clock macro placement or assignment in the physical design constraint (pdc) file or multiview navigator (mvn), the signal will use the chip global network or quadrant network. table 3-6 on page 3-11 lists the clock macros available for low-power flash devices. refer to the igloo, fusion and proasi c3 macro library guide for details. global resources in actel low-power flash devices v1.1 3-11 use these available macros to assign a signal to the global network. in addition to these global macros, pll and clkdly macros ca n also drive the global networks . use i/o?standard?specific clock macros (clkbuf_x) to instan tiate a specific i/o standar d for the global signals. table 3-7 shows the list of these i/o?standard?specific macros. note that if you use these i/o?standard?specific clock macros, you cannot change the i/ o standard later in the design stage. if you use the regular clkbuf macro, you can use mvn or the pdc file in designer to change the i/o standard. the default i/o standard for clkbuf is lvttl in the current actel libero ? integrated design environment (ide) and designer software. table 3-6 ? clock macros macro name description symbol clkbuf input macro for clock network clkbuf_x input macro for clock network with specific i/o standard clkbuf_lvds/ lvpecl lvds or lvpecl input macro for clock network clkint internal clock interface clkbibuf bidirectional macro with input dedicated to routed clock network y pad clkbuf pad y clkbuf_x padn padp clkbibuf_lvpecl y padn padp clkbibuf_lvds y ay clkint d y e pad clkbibu f table 3-7 ? i/o standards within clkbuf name description clkbuf_lvcmos5 lvcmos clock buffer with 5.0 v cmos voltage level clkbuf_lvcmos33 lvcmos clock buffer with 3.3 v cmos voltage level clkbuf_lvcmos25 lvcmos clock buffer with 2.5 v cmos voltage level 1 clkbuf_lvcmos18 lvcmos clock buffer with 1.8 v cmos voltage level clkbuf_lvcmos15 lvcmos clock buffer with 1.5 v cmos voltage level clkbuf_lvcmos12 lvcmos clock buffer with 1.2 v cmos voltage level clkbuf_pci pci clock buffer clkbuf_pcix pcix clock buffer clkbuf_gtl25 gtl clock buffer wi th 2.5 v cmos voltage level 1 clkbuf_gtl33 gtl clock buffer wi th 3.3 v cmos voltage level 1 notes: 1. supported in only the iglooe and proasic3e devices 2. by default, the clkbuf macro uses the 3.3 v lvttl i/o technology. global resources in actel low-power flash devices 3-12 v1.1 the current synthesis tool libraries only infer the clkbuf or clki nt macros in the netlist. all other global macros must be instantiat ed manually into your hdl code . the following is an example of clkbuf_lvcmos25 global macro in stantiations that you can copy and paste into your code: vhdl component clkbuf_lvcmos25 port (pad : in std_logic; y : out std_logic); end component begin -- concurrent statements u2 : clkbuf_lvcmos25 port map (pad => ext_clk, y => int_clk); end verilog module design (______); input _____; output ______; clkbuf_lvcmos25 u2 (.y(int_clk), .pad(ext_clk); endmodule using global macros in synplicity the synplify ? synthesis tool automaticall y inserts global buffers for nets with high fanout during synthesis. by default, synplicity ? puts six global macros (clkbuf or clkint) in the netlist, including any global instantiation or pll ma cro. synplify always honors your global macro instantiation. if you have a pll (only primary output is used) in the design, synplify adds five more global buffers in the netlist. synplify uses the following global counting rule to add global macros in the netlist: 1. clkbuf: 1 global buffer 2. clkint: 1 global buffer 3. clkdly: 1 global buffer 4. pll: 1 to 3 global buffers ? gla, glb, glc, yb, and yc are counted as 1 buffer. ? glb or yb is used or bo th are counted as 1 buffer. ? glc or yc is used or bo th are counted as 1 buffer. clkbuf_gtlp25 gtl+ clock buffer with 2.5 v cmos voltage level 1 clkbuf_gtlp33 gtl+ clock buffer with 3.3 v cmos voltage level 1 clkbuf_ hstl _i hstl class i clock buffer 1 clkbuf_ hstl _ii hstl class ii clock buffer 1 clkbuf_sstl2_i sstl2 class i clock buffer 1 clkbuf_sstl2_ii sstl2 cl ass ii clock buffer 1 clkbuf_sstl3_i sstl3 class i clock buffer 1 clkbuf_sstl3_ii sstl3 cl ass ii clock buffer 1 table 3-7 ? i/o standards within clkbuf (continued) name description notes: 1. supported in only the iglooe and proasic3e devices 2. by default, the clkbuf macro uses the 3.3 v lvttl i/o technology. global resources in actel low-power flash devices v1.1 3-13 you can use the syn_global_buffers attribute in synplify to specify a ma ximum number of global macros to be inserted in the netlist. this can also be used to restrict the number of global buffers inserted. in the synplicity 8.1 version, a new attr ibute, syn_global_minfanout, has been added for low-power flash devices. this enables you to promote only the high-fanout signal to global. however, be aware that you can only have six signals assigned to chip global networks, and the rest of the global signals should be assigned to qu adrant global networks. so, if the netlist has 18 global macros, the remaining 12 global macros should have fanout that allows the instances driven by these globals to be placed inside a quadrant. global promotion and demotion using pdc the hdl source file or schematic is the pref erred place for defining which signals should be assigned to a clock network using clock macro instan tiation. this method is preferred because it is guaranteed to be honored by the synthesis tool s and designer software and stop any replication on this net by the synthesis tool. note that a signal with fanout ma y have logic replication if it is not promoted to global during synthesis. in th at case, the user cannot promote that signal to global using pdc. see synplicity help for details on using this attribute. to help you with global management, designer allows you to promote a si gnal to a global network or demote a global macro to a regular macro from th e user netlist using the compile options and/or pdc commands. the following are the pdc constr aints you can use to promote a signal to a global network: 1. pdc syntax to promote a regula r net to a chip global clock: assign_global_clock ?net netname the following will happen during promotion of a regular signal to a global network: ? if the net is external, the net will be dr iven by a clkint in serted automatically by compile. ? the i/o macro will not be changed to clkbuf macros. ? if the net is an internal net, the net will be driven by a clkint inserted automatically by compile. 2. pdc syntax to promote a net to a quadrant clock: assign_local_clock ?net netname ?type quadrant ur|ul|lr|ll this follows the same rule as the chip global clock network. the following pdc comma nd demotes the clock nets to regular nets. unassign_global_clock -net netname note: oavdivrst exis ts only in the fusion pll. figure 3-8 ? plls in low-powe r flash devices c lka g la extfb powerdown oadivr s t lo c k g lb yb g l c y c global resources in actel low-power flash devices 3-14 v1.1 the following will happen during demotion of a global signal to regular nets: ? clkbuf_x becomes inbuf_x; clkint is removed from the netlist. ? the essential global macro, su ch as the output of the clock conditioning circuit, cannot be demoted. ? no automatic buffering will happen. since no automatic buffering happens when a signal is demoted, this net may have a high delay due to large fanout. this may have a negative effect on the quality of the results. actel recommends that the automatic gl obal demotion only be used on small-fanout nets. use clock networks for high-fanout nets to improve timing and routability. spine assignment the low-power flash device archit ecture allows the global networks to be segmented and used as clock spines. these spines, also ca lled local clocks, enable the use of pdc or mvn to assign a signal to a spine. pdc syntax to promote a net to a spine/local clock: assign_local_clock ?net netname ?type [quadrant|chip] tn|bn|tn:bm if the net is driven by a clock macro, designer automatically demotes the cl ock net to a regular net before it is assigned to a spine. nets driven by a pll or clkdly ma cro cannot be assigned to a local clock. when assigning a signal to a sp ine or quadrant global networ k using pdc (pre-compile), the designer software will legalize the shared in stances. the number of shared instances to be legalized can be controlled by compile options . if these networks are created in mvn (only quadrant globals can be created), no legalization is done (as it is post-compile). designer does not do legalization between non-clock nets. as an example, consider two nets, net_clk and net_reset, driving the same flip-flop. the following pdc constraints are used: assign_local_clock ?net net_clk ?type chip t3 assign_local_clock ?net net_reset ?type chip t1:t2 during compile, designer adds a bu ffer in the reset net and places it in the t1 or t2 region, and places the flip-flop in the t3 spine region ( figure 3-9 ). figure 3-9 ? adding a buffer fo r shared instances d clk clr net_clk net_reset t1 t2 t3 d clk clr net_clk net_reset assign_local_clock -net net_clk -type chip t3 assi g n_local_clock -net net_reset -t yp e chi p t1:t2 before compile after compile added buffer global resources in actel low-power flash devices v1.1 3-15 you can control the maximum numb er of shared instances allowe d for the legalization to take place using the compile option dialog box shown in figure 3-10 . refer to libero ide / designer online help for details on the co mpile option dialog box. a large number of shared instances most likely indicates a floorplanning problem that you should address. designer flow for global assignment to achieve the desired result, pay special attention to global management during synthesis and place-and-route. the current synplify tool does no t insert more than six global buffers in the netlist by default. thus, the default flow will not assi gn any signal to the qu adrant global network. however, you can use attributes in synplify and in crease the default glob al macro assignment in the netlist. designer v6.2 suppo rts automatic quadrant global a ssignment, which was not available in designer v6.1. layout will ma ke the choice to assign the correct signals to global. however, you can also utilize pdc and perform manual global assignment to overwrite any automatic assignment. the following step-by-step suggestions guide you in the layout of your design and help you improve timing in designer: 1. run compile and check the compile report. th e compile report has global information in the "device utilization" section that describe s the number of chip and quadrant signals in the design. a "net report" section describes chip global nets, quadrant global nets, local clock nets, a list of nets listed by fanout, and net candidates for local clock assignment. review this information. note that yb or yc are counted as global on ly when they are used in isolation; if you use yb only and not glb, this net is not shown in the global/quadrant nets report. instead, it appears in the global utilization report. 2. if some signals have a very high fanout and are candidates for global promotion, promote those signals to global using the compile options or pdc commands. figure 3-11 on page 3-16 shows the globals management section of the compile options. select promote regular nets whose fanout is greater than and enter a reasonable value for fanouts. figure 3-10 ? shared instances in the co mpile option dialog box global resources in actel low-power flash devices 3-16 v1.1 3. occasionally, the synthesis tool assigns a global macro to cloc k nets, even though the fanout is significantly less than othe r asynchronous signals. select demote global nets whose fanout is less than and enter a reasonable value for fa nouts. this frees up some global networks from the signals that have very lo w fanouts. this can also be done using pdc. 4. use local clocks for the signals that do not need to go to the whole chip but should have low skew. this local clocks assignme nt can only be done using pdc. 5. assign the i/o buffer using mvn if you have fixed i/o assignment. as shown in figure 3-6 on page 3-8 , there are three sets of global pins th at have a hardwired connection to each global network. do not try to put multiple clkbuf macros in these three sets of global pins. for example, do not assign two clkbufs to gaa0x and gaa2x pins. 6. you must click commit at the end of mvn assignment. this runs the pre-layout checker and checks the validity of global assignment. 7. always run co mpile with the keep existing physi cal constraints option on. this uses the quadrant clock network assignment in the mv n assignment and checks if you have the desired signals on the global networks. 8. run layout and check the timing. figure 3-11 ? globals management gui in designer global resources in actel low-power flash devices v1.1 3-17 simple design example consider a design consisting of six building blocks (shift regi sters) and targeted for an a3pe600- pq208 ( figure 3-9 on page 3-14 ). the example design consists of two plls (pll1 has gla only; pll2 has both gla and glb), a global reset (aclr), an enable (en_all), an d three external clock domains (qclk1, qclk2, and qclk3) driving the di fferent blocks of the design. note that the pq208 package only has two plls (which access the chip global network). because of fanout, the global reset and enable signals need to be assigned to the chip global resources. there is only one free chip global for the remaining global (qclk1, qclk2, qclk3). pl ace two of these signals on the quadrant global resource. the design example de monstrates manually a ssignment of qclk1 and qclk2 to the quadrant glob al using the pdc command. figure 3-12 ? block diagram of the global management example design reg256_behave reg_pllclk2gla_out reg_qclk1_out reg_qclk2_out reg_pllclk2glb_out reg_qclk3_out reg_pllclk1_out reg_pllclk2gla pdown pllz_clka data_qclk1 data_pllcqclk2 en_all qclk1 data_qclk2 qclk2 aclr data_qclk3 data_pllclk1 pll1_clka qclk3 shhl_in shhl_in adr clock shhl_out reg_qclk1 reg_qclk2 reg_pllclk2glb reg_qclk3 reg_pllclk1 pll1 \$115 power-down clka lock gla power-down clka lock gla glb pll2 \$116 reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out reg256_behave shhl_in shhl_in adr clock shhl_out global resources in actel low-power flash devices 3-18 v1.1 step 1 run synthesis with default options. the synplicity log shows the following device utilization: step 2 run compile with the promote regular nets whose fanout is greater than option selected in designer; you will see the following in the compile report: device utilization report: ========================== core used: 1536 total: 13824 (11.11%) io (w/ clocks) used: 19 total: 147 (12.93%) differential io used: 0 total: 65 (0.00%) global used: 8 total: 18 (44.44%) pll used: 2 total: 2 (100.00%) ram/fifo used: 0 total: 24 (0.00%) flashrom used: 0 total: 1 (0.00%) ???????? the following nets have been assigned to a global resource: fanout type name -------------------------- 1536 int_net net : en_all_c driver: en_all_pad_clkint source: auto promoted 1536 set/reset_net net : aclr_c driver: aclr_pad_clkint source: auto promoted 256 clk_net net : qclk1_c driver: qclk1_pad_clkint source: auto promoted 256 clk_net net : qclk2_c driver: qclk2_pad_clkint source: auto promoted 256 clk_net net : qclk3_c driver: qclk3_pad_clkint source: auto promoted 256 clk_net net : $1n14 driver: $1i5/core source: essential 256 clk_net net : $1n12 driver: $1i6/core source: essential 256 clk_net net : $1n10 driver: $1i6/core source: essential designer will promote five more signals to global due to high fanout. there are eight signals assigned to global networks. cell usage: cell count area count*area dfn1e1c1 buff inbuf vcc gnd outbuf clkbuf pll total 1536 278 10 9 9 6 3 2 1853 2.0 1.0 0.0 0.0 0.0 0.0 0.0 0.0 3072.0 278.0 0.0 0.0 0.0 0.0 0.0 0.0 3350.0 global resources in actel low-power flash devices v1.1 3-19 during layout, designer will assign two of the signals to quadrant global locations. step 3 (optional) you can also assign the qclk1_c and qclk2_c ne ts to quadrant regions using the following pdc commands: assign_local_clock ?net qclk1_c ?type quadrant ul assign_local_clock ?net qclk2_c ?type quadrant ll step 4 import this pdc with the netlist and run compile again. you will see the following in the compile report: the following nets have been assigned to a global resource: fanout type name -------------------------- 1536 int_net net : en_all_c driver: en_all_pad_clkint source: auto promoted 1536 set/reset_net net : aclr_c driver: aclr_pad_clkint source: auto promoted 256 clk_net net : qclk3_c driver: qclk3_pad_clkint source: auto promoted 256 clk_net net : $1n14 driver: $1i5/core source: essential 256 clk_net net : $1n12 driver: $1i6/core source: essential 256 clk_net net : $1n10 driver: $1i6/core source: essential the following nets have been assigned to a quadrant clock resource using pdc: fanout type name -------------------------- 256 clk_net net : qclk1_c driver: qclk1_pad_clkint region: quadrant_ul 256 clk_net net : qclk2_c driver: qclk2_pad_clkint region: quadrant_ll step 5 run layout. global management in pll design this section describes the legal global network co nnections to plls in th e low-power flash devices. for detailed information on using plls, refer to clock conditioning circuits in igloo and proasic3 devices . actel recommends that you use the dedicated gl obal pins to directly drive the reference clock input of the associated pll for reduced propagation delays and clock distortion. however, low-power flash devices offer the fl exibility to connect other signal s to reference clock inputs. each pll is associated with three global networks ( figure 3-7 on page 3-9 ). there are some limitations, such as when trying to use the global and pll at the same time: ? if you use a pll with only primary output, you can still use the remaining two free global networks. ? if you use three globals associ ated with a pll location, yo u cannot use the pll on that location. ? if the yb or yc output is used standalone, it will occupy one global, even though this signal does not go to the global network. global resources in actel low-power flash devices 3-20 v1.1 using spines of occ upied global networks when a signal is assigned to a global network, the flash switches are programmed to set the mux select lines (explained in the "clock aggregation architecture" section on page 3-8 ) to drive the spines of that network wi th the global net. however, if the global net is restricted from reaching into the scope of a spine, the mux drivers of that spine are available for other high-fanout or critical signals ( figure 3-13 ). for example, if you want to limit the clk1_c signal to the left half of th e chip and want use the right side of the same global network for clk2_c, you can add the following pdc commands: define_region -name region1 -type inclusive 0 0 34 29 assign_net_macros region1 clk1_c assign_local_clock ?net clk2_c ?type chip b2 conclusion igloo, fusion, an d proasic3 devices contain 18 global ne tworks: 6 chip glob al networks and 12 quadrant global networks . these global networks can be se gmented into loca l low-skew networks called spines. the sp ines provide low-skew networks for the high-fanout signals of a design. these allow you up to 252 different internal/externa l clocks in an a3pe3000 device. this document describes the architecture for the global network, plus guidelines and methodologies in assigning signals to globals and spines. figure 3-13 ? design example using spines of occupied global networks global resources in actel low-power flash devices v1.1 3-21 related documents handbook documents clock conditioning circuits in igloo and proasic3 devices http://www.actel.com /lpd_ccc_hbs.pdf i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in iglo oe and proasic3e device s http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf user?s guides igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-005-1 revised march 2008 global resources in actel low-power flash devices 3-22 v1.1 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the "global architecture" section was updated to include the igloo plus family. the bullet was revised to incl ude that the west ccc does not contain a pll core in 15 k and 30 k devices. instances of "a3p030 and agl030 devices" were replaced with "15 k and 30 k gate devices." 3-1 table 3-1 low-power flash families and the accompanying text was updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 3-2 the "versanet global networ k distribution" section , "spine architecture" section , the note in figure 3-1 overview of ve rsanet global network and device architecture , and the note in figure 3-2 simplified versanet global network were updated to include mention of 15 k gate devices. 3-3 , 3-4 table 3-2 globals/spines/rows fo r igloo and proasic3 devices was updated to add the a3p015 device, and to revise the values for clock trees, globals/spines per tree, and globals/spines per device for the a3p030 and agl030 devices. 3-5 table 3-3 globals/spines/rows for igloo plus devices is new. 3-5 clkbuf_lvcmos12 was added to table 3-7 i/o standards within clkbuf . 3-11 the "handbook documents" section was updated to include the three different i/o structures chapters for proasic3 and igloo device families. 3-21 51900087-1/3.05 figure 3-2 simplified versanet global network was updated. 3-4 the "naming of global i/os" section was updated. 3-9 the "using global macros in synplicity" section was updated. 3-12 the "global promotion and demotion using pdc" section was updated. 3-13 the "designer flow for glob al assignment" section was updated. 3-15 the "simple design example" section was updated. 3-17 51900087-0/1.05 table 3-2 globals/spines/rows fo r igloo and proasic3 devices was updated. 3-5 v1.1 4-1 clock conditioning circuits in igloo and proasic3 devices 4 ? clock conditioning circuits in igloo and proasic3 devices introduction this document outlines the following device in formation: ccc features, pll core specifications, functional descri ptions, software configuration info rmation, detailed usage information, recommended board-level considerations, and other considerations concerning clock conditioning circuits and global networks in low-power flash devices. overview of clock conditioning circuitry in igloo ? and proasic ? 3 devices, the cccs are used to implement frequency division, frequency multiplication, phase shifting, and delay operations . the cccs are available in six chip locations? each of the four chip corners and the middle of the east and west chip sides. for device-specific variations, refer to the "device-specific layout" section on page 4-13 . the ccc is composed of the following: ? pll core ? 3 phase selectors ? 6 programmable delays and 1 fixe d delay that advances/delays phase ? 5 programmable frequency dividers that provide frequency multiplication/division (not shown in figure 4-5 on page 4-8 because they are automatically configured based on the user's required frequencies) ? 1 dynamic shift register that provides ccc dynamic reconfiguration capability figure 4-1 provides a simplified block diagram of th e physical implementation of the building blocks in each of the cccs. each ccc can implement up to three independent global buffers (with or without programmable delay) or a pll function (programmable frequency division/multiplication, phase shift, and delays) figure 4-1 ? overview of the cccs offe red in igloo and proasic3 3 global i/os clka clkb clkc to global network a to global network b to global network c from core to core ccc function block (with or without pll) multiplexer tree 3 global i/os 3 global i/os to core to core from core from core multiple signals single signals clock conditioning circuits in igloo and proasic3 devices 4-2 v1.1 with up to three global outputs. unused global outputs of a pll can be used to implement independent global buffers, up to a maximu m of three global ou tputs for a given ccc. ccc programming the ccc block is fully configurab le, either via flash configurat ion bits set in the programming bitstream or through an asynch ronous interface. this asynchro nous dedicated shift register interface is dynamically accessible from inside the low-power flash devices to permit parameter changes, such as pll divide ratios and delays, during device operation. to increase the versatility and flexibility of the clock conditioning system, the ccc configuration is determined either by th e user during the design process, with configuration data being stored in flash memory as part of the devi ce programming procedure, or by writing data into a dedicated shift register during normal device operation. this latter mode allows the user to dynamically reconfigur e the ccc without the need for core programming. the shift register is accessed th rough a simple serial interface. refer to ujtag applications in actel?s low-power flash devices . global resources low-power flash devices provide three global routing networks (gla, glb, and glc) for each of the ccc locations. there are potentially many i/o lo cations; each global i/o location can be chosen from only one of three possibilit ies. this is controlled by the multiplexer tree circuitry in each global network. once the i/o location is selected , the user has the option to utilize the cccs before the signals are connected to the gl obal networks. the ccc in each location (up to six) has the same structure, so generating the ccc ma cros is always done with an identical software gui. the cccs in the corner locations drive the qu adrant global networks, and the cccs in the middle of the east and west locations drive the chip global networks. the quadrant global networks span only a quarter of the device, while the chip global netw orks span the entire device. for more details on global resources offered in lo w-power flash devices, refer to global resources in actel low-power flash devices . a global buffer can be placed in any of the three global locations (clka-gla, clkb-glb, or clkc-glc) of a given ccc. a pll macro uses the clka ccc input to drive its reference clock. it uses the gla and, optionally, the glb and glc global outputs to drive the global networks. a pll macro can also drive the yb and yc regular core outputs. the glb (or glc) global output cannot be reused if the yb (or yc) ou tput is used. refer to the "pll macro signal descriptions" section on page 4-7 for more information. each global buffer, as well as the pll reference cl ock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core clock conditioning circuits in igloo and proasic3 devices v1.1 4-3 ccc support in low-power devices the low-power flash families listed in table 4-1 support the ccc feature and the functions described in this document. actel's low-power flas h devices (listed in table 4-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 4-1 . where the information applies to only one fami ly or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 4-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 4-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze technology and enhanced i/o capabilities. igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1.2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher de nsity, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fpgas qualified for automotive applications automotive proasic3 dc and switching characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. clock conditioning circuits in igloo and proasic3 devices 4-4 v1.1 global buffers with no programmable delays access to the global / quadrant global networks can be configured directly from the global i/o buffer, bypassing the ccc functional block (as indicated by the dotted lines in figure 4-2 ). internal signals driven by the fpga core can use the global / quadrant global networks by connecting via the routed clock input of the multiplexer tree. there are many specific clkbuf macros supporting the wide variety of single-ended i/o inputs (clkbuf) and differential i/o standards (clkbuf_ lvds/lvpecl) in the lo w-power flash families. they are used when connecti ng global i/os directly to the global/quadrant networks. when an internal signal needs to be connected to the global/quadrant network, the clkint macro is used to connect the sign al to the routed clock inpu t of the network's mux tree. to utilize direct connection from global i/os or from internal signals to the global/quadrant networks, clkbuf, clkbuf_lvpecl/lvds, and clkint macros are used. ? the clkbuf and clkbuf_lvpecl/lvds/blvds /m-lvds macros are composite macros that include an i/o macro driving a global bu ffer, which uses a hardwired connection. ? the clkbuf, clkbuf_lvpecl/lvds/blvds/m-l vds, and clkint macros are pass-through clock sources and do not use the pll or pr ovide any programmable delay functionality. ? the clkint macro provides a global buffer function driven internally by the fpga core. the available clkbuf macros are described in the igloo, fusion, and proa sic3 macro library guide . global buffer with programmable delay clocks requiring clock adjustments can utilize th e programmable delay cores before connecting to the global / quadrant global netw orks. a maximum of 18 ccc global buffers can be instantiated in a device?three per ccc times up to six cccs per device. each ccc functional block contains a programmable delay element for each of the global networks (up to three). note: the clkdly macro uses progra mmable delay element type 2. figure 4-2 ? ccc options: global buffers with no programmable delay none clkbuf_lvds/lvpecl macro padn padp yy a pad y clkint macro clkbuf macro gla or glb or glc clock source clock conditioning output clock conditioning circuits in igloo and proasic3 devices v1.1 4-5 the clkdly macro is a pass-through clock source th at does not use the pll, but provides the ability to delay the clock input using a programmable delay. the clkdly macro takes the selected clock input and adds a user-defined de lay element. this macro generate s an output clock phase shift from the in put clock. the clkdly macro can be driven by an inbuf* macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedica ted global i/o locations. many specific inbuf macros support the wide variety of single-ended and differential i/o standards supported by the low-power flash family. the available inbuf macros are described in the igloo, fusion, and proasic3 macro library guide . the clkdly macro can be driven directly from th e fpga core. the clkdly macro can also be driven from an i/o that is routed through the fpga re gular routing fabric. in this case, users must instantiate a special macro, pllint, to differenti ate from the hardwired i/ o connection described earlier. the visual clkdly configuration in th e smartgen part of the actel libero ? integrated design environment (ide) and designer to ols allows the user to select the desired amount of delay and configures the delay elem ents appropriately. smartgen also a llows the user to select the input clock source. smartgen will automatically instan tiate the special macro, pllint, when needed. clkdly macro signal descriptions the clkdly macro supports one input and on e output. each signal is described in table 4-2 . clkdly macro usage when a clkdly macro is used in a ccc location, the programmable delay element is used to allow the clock delays to go to the gl obal network. in addition, the user can bypass the pll in a ccc location integrated with a pll, but use the prog rammable delay that is as sociated with the global network by instantiating the clkdly macro. the same is true when using programmable delay elements in a ccc location with no plls (the us er needs to instantiate the clkdly macro). there is no difference between the programmable delay el ements used for the pll and the clkdly macro. note: for inbuf* driving a pll macro or clkd ly macro, the i/o will be hard-routed to the ccc; i.e., will be placed by software to a dedicated global i/o. figure 4-3 ? ccc options: global buffers with programmable delay padn padp y pad y input lvds/lvpecl macro inbuf* macro gla or glb or glc clock source clock conditioning output clk dlygl[4:0] gl table 4-2 ? input and output description of the clkdly macro signal name i/o description clk reference clock input reference clock input for pll core input clock for primary output clock, gla gl global output output primary output clock to respective global/quadrant clock networks clock conditioning circuits in igloo and proasic3 devices 4-6 v1.1 the ccc will be configured to use the programma ble delay elements in accordance with the macro instantiated by the user. as an example, if the pll is not used in a partic ular ccc location, the desi gner is free to specify up to three clkdly macros in the ccc, each of wh ich can have its own input frequency and delay adjustment options. if the pll core is used, assuming output to only one global clock network, the other two global clock networks are free to be us ed by either connecting directly from the global inputs or connecting from one or two clkdly macros for programmable delay. the programmable delay elements are shown in the block diagram of the pll block shown in figure 4-5 on page 4-8 . note that any ccc locations with no pll present contain only the programmable delay blocks going to the global networks (labeled "prog rammable delay type 2"). refer to the "clock delay adjustment" section on page 4-19 for a description of the programmable delay types used for the pll. also refer to table 4-13 on page 4-24 for programmable delay type 1 step delay values, and table 4-14 on page 4-25 for programmable delay type 2 step delay values. ccc locations with a pll present can be configured to utilize only the programmable delay blocks (programmable delay type 2) going to the global networks a, b, and c. global network a can be configured to use only the programmable delay element (bypassing the pll) if the pll is not used in the design. figure 4-5 on page 4-8 shows a block diagram of the pll, where the programmable delay elements are used for the global networks (programmable delay type 2). global buffers with pll function clocks requiring frequency sy nthesis or clock adjustments ca n utilize the pll core before connecting to the global / quadrant global networks. a maximum of 18 ccc global buffers can be instantiated in a device?three per ccc times up to six cccs per device. ea ch pll core can generate up to three global/quadrant clocks, while a clock delay element provides one. the pll functionality of the clock conditio ning block is supported by the pll macro . the pll macro provides five deri ved clocks (three independent) from a single reference clock. the pll macro also provides power-down input and lo ck output signals. the additional inputs shown note: refer to the igloo, fusion, and proasi c3 macro library guide for more information. figure 4-4 ? ccc options: global buffers with pll padn padp y pad y input lvds/lvpecl macro pll macro inbuf* macro gla or gla and (glb or yb) or gla and (glc or yc) or gla and (glb or yb) and (glc or yc) clock source clock conditioning output for inbuf* driving a pll macro or clkdly macro, the i/o will be hard-routed to the ccc; i.e., will be placed by software to a dedicated global i/o. oadiv[4:0]* oamux[2:0]* dlygla[4:0]* obdiv[4:0]* obmux[2:0]* dlyyb[4:0]* dlyglb[4:0]* ocdiv[4:0]* ocmux[2:0]* dlyyc[4:0]* dlyglc[4:0]* findiv[6:0]* fbdiv[6:0]* fbdly[4:0]* fbsel[1:0]* xdlysel* vcosel[2:0]* clka extfb gla lock glb yb glc yc powerdown clock conditioning circuits in igloo and proasic3 devices v1.1 4-7 on the macro are configuration settings, which are configured through the use of smartgen. for manual setting of these bits refer to the igloo, fusion, and proasi c3 macro library guide for details. figure 4-5 on page 4-8 illustrates the variou s clock output options and delay elements. pll macro signal descriptions the pll macro supports two in puts and up to six outputs. table 4-3 gives a description of each signal. input clock as discussed above, the inputs to the input reference clock (clka) of the pll can come from global input pins, regular i/o pins, or internally from the core. global output clocks gla (primary), glb (secondary 1) , and glc (secondary 2) are the outputs of global multiplexer 1, global multiplexer 2, and global multiplexer 3, respectively. these signal s (glx) can be used to drive the high-speed global and quadrant networks of the low-power flash devices. a global multiplexer block consists of the input ro uting for selecting the in put signal for the glx clock and the output mu ltiplexer, as well as delay elements associated with that clock. core output clocks yb and yc are known as core outputs and can be used to drive internal logic without using global network resources. this is especially helpful when global network resources must be conserved and utilized for other timing-critical paths. yb and yc are identical to glb and glc, respec tively, with the possible exception of a higher selectable final output delay. the smartgen p ll wizard will configure these outputs according to user specifications and can enable these signals with or without the enabling of global output clocks. the above signals can be enabled in the following output groupings in both internal and external feedback configurati ons of the static pll: ? one output ? gla only ? two outputs ? gla + (glb and/or yb) ? three outputs ? gla + (glb an d/or yb) + (glc and/or yc) table 4-3 ? input and output signals of the pll block signal name i/o description clka reference clock input reference clock in put for pll core; input clock for primary output clock, gla extfb external feedback input allows an external signal to be co mpared to a reference clock in the pll core's phase detector powerdown power down input active low input that selects power-down mode and disables the pll. with the powerdown signal asserted, the pll core sends 0 v signals on all of the outputs. gla primary output output prim ary output clock to respective global/quadrant clock networks glb secondary 1 output output secondary 1 output clock to respective global/quadrant clock networks yb core 1 output output core 1 output clock to local routing network glc secondary 2 output output secondary 2 output clock to respective global/quadrant clock networks yc core 2 output output core 2 output clock to local routing network lock pll lock indicator output active-high signa l indicating that steady-state lock has been achieved between clka and the pll feedback signal clock conditioning circuits in igloo and proasic3 devices 4-8 v1.1 pll macro block diagram as illustrated, the pll supports three distinct output frequencies from a given input clock. two of these (glb and glc) can be routed to the b an d c global network acce ss, respectively, and/or routed to the device core (yb and yc). there are five delay elements to support phase con trol on all five outputs (gla, glb, glc, yb, and yc). there is also a delay element in the feedback loop that can be used to advance the clock relative to the reference clock. the pll macro reference clock can be driven by an inbuf* macro to create a composite macro, where the i/o macro drives the global buffer (with programmable delay) using a hardwired connection. in this case, the i/o must be placed in one of the dedicated global i/o locations. the pll macro reference clock can be driven directly from the fpga core. the pll macro reference clock can also be driven from an i/o that is routed through the fpga regular routing fabric. in this case, users must insta ntiate a special macro, pllint, to differentiate from the hardwired i/o conn ection described earlier. during power-up, the pll output s will toggle around the maxi mum frequency of the voltage- controlled oscillator (vco) gear selected. toggl e frequencies can range from 40 mhz to 250 mhz. this will continue as long as the clock input (clka) is constant (high or low). this can be prevented by low assertion of the powerdown signal. the visual pll configuratio n in smartgen, part of the libero id e and designer tools, will derive the necessary internal divider ratios based on th e input frequency and desired output frequencies selected by the user. smartgen also allows the user to select the variou s delays and phase shift values necessary to adjust the phases between the reference cl ock (clka) and the derived clocks (gla, glb, glc, yb, and yc). smartgen also allows the user to select the inpu t clock source. smartgen automatically instantiates the special macro, pllint, when needed. note: clock divider and clock multiplier blocks are not shown in this figure or in smartgen. they are automatically configured based on the user's required frequencies. figure 4-5 ? ccc with pll block pll core phase select phase select phase select gla clka glb yb glc yc fixed delay programmable delay type 1 programmable delay type 2 programmable delay type 2 programmable delay type 1 programmable delay type 2 programmable delay type 1 four-phase output extfb clock conditioning circuits in igloo and proasic3 devices v1.1 4-9 global input selections low-power flash devices provide the flexibility of choosing one of the three global input pad locations available to conn ect to a ccc functional block or to a global / quadrant global network. figure 4-6 shows the detailed architecture of each gl obal input structure. if the single-ended i/o standard is chosen, there is flexibility to choose one of the glob al input pads (the first, second, and fourth input). once chosen, the ot her i/o locations are used as regu lar i/os. if the differential i/o standard is chosen, the first and second inputs are considered as paired, and the third input is paired with a regular i/o. the user then has the choice of selecting one of th e two sets to be used as the clock input source to the ccc functional block. there is also the option to allow an internal clock signal to feed the global network or the ccc functional block. a multiplexer tree selects the appropriate global input for routing to the desired location . note that the global i/o pads do not need to feed the global network; they can also be used as regular i/o pads. each global buffer, as well as the pll reference cl ock, can be driven from one of the following: ? 3 dedicated single-ended i/os using a hardwired connection ? 2 dedicated differential i/os using a hardwired connection ? the fpga core notes: 1. represents the global input pins. globals have direct access to the clock conditioning block and are not routed via the fpga fabric. refer to user i/o naming conventions in i/o structures in igloo and proasic3 devices . 2. instantiate the routed cloc k source input as follows: a) connect the output of a logic element to the clock input of a pll, clkdly, or clkint macro. b) do not place a clock source i/ o (inbuf or inbuf_lvpecl/lvds/blvds/ m-lvds/ddr) in a relevant global pin location. figure 4-6 ? clock input sources including clkbuf, clkbuf_lvds/lvpecl, and clkint + + source for ccc (clka or clkb or clkc) each shaded box represents an inbuf or inbuf_lvds/lvpecl macro, as appropriate. to core routed clock (from fpga core) sample pin names gaa0/io0ndb0v0 1 gaa1/io00pdb0v0 1 gaa2/io13pdb7v1 1 gaa[0:2]: ga represents global in the northwest corner of the device. a[0:2]: designates specific a clock source. 2 clock conditioning circuits in igloo and proasic3 devices 4-10 v1.1 since the architecture of the devi ces varies as size increases, th e following list details i/o types supported for globals: ? lvds-, blvds-, and m-lvds?based clock sources are only available on 250 k gate devices and above. ? 65 k and 125 k gate devices suppo rt single-ended clock sources only. ? 15 k and 30 k gate devices support these in puts for ccc only and do not contain a pll. clock sources for p ll and clkdly macros the input reference clock (clka for a pll macro, clk for a clkdly macro) can be accessed from different sources via the associated clock multiple xer tree. each ccc has the option of choosing the source of the input clock from one of the following: ? hardwired i/o ? external i/o ? core logic the smartgen macro builder tool al lows users to easily create the pll and clkdly macros with the desired settings. it is strongly recommended that smartgen be us ed to generate the ccc macros. hardwired i/o clock source hardwired i/o refers to global inpu t pins that are hardwired to th e multiplexer tree, which directly accesses the ccc global buffers. these global input pins have designated pin locations and are indicated with the i/o naming convention gmn ( m refers to any one of the positions where the pll core is available, and n refers to any one of the three glob al input muxes and the pin number of the associated global location, m ). choosing this option provides the benefit of directly connecting to the ccc reference clock input, which provides less delay. see figure 4-7 for an example illustration of the connections, shown in red. if a clkdly macro is initiated to utilize the programmable delay element of the ccc, the clock input can be placed at one of nine dedicated global input pin locations. in other words, if ha rdwired i/o is chosen as the input source, the user can decide to place the input pin in one of the gma0, gma1, gma2, gmb0, gmb1, gmb2, gmc0, gmc1, or gmc2 locations of the low-power flash de vices. when a pll macro is used to utilize the pll core in a ccc location, the clock input of th e pll can only be connected to one of three gma* global pin locations: gma0, gma1, or gma2. figure 4-7 ? illustration of hardwired i/o (global input pins) usage + _ pll or clkdly macro routed clock (from fpga core) gmn0 gmn1 gmn2 to core to global (or local) routing network clka pllint multiplexer tree + _ iouxwbyvz gmn* = global input pin iouxwbyvz = regular i/o pin clock conditioning circuits in igloo and proasic3 devices v1.1 4-11 external i/o clock source external i/o refers to regular i/o pins. the clock source is instantiated with one of the various inbuf options and accesses th e cccs via internal routing. the user has the option of assigning this input to any of the i/os labeled with the i/o convention iouxwbyvz . refer to user i/o naming conventions in i/o structures in igloo and proasic3 devices for more information. figure 4-8 gives a brief explanation of external i/o usage. choosing this option provides the freedom of selecting any user i/o location but introduces additional delay because the signal connects to the routed clock input through internal ro uting before connecting to the ccc reference clock input. for the external i/o opti on, the routed signal would be instan tiated with a pllint macro before connecting to the ccc reference cl ock input. this instantiation is conveniently done automatically by smartgen when this option is selected. usin g the smartgen tool to generate the ccc macro is the recommended approach. the instantiation of the pllint macr o results in the use of the routed clock input of the i/o to connect to the pll clock input. if not us ing smartgen, manually instantiate a pllint macro before the pll reference clock to indicate that the regular i/o driving the pll reference clock should be used (see figure 4-8 for an example illustrati on of the connections, shown in red). in the above two op tions, the clock s ource must be instantiated with one of the various inbuf macros. the reference clock pins of the ccc functional block core macros must be driven by regular input macros (inbufs), no t clock input macros. figure 4-8 ? illustration of external i/o usage pll or clkdly macro routed clock (from fpga core) gmn* gmn* gmn* to core iouxwbyvz* to global (or local) routing network iouxwbyvz* clka pllint multiplexer tree + _ + _ gmn* = global input pin iouxwbyvz = regular i/o pin clock conditioning circuits in igloo and proasic3 devices 4-12 v1.1 core logic clock source core logic refers to internal routed ne ts. internal routed signals ac cess the ccc via the fpga core fabric. similar to the external i/o option, whenever the clock source comes internally from the core itself, the routed signal is instantiated with a pllint macro before conn ecting to the ccc clock input (see figure 4-9 for an example illustration of the connections, shown in red). available i/o standards figure 4-9 ? illustration of core logic usage table 4-4 ? available i/o stan dards within clkbuf and clkbuf_lvds/lvpecl macros clkbuf_lvcmos5 clkbuf_lvcmos33 1 clkbuf_lvcmos25 2 clkbuf_lvcmos18 clkbuf_lvcmos15 clkbuf_pci clkbuf_pcix 2 clkbuf_gtl25 2 clkbuf_gtl33 2 clkbuf_gtlp25 2 clkbuf_gtlp33 2 clkbuf_hstl_i 2 clkbuf_hstl_ii 2 clkbuf_sstl3_i 2 clkbuf_sstl3_ii 2 clkbuf_sstl2_i 2 clkbuf_sstl2_ii 2 clkbuf_lvds 3 clkbuf_lvpecl notes: 1. by default, the clkbuf macro uses the 3.3 v lvttl i/o technology. for more details, refer to the igloo, fusion, and proasi c3 macro library guide . 2. i/o standards only supported in proasic3e and iglooe families. 3. blvds and m-lvds standards ar e supported by clkbuf_lvds. pll or clkdly macro routed clock (from fpga core) gmn* gmn* gmn* to core iouxwbyvz* to global (or local) routing network from internal signals clka pllint multiplexer tree _ + _ + gmn* = global input pin iouxwbyvz = regular i/o pin clock conditioning circuits in igloo and proasic3 devices v1.1 4-13 global synthesis constraints the synplify ? synthesis tool, by default, allows six clocks in a design for igloo and proasic3. when more than six clocks are needed in the de sign, a user synthesis constraint attribute, syn_global_buffers, can be used to control the maximum number of clocks (up to 18) that can be inferred by the synthesis engine. high-fanout nets will be inferred with clock buff ers and/or internal cloc k buffers. if the design consists of ccc global buffers, they are incl uded in the count of clocks in the design. the subsections below discuss the clock input source (global buffer s with no programmable delays) and the clock conditioning functional block (global buffers with programmable delays and/or pll function) in detail. device-specific layout two kinds of cccs are offered in low-power flas h devices: cccs with in tegrated plls, and cccs without integrated plls (simplified cccs). table 4-5 lists the number of cc cs in various devices. this document outlines the following device in formation: ccc features, pll core specifications, functional descri ptions, software configuration info rmation, detailed usage information, recommended board-level considerations, and other considerations concerning global networks in low-power flash devices. clock conditioning circuits with integrated plls each of the cccs with integrated plls includes the following: ? 1 pll core, which consists of a phase detector , a low-pass filter, and a four-phase voltage- controlled oscillator ? 3 global multiplexer blocks that steer signals fr om the global pads and the pll core onto the global networks ? 6 programmable delays and 1 fixed de lay for time advanc e/delay adjustments table 4-5 ? number of cccs by device size and package device package cccs with integrated plls cccs without integrated plls (simplified ccc) proasic3/proasic3l igloo/igloo plus a3p015 agl015 all 0 2 a3p030 agl030/aglp030 all 0 2 a3p060 agl060/aglp060 all 1 5 a3p125 agl125/aglp125 all 1 5 a3p250/l agl250 all 1 5 a3p400 all 1 5 a3p600/l agl600 all 1 5 a3p1000/l agl1000 all 1 5 a3pe600 agle600 pq208 2 4 a3pe600 all other packages 60 a3pe1500 pq208 2 4 a3pe1500 all other packages 60 a3pe3000/l pq208 2 4 a3pe3000/l agle3000 all other packages 60 clock conditioning circuits in igloo and proasic3 devices 4-14 v1.1 ? 5 programmable frequency divider blocks to provide frequency synthesis (automatically configured by the smartgen macro builder tool) clock conditioning circuits without integrated plls each of the simplified cccs without integrated plls in the low-power flash families is composed of the following: ? 3 global multiplexer blocks that steer sign als from the global pads and the programmable delay elements onto the global networks ? 3 programmable delay elements to provide time delay adjustments ccc locations cccs located in the middle of the east and west sides of the device access the three versanet global networks on each side (six total networks), while the four cccs located in the four corners access three quadrant global networks (twelve total networks). see figure 4-10 . the following explains the locations of the cccs in igloo and proasic3 devices: in figure 4-13 on page 4-16 through figure 4-14 on page 4-16 , cccs with integrated plls are indicated in red, and simplified cccs are indicated in yellow. there is a letter associated with each location of the ccc, in clockwise order. the uppe r left corner ccc is name d "a," the upper right is named "b," and so on. these names finish up at the middle left with letter "f." igloo and proasi c3 ccc locations in all igloo and proasic3 devices (except 15 k an d 30 k gate devices, which do not contain plls), six cccs are located in the same positions as the iglooe and proasic3e cccs. only one of the cccs has an integrated pll and is locate d in the middle of the west (mid dle left) side of the device. the figure 4-10 ? global network architecture northwest quadrant global networks southeast quadrant global networks chip-wide (main) global networks 3 3 3 333 3 333 6 6 6 6 6 6 6 6 global spine quadrant global spine ccc location a ccc location f ccc location e ccc location d ccc location c ccc location b clock conditioning circuits in igloo and proasic3 devices v1.1 4-15 other five cccs are simplified cc cs and are located in the four co rners and the middle of the east side of the device ( figure 4-11 ). note that the 15 k and 30 k gate de vices do not support pll features. this device has only six global i/o buffers, three each located in the middle of the east and west side s of the device. a ccc functional block is available in each of the two locations, for a total of two cccs. no quadrant global networks are present in th e four corners of this device ( figure 4-12 ). figure 4-11 ? ccc locations in igloo and proasic3 family devices (except 15 k and 30 k gate devices) figure 4-12 ? ccc locations in the 15 k and 30 k gate devices ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 a b c d e f = ccc with integrated pll = simplified ccc with programmable delay elements (no pll) ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 1 bank 1 bank 0 bank 0 bank 1 = simplified ccc with programmable delay elements (no pll) a b c d e f clock conditioning circuits in igloo and proasic3 devices 4-16 v1.1 iglooe and proasic3e ccc locations iglooe and proasic3e devices have six cccs ? one in each of the four corners and one each in the middle of the east and we st sides of the device ( figure 4-13 ). all six cccs are integrated with plls, except in pqfp-208 package devi ces. pqfp-208 package devices also have six cccs, of which two include plls and four are simpli fied cccs. the cccs with plls are implemented in the middle of the east and west (middle right and mi ddle left) sides of the device. the simplified cccs without plls are located in the four corners of the device ( figure 4-14 ). figure 4-13 ? ccc locations in iglooe an d proasic3e family device s (except pqfp-208 package) figure 4-14 ? ccc locations in proasic3e fami ly devices (pqfp-208 package) versatile ram block 4,608-bit dual-port sram or fifo block pro i/os ram block 4,608-bit dual-port sram or fifo block isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps = ccc with integrated pll ccc a b c d e f ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 = ccc with integrated pll = simplified ccc with programmable delay elements (no pll) b c d ccc a e f isp aes decryption* user nonvolatile flashrom flash*freeze technology charge pumps clock conditioning circuits in igloo and proasic3 devices v1.1 4-17 pll core specifications pll core specifications can be found in the dc and switching characte ristics chapter of the appropriate family datasheet. loop bandwidth common design practice fo r systems with a low-noise input cloc k is the need to have plls with small loop bandwidths to reduce the effects of noise sources at the output. table 4-6 shows the pll loop bandwidth, providing a measure of the pll' s ability to track the in put clock and jitter. pll core operating principles this section briefly describes the basic principles of pll operation. the pll core is composed of a phase detector (pd), a low-pass filter (lpf), an d a four-phase voltage-co ntrolled oscillator (vco). figure 4-15 illustrates a basic single-phase pll core wi th a divider and delay in the feedback path. the pll is an electronic servo loop that phase-aligns the pd fee dback signal with the reference input. to achieve this, the pll dynamically adjusts the vco output signal according to the average phase difference between the input and feedback signals. the first element is the pd, wh ich produces a voltage proporti onal to the phase difference between its inputs. a simple exam ple of a digital phase detector is an exclusive-or gate. the second element, the lpf, extracts the average voltage from the phas e detector and applies it to the vco. this applied voltage alters the resonant fr equency of the vco, th us adjusting its output frequency. consider figure 4-15 with the feedback path bypassing the divider and delay elements. if the lpf steadily applies a voltage to the vco such that the output freque ncy is identical to the input frequency, this steady-state condition is known as lock. note that the inpu t and output phases are also identical. the pll core sets a lock outp ut signal high to in dicate this condition. should the input frequency increase slightly, the pd detects the frequency/phase difference between its reference and feedback input signals. since the pd output is proportional to the phase difference, the change causes the output from th e lpf to increase. this voltage change increases the resonant frequency of the vco and increase s the feedback frequency as a result. the pll dynamically adjusts in this manner until the pd senses two phase- identical signals and steady-state lock is achieved. the opposite (decreasing pd output signal) occurs wh en the input frequency decreases. table 4-6 ? ?3db frequency of the pll minimum (t a = +125c, v cca = 1.4 v) ty p i c a l (t a = +25c, v cca = 1.5 v) maximum (t a = ? 55c, v cca = 1.6 v) ? 3 db frequency 15 khz 25 khz 45 khz figure 4-15 ? simplified pll core with fe edback divider and delay frequency reference input f in phase detector low-pass filter voltage controlled oscillator divide by m counter delay frequency output m f in clock conditioning circuits in igloo and proasic3 devices 4-18 v1.1 now suppose the feedback divider is inserted in the feedback pa th. as the division factor n is increased, the average phase differ ence increases. the average phas e difference will cause the vco to increase its frequency until th e output signal is ph ase-identical to the input after undergoing division. in other words, lock in both frequency and phase is achieved when the output frequency is m times the input. thus, cl ock division in the feedback path resu lts in multiplication at the output. a similar argument can be made when the delay element is inserted into the feedback path. to achieve steady-state lock, the vco output signal will be delayed by the input period less the feedback delay. for periodic signals, this is equi valent to time-advancing the output clock by the feedback delay. another key parameter of a pll system is the acqu isition time. acquisition time is the amount of time it takes for the pll to ac hieve lock (i.e., phase- align the feedback si gnal with the input reference clock). for example, su ppose there is no voltage applie d to the vco, allowing it to operate at its free-running frequency. should an input reference clock suddenly appear, a lock would be established within the maximum acquisition time. functional description this section provides detailed descriptions of p ll block functionality: clock dividers and multipliers, clock delay adjustment, phase adjustm ent, and dynamic pll configuration. clock dividers and multipliers the pll block contains five programmable dividers. figure 4-16 shows a simplifi ed pll block. figure 4-16 ? pll block diagram pll core clka fixed delay d1 d2 d2 d1 d2 d1 n m u v w gla glb glc primary secondary 1 secondary 2 yb yc system delay output delay feedback delay output delay output delay output delay output delay 270 180 90 0 d1 = programmable delay type 1 d2 = programmable delay type 2 clock conditioning circuits in igloo and proasic3 devices v1.1 4-19 dividers n and m (the input divider and feedback divider, respectively) provide integer frequency division factors from 1 to 128. the output dividers u , v , and w provide integer di vision factors from 1 to 32. frequency scaling of the reference cloc k clka is performed acco rding to the following formulas: f gla = f clka m / (n u) ? gla primary pll output clock eq 4-1 f glb = f yb = f clka m / (n v) ? glb secondary 1 pll output clock(s) eq 4-2 f glc = f yc = f clka m / (n w) ? glc secondary 2 pll output clock(s) eq 4-3 smartgen provides a user-friendl y method of generating the configured pll netlist, which includes automatically setting the division factors to achi eve the closest possible match to the requested frequencies. since the five output clocks share the n and m dividers, the achievable output frequencies are inte rdependent and related accord ing to the foll owing formula: f gla = f glb (v / u) = f glc (w / u) eq 4-4 clock delay adjustment there are a total of seven configurable delay elements implemented in the pll architecture. two of the delays are located in the feedback path, entitled system delay and feedback delay. system delay provides a fixed delay of 2 ns (typical), and feedback delay provides se lectable delay values from 0.6 ns to 5.56 ns in 160 ps increments (typical). for plls, dela ys in the feedback path will effectively advance the output signal from the pll core with respect to the reference clock. thus, the system and feedback delays generate nega tive delay on the output clock. additionally, each of these delays can be independently bypassed if necessary. the remaining five delays perform traditional time delay and are located at each of the outputs of the pll. besides the fixed global driver delay of 0.755 ns for each of the global networks, the global multiplexer outputs (gla, glb, an d glc) each feature an addition al selectable delay value from 0.025 ns to 0.76 ns in the first st ep, and then to 5.56 ns in 160 ps increments. the additional yb and yc signals have access to a selectable delay from 0. 6 ns to 5.56 ns in 160 ps increments (typical). this is the same delay value as the clkdly macro. it is similar to clkdly, which bypasses the pll core just to take advantage of the phase adjustment option wi th the delay value. the following parameters must be taken into consideration to achieve minimum delay at the outputs (gla, glb, glc, yb, and yc) relative to the reference clock: routing delays from the pll core to ccc outputs, core output s and global network output delays, and the feedback path delay. the feedback path delay acts as a time advance of the input clock and will offset any delays introduced beyond the pll core output. the routing delays are determined from back-annotated simulation and are configuration-dependent. phase adjustment the output from the pll core can be phase-adju sted with respect to the reference input clock, clka. the user can select a 0, 90, 180, or 270 phase shift independently for each of the outputs ya, glb/yb, and glc/yc. note that each of these phase-adjusted signals may also undergo further frequency division and/or time adjustment via the remaining dividers and delays located at the outputs of the pll. dynamic pll configuration the cccs can be configured both statically and dynamically. in addition to the ports available in the static ccc, th e dynamic ccc has the dynamic shift register signals that enab le dynamic reconfiguration of the ccc. with the dynamic ccc, the ports clkb and clkc are also exposed. all three clocks (clka, clkb, and cl kc) can be configured independently. clock conditioning circuits in igloo and proasic3 devices 4-20 v1.1 the ccc block is fully configurable. the followin g two sources can act as the ccc configuration bits. flash configuration bits the flash configuration bits are the configuratio n bits associated with pr ogrammed flash switches. these bits are used when the ccc is in static co nfiguration mode. once the device is programmed, these bits cannot be modifi ed. they provide the default operating state of the ccc. dynamic shift register outputs this source does not require core reprog ramming and allows core-driven dynamic ccc reconfiguration. when the dynamic register drives the configuration bits, the user-defined core circuit takes full control over sdin, sdout, sclk , sshift, and supdate. the configuration bits can consequently be dynamically changed through shift and update operations in the serial register interface. access to the logic core is accomplished via the dynamic bi ts in the specific tiles assigned to the plls. figure 4-17 illustrates a simplified block diagram of the mux ar chitecture in the cccs. the selection between the flash configuration bits and the bits from the co nfiguration register is made using the mode signal shown in figure 4-17 . if the mode signal is logic high, the dynamic shift register configuration bits are selected. there are 81 control bits to configure the different functions of the ccc. each group of control bits is assigned a specific lo cation in the configuration shift register. for a list of the 81 configuration bits (c[80:0]) in the ccc and a description of each, refer to "pll configuration bits description" on page 4-22 . the configuration registe r can be serially loaded with the new configuration data and progra mmed into the ccc usin g the following ports: ? sdin: the configuration bits are serially loaded into a shift register thro ugh this port. the lsb of the configuration data bits should be loaded first. ? sdout: the shift register contents can be shi fted out (lsb first) thro ugh this po rt using the shift operation. ? sclk: this port should be driven by the shift clock. ? sshift: the active-high shift enable signal shou ld drive this port. the configuration data will be shifted into the shift register if this si gnal is high. once sshift goes low, the data shifting will be halted. ? supdate: the supdate signal is used to conf igure the ccc with the new configuration bits when shifting is complete. to access the configuration ports of the shift regi ster (sdin, sdout, sshift, etc.), the user should instantiate the ccc macro in his design with appropriate ports. actel recommends that users choose smartgen to generate the ccc macros with the required po rts for dynamic reconfiguration. figure 4-17 ? the ccc configuration mux architecture sdin sclk reset_enable sdout sshift mode supdate configuration bits dynamic shift register flash programming configuration bits <80:0> <80> <79:0> <79:0> clock conditioning circuits in igloo and proasic3 devices v1.1 4-21 users must familiarize themselves with the architec ture of the ccc core and its input, output, and configuration ports to implement the desired de lay and output frequency in the ccc structure. figure 4-18 shows a model of the ccc with configurable blocks and switches. loading the confi guration register the most important part of ccc dynamic configuratio n is to load the shift register properly with the configuration bits. there are different ways to access and load the co nfiguration shift register: ? jtag interface ? logic core ? specific i/o tiles figure 4-18 ? ccc block control bits ? graphical representation of assignments m u x c /w d c<37:35> c<28:24> internal c<60:56> glc d c<70:66> yc clkc clkb internal c<55:51> c<23:19> c<34:32> glb d dyb /v m u x b c<44:40> c<45> c<39:38> d d (0) (1) (1) (2) c<13:7> c<6:0> /m /n clka pll core (4) (2) (7) (6) (5) c<18:14> c<31:29> c<50:46> internal gla d /u m u x a 0 270 90 180 clock conditioning circuits in igloo and proasic3 devices 4-22 v1.1 jtag interface the jtag interface requires no ad ditional i/o pins. the jtag tap co ntroller is used to control the loading of the ccc configuration shift register. low-power flash devices provide a user interface macro between the jtag pins and the device core logic. this macro is called ujtag. a user should instantiate the uj tag macro in his design to access the configuration register ports via the jtag pins. for more information on ccc dynamic reconfiguration using ujtag, refer to ujtag applications in actel?s low-power flash devices. logic core if the logic core is employed, the user must design a module to provide th e configuration data and control the shifting and updating of the ccc configur ation shift register. in effect, this is a user- designed tap controller, which requ ires additional chip resources. specific i/o tiles if specific i/o tiles are used fo r configuration, the user must prov ide the external equivalent of a tap controller. this does no t require additional core re sources but does use pins. shifting the conf iguration data to enter a new configuration, all 81 bits must shift in via sdin. after all bits are shi fted, sshift must go low and supdate high to enable the new configuration. for simulation purposes, bits <71:73> and <77:80> are "don?t cares." the supdate signal must be low during any clock cycle where sshift is active. after supdate is asserted, it must go back to the low state until a new update is required. pll configuration bits description table 4-7 ? configuration bit descriptions for the ccc blocks config. bits signal name description 80 reseten reset enable enables (active hi gh) the synchronization of pll output dividers after dynamic reco nfiguration (supdate). the reset enable signal is read-only and should not be modified via dynamic reconfiguration. 79 dyncsel clock input c dynamic select configures clock input c to be sent to glc for dynamic control.* 78 dynbsel clock input b dynamic select configures clock input b to be sent to glb for dynamic control.* 77 dynasel clock input a dynamic select configures clock input a for dynamic pll configuration.* <76:74> vcosel[2:0] vco gear co ntrol three-bit vco gear control for four frequency ranges 73 statcsel mux select on input c m ux selection for clock input c* 72 statbsel mux select on input b m ux selection for clock input b* 71 statasel mux select on input a m ux selection for clock input a* <70:66> dlyc[4:0] yc output delay se ts the output delay value for yc. <65:61> dlyb[4:0] yb output delay se ts the output delay value for yb. <60:56> dlyglc[4:0] glc output delay s ets the output delay value for glc. <55:51> dlyglb[4:0] glb output delay s ets the output delay value for glb. <50:46> dlygla[4:0] primary output delay primary, gla output delay * this value depends on the input clock source, so layout must complete before these bits can be set. after completing layout in designe r, generate the ?ccc_confi guration? report by choosing tools > report > ccc_configuration . the report contains the appropriate settings for these bits. clock conditioning circuits in igloo and proasic3 devices v1.1 4-23 table 4-8 to table 4-14 on page 4-25 provide descriptions of th e configuration data for the configuration bits. 45 xdlysel system delay select when selected, inserts system delay in the feedback path in figure 4-16 on page 4-18 . <44:40> fbdly[4:0] feedback delay sets the feedback delay value for the feedback element in figure 4-16 on page 4-18 . <39:38> fbsel[1:0] primary feedback delay select co ntrols the feedback mux: no delay, include programmable delay element, or use external feedback. <37:35> ocmux[2:0] secondary 2 output select selects from the vco?s four phase outputs for glc/yc. <34:32> obmux[2:0] secondary 1 output select selects from the vco?s four phase outputs for glb/yb. <31:29> oamux[2:0] gla output se lect selects from the vco?s four phase outputs for gla. <28:24> ocdiv[4:0] secondary 2 output divider sets the divider value for the glc/yc outputs. also known as divider w in figure 4-16 on page 4-18 . the divider value will be ocdiv[4:0] + 1. <23:19> obdiv[4:0] secondary 1 output divider sets the divider value for the glb/yb outputs. also known as divider v in figure 4-16 on page 4-18 . the divider value will be obdiv[4:0] + 1. <18:14> oadiv[4:0] primary output divider sets the divider value for the gla output. also known as divider u in figure 4-16 on page 4-18 . the divider value will be oadiv[4:0] + 1. <13:7> fbdiv[6:0] feedba ck divider sets the di vider value for the pll core feedback. also known as divider m in figure 4-16 on page 4-18 . the divider value will be fbdiv[6:0] + 1. <6:0> findiv[6:0] input divider input clock divider (/n). sets the divider value for the input delay on clka. the divider value will be findiv[6:0] + 1. table 4-7 ? configuration bit descriptions for the ccc blocks (continued) config. bits signal name description * this value depends on the input clock source, so layout must complete before these bits can be set. after completing layout in designe r, generate the ?ccc_confi guration? report by choosing tools > report > ccc_configuration . the report contains the appropriate settings for these bits. table 4-8 ? input clock (fin) divider, (/n) (used as frequency divider) findiv<6:0> state divis or new frequency factor 0 1 1.00000 1 2 0.50000 ? ? ? 127 128 0.0078125 table 4-9 ? feedback signal (fbin) divider, (/m) (used as frequency multiplier) fbdiv<6:0> state divisor new frequency factor 011 122 ? ? ? 127 128 128 clock conditioning circuits in igloo and proasic3 devices 4-24 v1.1 table 4-10 ? output frequency dividers a output divider, oadiv <4:0> (/u); b output divider, obdiv <4:0> (/v); c output divider, ocdiv <4:0> (/w) oadiv<4:0>; obdiv<4:0>; cdiv<4:0> state divisor new frequency factor 0 1 1.00000 1 2 0.50000 ? ? ? 31 32 0.03125 table 4-11 ? muxa, muxb, muxc oamux<2:0>; obmux<2:0>; ocmux<2:0> state mux input selected 0 none. six-input mux and pll are bypassed. clock passes only through global mux and goes directly into hc ribs. 1 not available 2 pll feedback delay line output 3not used 4 pll vco 0 phase shift 5 pll vco 90 phase shift 6 pll vco 180 phase shift 7 pll vco 270 phase shift table 4-12 ? 2-bit feedback mux fbsel<1:0> state mux input selected 0 ground. used for power-down mode in power-down logic block. 1 pll vco 0 phase shift 2 pll delayed vco 0 phase shift 3n/a table 4-13 ? programmable delay selection for feedback delay and secondary core output delays fbdly<4:0>; dlyyb<4:0>; dlyyc<4:0> state delay value 0 typical delay = 600 ps 1 typical delay = 760 ps 2 typical delay = 920 ps ? ? 31 typical delay = 5.56 ns clock conditioning circuits in igloo and proasic3 devices v1.1 4-25 software configuration smartgen automatically generates the desired ccc functional block by configuring the control bits, and allows the user to select two ccc modes: static pll and delayed clock (clkdly). static pll configuration the newly implemented visual p ll configuration wizard feature provides the user a quick and easy way to configur e the pll with the desired settings ( figure 4-19 on page 4-26 ). the user can invoke smartgen to set the parameters and genera te the netlist file with the appropriate flash configuration bits set for the cccs. as mentioned in "pll macro block diagram" on page 4-8 , the input reference clock clka can be configured to be driven by hardwired i/o, external i/o, or core logic. the user enters the desired settings fo r all the parameters (output frequency, output selection, output phase adjustment, clock delay, feed back delay, and system delay). notice that the actual values (divider values, ou tput frequency, delay values, and phase) are shown to aid the user in reaching the desired design fre quency in real time. these values are typical-case data. best- and worst-case data can be observed through static timing analysis in smar ttime within designer. for dynamic configuration, the ccc parameters ar e defined using either the external jtag port or an internally defined serial interface via the bu ilt-in dynamic shift regist er. this feature provides the ability to compensate for chan ges in the external environment. table 4-14 ? programmable delay selection fo r global clock output delays dlygla<4:0>; dlyglb<4:0>; dlyglc<4:0> state delay value 0 typical delay = 225 ps 1 typical delay = 760 ps 2 typical delay = 920 ps ? ? 31 typical delay = 5.56 ns clock conditioning circuits in igloo and proasic3 devices 4-26 v1.1 feedback configuration the pll provides both internal and external feedback delays. depending on the configuration, various combinations of feedback delays can be achieved. internal feedback configuration this configuration essentially sets the feedback multiplexer to route the vco output of the pll core as the input to the feedback of the pll. th e feedback signal may be processed with the fixed system and the adju stable feedback delay, as shown in figure 4-20 . the dividers are automatically configured by smartgen based on the user input. indicated below is the system delay pull-down me nu. the system delay can be bypassed by setting it to 0. when set, it adds a 2 ns delay to the feedback path (wh ich results in delay advancement of the output clock by 2 ns). figure 4-19 ? visual pll conf iguration wizard input selection fixed system delay feedback selection (feedback mux) vco clock frequency programmable output delay elements output selection figure 4-20 ? internal feedback with selectable system delay clock conditioning circuits in igloo and proasic3 devices v1.1 4-27 figure 4-21 shows the controllable feedback delay. if set properly in conjunction with the fixed system delay, the total output dela y can be advanced significantly. external feedback configuration for certain applications, such as those requiring generation of pcb clocks that must be matched with existing board delays, it is useful to im plement an external feed back extfb. the phase detector of the pll core will receive clka and extfb as inputs. extfb may be processed by the fixed system delay element as well as the m divider element. the extf b option is currently not supported. after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen enab les them to save the session results and messages in a log file: **************** macro parameters **************** name : test_pll family : proasic3e output format : vhdl type : static pll input freq(mhz) : 10.000 clka source : hardwired i/o feedback delay value index : 1 feedback mux select : 2 xdly mux select : no primary freq(mhz) : 33.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 66.000 use glb : yes use yb : yes glb delay value index : 1 yb delay value index : 1 secondary1 phaseshift : 0 secondary1 mux select : 4 secondary2 freq(mhz) : 101.000 use glc : yes use yc : no glc delay value index : 1 yc delay value index : 1 secondary2 phaseshift : 0 secondary2 mux select : 4 figure 4-21 ? internal feedback with se lectable feedback delay clock conditioning circuits in igloo and proasic3 devices 4-28 v1.1 ? ? ? primary clock frequency 33.333 primary clock phase shift 0.000 primary clock output delay from clka 0.180 secondary1 clock frequency 66.667 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clka 0.180 secondary1 clock core output delay from clka 0.625 secondary2 clock frequency 100.000 secondary2 clock phase shift 0.000 secondary2 clock global output delay from clka 0.180 below is an example verilog hdl description of a legal pll core configuration generated by smartgen: module test_pll(powerdown,clka,lock,gla); input powerdown, clka; output lock, gla; wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); pll core(.clka(clka), .extfb(gnd), .powerdown(powerdown), .gla(gla), .lock(lock), .glb(), .yb(), .glc(), .yc(), .oadiv0(gnd), .oadiv1(gnd), .oadiv2(gnd), .oadiv3(gnd), .oadiv4(gnd), .oamux0(gnd), .oamux1(gnd), .oamux2(vcc), .dlygla0(gnd), .dlygla1(gnd), .dlygla2(gnd), .dlygla3(gnd) , .dlygla4(gnd), .obdiv0(gnd), .obdiv1(gnd), .obdiv2(gnd), .obdiv3(gnd), .obdiv4(gnd), .obmux0(gnd), .obmux1(gnd), .obmux2(gnd), .dlyyb0(gnd), .dlyyb1(gnd), .dlyyb2(gnd), .dlyyb3(gnd), .dlyyb4(gnd), .dlyglb0(gnd), .dlyglb1(gnd), .dlyglb2(gnd), .dlyglb3(gnd), .dlyglb4(gnd), .ocdiv0(gnd), .ocdiv1(gnd), .ocdiv2(gnd), .ocdiv3(gnd), .ocdiv4(gnd), .ocmux0(gnd), .ocmux1(gnd), .ocmux2(gnd), .dlyyc0(gnd), .dlyyc1(gnd), .dlyyc2(gnd), .dlyyc3(gnd), .dlyyc4(gnd), .dlyglc0(gnd), .dlyglc1(gnd), .dlyglc2(gnd), .dlyglc3(gnd) , .dlyglc4(gnd), .findiv0(vcc), .findiv1(gnd), .findiv2( vcc), .findiv3(gnd), .findiv4(gnd), .findiv5(gnd), .findiv6(gnd), .fbdiv0(vcc), .fbdiv1(gnd), .fbdiv2(vcc), .fbdiv3(gnd), .fbdiv4(gnd), .fbdiv5(gnd), .fbdiv6(gnd), .fbdly0(gnd), .fbdly1(gnd), .fbdly2(gnd), .fbdly3(gnd), .fbdly4(gnd), .fbsel0(vcc), .fbsel1(gnd), .xdlysel(gnd), .vcosel0(gnd), .vcosel1(gnd), .vcosel2(gnd)); defparam core.vcofrequency = 33.000; endmodule the "pll configuration bits descri ption" section on page 4-22 provides descriptions of the pll configuration bits and is provided only for completeness. the configuration bits are shown as busses only for purposes of illustr ation. they will actually be br oken up into individual pins in compilation libraries and all simu lation models. for example, th e fbsel[1:0] bu s will actually appear as pins fbsel1 and fbsel0 . the setting of these select line s for the static pll configuration is performed by the software and is completely transparent to the user. clock conditioning circuits in igloo and proasic3 devices v1.1 4-29 dynamic pll configuration to generate a dynamically reconfigur able ccc, the user should select dynamic ccc in the configuration section of the smartgen gui ( figure 4-22 ). this will ge nerate both the ccc core and the configuration shift re gister / control bit mux. even if dynamic configuration is selected in smartgen, the user still must specify the static configuration data for the ccc ( figure 4-23 ). the specified static conf iguration is used whenever the mode signal is set to low and the ccc is requ ired to function in th e static mode. the static configuration data can be used as the default behavior of the ccc where required. figure 4-22 ? smartgen gui figure 4-23 ? dynamic ccc configuration in smartgen clock conditioning circuits in igloo and proasic3 devices 4-30 v1.1 when smartgen is used to define the configuration that will be sh ifted in via the serial interface, smartgen prints out the values of the 81 configurat ion bits. for ease of use, several configuration bits are automatically inferred by smartgen when the dynamic pll core is generated; however, <71:73> (statasel, statbsel, statcsel) and <7 7:79> (dynasel, dynbsel, dyncsel) depend on the input clock source of the corresponding cc c. users must first run layout in designer to determine the exact setting for these ports. after layout is complete, generate the "ccc_configuration" re port by choosing to o l s > reports > ccc_configuration in the designer software. refer to "pll configuration bits description" on page 4-22 for descriptions of the pll configuration bits. for si mulation purposes, bits <71:73> and <78:80> are "don?t cares." therefore, it is strongly suggested that smartgen be used to generate the correct configuration bit settings for the dynamic pll core. after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen enab les them to save the session results and messages in a log file: **************** macro parameters **************** name : dyn_pll_hardio family : proasic3e output format : verilog type : dynamic ccc input freq(mhz) : 30.000 clka source : hardwired i/o feedback delay value index : 1 feedback mux select : 1 xdly mux select : no primary freq(mhz) : 33.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 40.000 use glb : yes use yb : no glb delay value index : 1 yb delay value index : 1 secondary1 phaseshift : 0 secondary1 mux select : 0 secondary1 input freq(mhz) : 40.000 clkb source : hardwired i/o secondary2 freq(mhz) : 50.000 use glc : yes use yc : no glc delay value index : 1 yc delay value index : 1 secondary2 phaseshift : 0 secondary2 mux select : 0 secondary2 input freq(mhz) : 50.000 clkc source : hardwired i/o configuration bits: findiv[6:0] 0000101 fbdiv[6:0] 0100000 oadiv[4:0] 00100 obdiv[4:0] 00000 ocdiv[4:0] 00000 oamux[2:0] 100 obmux[2:0] 000 ocmux[2:0] 000 fbsel[1:0] 01 fbdly[4:0] 00000 xdlysel 0 dlygla[4:0] 00000 clock conditioning circuits in igloo and proasic3 devices v1.1 4-31 dlyglb[4:0] 00000 dlyglc[4:0] 00000 dlyyb[4:0] 00000 dlyyc[4:0] 00000 vcosel[2:0] 100 primary clock frequency 33.000 primary clock phase shift 0.000 primary clock output delay from clka 1.695 secondary1 clock frequency 40.000 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clkb 0.200 secondary2 clock frequency 50.000 secondary2 clock phase shift 0.000 secondary2 clock global output delay from clkc 0.200 ###################################### # dynamic stream data ###################################### -------------------------------------- |name |sdin |value |type | -------------------------------------- |findiv |[6:0] |0000101 |edit | |fbdiv |[13:7] |0100000 |edit | |oadiv |[18:14] |00100 |edit | |obdiv |[23:19] |00000 |edit | |ocdiv |[28:24] |00000 |edit | |oamux |[31:29] |100 |edit | |obmux |[34:32] |000 |edit | |ocmux |[37:35] |000 |edit | |fbsel |[39:38] |01 |edit | |fbdly |[44:40] |00000 |edit | |xdlysel |[45] |0 |edit | |dlygla |[50:46] |00000 |edit | |dlyglb |[55:51] |00000 |edit | |dlyglc |[60:56] |00000 |edit | |dlyyb |[65:61] |00000 |edit | |dlyyc |[70:66] |00000 |edit | |statasel|[71] |x |masked | |statbsel|[72] |x |masked | |statcsel|[73] |x |masked | |vcosel |[76:74] |100 |edit | |dynasel |[77] |x |masked | |dynbsel |[78] |x |masked | |dyncsel |[79] |x |masked | |reseten |[80] |1 |readonly | the resultant verilog hdl description of a lega l dynamic pll core conf iguration generated by smartgen is as follows: module dyn_pll_macro(powerdown, clka, lock, gla, glb, glc, sdin, sclk, sshift, supdate, mode, sdout, clkb, clkc); input powerdown, clka; output lock, gla, glb, glc; input sdin, sclk, sshift, supdate, mode; output sdout; input clkb, clkc; wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); clock conditioning circuits in igloo and proasic3 devices 4-32 v1.1 dynccc core(.clka(clka), .extfb(gnd), .powerdown(powerdown), .gla(gla), .lock(lock), .clkb(clkb), .glb(glb), .yb(), .clkc(clkc), .glc(glc), .yc(), .sdin(sdin), .sclk(sclk), .sshift(sshift), .supdate(supdate), .mode(mode), .sdout(sdout), .oadiv0(gnd), .oadiv1(gnd), .oadiv2(vcc), .oadiv3(gnd), .oadiv4(gnd), .oamux0(gnd), .oamux1(gnd), .oamux2(vcc), .dlygla0(gnd), .dlygla1(gnd), .dlygla2(gnd), .dlygla3(gnd), .dlygla4(gnd), .obdiv0(gnd), .obdiv1(gnd), .obdiv2(gnd), .obdiv3(gnd), .obdiv4(gnd), .obmux0(gnd), .obmux1(gnd), .obmux2(gnd), .dlyyb0(gnd), .dlyyb1(gnd), .dlyyb2(gnd), .dlyyb3(gnd), .dlyyb4(gnd), .dlyglb0(gnd), .dlyglb1(gnd), .dlyglb2(gnd), .dlyglb3(gnd), .dlyglb4(gnd), .ocdiv0(gnd), .ocdiv1(gnd), .ocdiv2(gnd), .ocdiv3(gnd), .ocdiv4(gnd), .ocmux0(gnd), .ocmux1(gnd), .ocmux2(gnd), .dlyyc0(gnd), .dlyyc1(gnd), .dlyyc2(gnd), .dlyyc3(gnd), .dlyyc4(gnd), .dlyglc0(gnd), .dlyglc1(gnd), .dlyglc2(gnd), .dlyglc3(gnd), .dlyglc4(gnd), .findiv0(vcc), .findiv1(gnd), .findiv2(vcc), .findiv3(gnd), .findiv4(gnd), .findiv5(gnd), .findiv6(gnd), .fbdiv0(gnd), .fbdiv1(gnd), .fbdiv2(gnd), .fbdiv3(gnd), .fbdiv4(gnd), .fbdiv5(vcc), .fbdiv6(gnd), .fbdly0(gnd), .fbdly1(gnd), .fbdly2(gnd), .fbdly3(gnd), .fbdly4(gnd), .fbsel0(vcc), .fbsel1(gnd), .xdlysel(gnd), .vcosel0(gnd), .vcosel1(gnd), .vcosel2(vcc)); defparam core.vcofrequency = 165.000; endmodule delayed clock configuration the clkdly macro can be generated with the desi red delay and input clock source (hardwired i/o, external i/o, or core logic), as in figure 4-24 . after setting all the required parameters, users ca n generate one or more pll configurations with hdl or edif descriptions by clicking the generate button. smartgen enab les them to save the session results and messages in a log file: **************** macro parameters **************** name : delay_macro family : proasic3 output format : verilog type : delayed clock delay index : 2 clka source : hardwired i/o total clock delay = 0.935 ns. the resultant clkdly macro verilog netlist is as follows: module delay_macro(gl,clk); output gl; input clk; figure 4-24 ? delayed clock configuration dialog box clock conditioning circuits in igloo and proasic3 devices v1.1 4-33 wire vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); clkdly inst1(.clk(clk), .gl(gl), .dlygl0(vcc), .dlygl1(gnd), .dlygl2(vcc), .dlygl3(gnd), .dlygl4(gnd)); endmodule detailed usage information clock frequency synthesis deriving clocks of various fre quencies from a single reference clock is known as frequency synthesis. the pll has an input frequency range from 1.5 to 350 mh z. this frequency is automatically divided down to a range between 1.5 mhz and 5.5 mhz by input dividers (not shown) between pll macro inputs and pll phase detector inputs. the vco output is capable of an output range from 24 to 350 mhz. with dividers before the input to the pll core an d following the vco outputs, the vco output frequency can be divided to provide the final frequency range from 0.75 to 350 mhz. using smartgen, the dividers are automatically set to achi eve the closest possible matches to the specifie d output frequencies. users should be cautious when selecting the de sired pll input and output frequencies and the i/o buffer standard used to connect to the pll input and output clocks. depending on the i/o standards used for the pll input and output cloc ks, the i/o frequencies have different maximum limits. refer to the fami ly datasheets for specifications of maximum i/o frequencies for supported i/o standards. desired p ll input or output frequencies will not be achieved if the selected frequencies are higher than the maximum i/o frequencies allowed by the selected i/o standards. users should be careful when selecting the i/o standards used for pll in put and output clocks. performing post-layout simulation ca n help detect this type of error, which will be identified with pulse width violation errors. use rs are strongly encouraged to pe rform post-layout simulation to ensure the i/o standard used can provide the desi red pll input or output frequencies. users can also choose to cascade p lls together to achieve the high frequ encies needed for their applications. details of cascading plls are discussed in the "cascading cccs" section on page 4-38 . in smartgen, the actual generated frequency (under typical operating conditions) will be displayed beside the requested output frequency value. th is provides the ability to determine the exact frequency that can be generated by smartgen, in real time. the log file generated by smartgen is a useful tool in determining how closely th e requested clock frequencies match the user specifications. for example, assume a user sp ecifies 101 mhz as one of the secondary output frequencies. if the best output frequency that could be achi eved were 100 mhz, the log file generated by smartgen would indicate the actual generated frequency. simulation verification the integration of the generated pll and clkdly modules is similar to any vhdl component or verilog module instantiation in a larger design; i. e., there is no special re quirement that users need to take into account to successf ully synthesize their designs. for simulation purposes, users need to refer to the vital or verilog library that includes the functional descript ion and associated timing parameters. refer to the software tools section of the actel website to obtain the family simulation libraries. if actel desi gner is installed, these libraries are stored in the following locations: clock conditioning circuits in igloo and proasic3 devices 4-34 v1.1 for libero ide users, there is no need to compil e the simulation libraries, as they are conveniently pre-compiled in the model sim ? actel simulation tool. the following is an example of a pll configuratio n utilizing the clock frequency synthesis and clock delay adjustment features. the ste ps include generating the pll core with smartgen, performing simulation for verifi cation with model sim , and performing stat ic timing analysis with smarttime in designer. parameters of the example pll configuration: input frequency ? 20 mhz primary output requirement ? 20 mhz with clock advancement of 3.02 ns secondary 1 output requirement ? 40 mhz with clock delay of 2.515 ns figure 4-25 shows the smartgen settings. notice that the overall delays are calculated automatically, allowing the user to adjust the delay elements appropriately to obtain the desired delays. after confirming the correct settings, generate a structural netlist of th e pll and verify pll core settings by checking the log file: name : test_pll_delays family : proasic3e output format : vhdl type : static pll input freq(mhz) : 20.000 clka source : hardwired i/o feedback delay value index : 21 feedback mux select : 2 xdly mux select : no primary freq(mhz) : 20.000 primary phaseshift : 0 primary delay value index : 1 primary mux select : 4 secondary1 freq(mhz) : 40.000 use glb : yes use yb : no figure 4-25 ? smartgen settings clock conditioning circuits in igloo and proasic3 devices v1.1 4-35 ? ? ? primary clock frequency 20.000 primary clock phase shift 0.000 primary clock output delay from clka -3.020 secondary1 clock frequency 40.000 secondary1 clock phase shift 0.000 secondary1 clock global output delay from clka 2.515 next, perform simulation in model sim to verify the correct delays. figure 4-26 shows the simulation results. the delay values match those reported in the smartgen pll wizard. the timing can also be analyzed using smarttim e in designer. the user should import the synthesized netlist to designer, perform compile and layout, and then invoke smarttime. go to tools > options and change the maximum delay operating conditions to typical case . then expand the clock-to-out paths of gla and glb and the in dividual components of the path delays are shown. the path of gla is shown in figure 4-27 on page 4-36 displaying the sa me delay value. figure 4-26 ? model sim simulation results primary clock output time advancement from clka secondary1 clock global output delay from clka clock conditioning circuits in igloo and proasic3 devices 4-36 v1.1 place-and-route stage considerations several considerations must be noted to properly place the ccc macros for layout. for cccs with clock inputs configured with the hardwired i/o?driven option: ? pll macros must have the cl ock input pad coming from one of the gma* locations. ? clkdly macros must have the clock input pad coming from one of the global i/os. if a pll with a hardwired i/o in put is used at a ccc location and a hardwired i/o?driven clkdly macro is used at the same ccc location, the clock input of the clkdly macro must be chosen from one of the gmb* or gmc* pin locations. if the pll is not used or is an external i/o?driven or core logic?driven pll, the clock input of the clkd ly macro can be sourced from the gma*, gmb*, or gmc* pin locations. for cccs with clock inputs configured with the ex ternal i/o?driven option, the clock input pad can be assigned to any regular i/o location (io*** ***** pins). note that sinc e global i/o pins can also be used as regular i/os, regardle ss of ccc function (clkdly or pll), clock inputs can also be placed in any of these i/o locations. by default, the designer layout engine will place global nets in the design at one of the six chip globals. when the number of glob als in the design is greater than six, the designer layout engine will automatically assign addition al globals to the quadrant global networks of the low-power flash devices. if the user wishes to decide which global signals should be assigned to chip globals (six available) and which to the quadrant globals (three per quadrant for a total of 12 available), the assignment can be achieved with pineditor, chipplanner, or by importing a placement figure 4-27 ? static timing analysis using smarttime clock conditioning circuits in igloo and proasic3 devices v1.1 4-37 constraint file. layout will fail if the global assignments are not allocated properly. see the "physical constraints for quadrant clocks" section for information on assi gning global signals to the quadrant clock networks. promoted global signals will be instantiated with clkint macros to drive these signals onto the global network. this is automatically done by designer when the au to-promotion option is selected. if the user wishes to as sign the signals to th e quadrant globals inst ead of the default chip globals, this can done by using chipplanner, by de claring a physical design constraint (pdc), or by importing a pdc file. physical constraints for quadrant clocks if it is necessary to promote global clocks (clkbuf, clkint, pll, clkdly) to quadrant clocks, the user can define pdcs to execute the promotion. pdcs can be created using pdc commands (pre- compile) or the mvn interface (post-compile). th e advantage of using the pdc flow over the mvn flow is that the compile stage is able to automatically promote any regular net to a global net before assigning it to a quadrant. there are th ree options to place a qu adrant clock using pdc commands: ? place a clock core (not hardwired to an i/o) into a quadrant clock location. ? place a clock core (hardwired to an i/o) in to an i/o location (set_io) or an i/o module location (set_location) that dr ives a quadrant clock location. ? assign a net driven by a regular net or a cloc k net to a quadrant clock using the following command: assign_local_clock -net clock conditioning circuits in igloo and proasic3 devices 4-38 v1.1 ? use quadrant global region assignments by finding the clock net as sociated with the ccc macro under the nets tab and creating a quadra nt global region for the net, as shown in figure 4-29 . external i/o?driven cccs the above-mentioned recommendation for proper layout techniques wi ll ensure the correct assignment. it is possible that, es pecially with external i/o?driv en ccc macros, placement of the ccc macro in a desired location may not be achieved. for example, assigning an input port of an external i/o?driven ccc near a particular ccc lo cation does not guarante e global assignments to the desired location. this is because the clock inputs of external i/o?driven cccs can be assigned to any i/o location; therefore, it is possible that th e ccc connected to the clock input will be routed to a location other than the one cl osest to the i/o location, depend ing on resource availability and placement constraints. clock placer the clock placer is a placement en gine for low-power flash devices that places global signals on the chip global and quadrant global networks. based on the clock assignment constraints for the chip global and quadrant global clocks, it will try to satisfy all constraints, as well as creating quadrant clock regions when necessary. if th e clock placer fails to create th e quadrant clock regions for the global signals, it will repo rt an error and stop layout. the user must ensure that the co nstraints set to promote clock sign als to quadrant global networks are valid. cascading cccs the cccs in low-power flash devices can be cascaded. cascading cccs can help achieve more accurate pll output frequency resu lts than those achievable with a single ccc. in addition, this technique is useful when the user application requires the output clock of the pll to be a multiple of the reference clock by an integer greater than the maximum feedback divider value of the pll (divide by 128) to achieve the desired frequency. for example, the user application may requir e a 280 mhz output clock using a 2 mhz input reference clock, as shown in figure 4-30 on page 4-39 . figure 4-29 ? quadrant clock assignment for a global net clock conditioning circuits in igloo and proasic3 devices v1.1 4-39 using internal feedback, we know from eq 4-1 on page 4-19 that the maximum achievable output frequency from the primary output is f gla = f clka m / (n u) = 2 mhz 128 / (1 1) = 256 mhz eq 4-5 figure 4-31 shows the settings of the initial pll. when configuring the initial pll, specify the input to be either hardwired i/o?driven or external i/o?driven. this generates a netlist with the initial pll routed from an i/o. do not sp ecify the input to be core logi c?driven, as this prohibits the connection from the i/o pin to the input of the pll. a second pll can be connected serially to achieve the required frequency. eq 4-1 on page 4-19 to eq 4-3 on page 4-19 are extended as follows: f gla2 = f gla m 2 / (n 2 u 2 ) = f clka1 m 1 m 2 / (n 1 u 1 n 2 u 2 ) ? primary pll output clock eq 4-6 f glb2 = f yb2 = f clka1 m 1 m 2 / (n 1 n 2 v 1 v 2 ) ? secondary 1 pll output clock(s) eq 4-7 f glc2 = f yc2 = f clka1 m 1 m 2 / (n 1 n 2 w 1 w 2 ) ? secondary 2 pll output clock(s) eq 4-8 in the example, the final output frequency (f output ) from the primary output of the second pll will be as follows ( eq 4-9 ): f output = f gla2 = f gla m 2 / (n 2 u 2 ) = 256 mhz 70 / (64 1) = 280 mhz eq 4-9 figure 4-32 on page 4-40 shows the settings of the second p ll. when configuring the second pll (or any subsequent-stage plls), sp ecify the input to be core logic? driven. this gene rates a netlist with the second pll routed internally from the co re. do not specify the in put to be hardwired i/o? driven or external i/o?driven, as these options prohibit the connection from the output of the first pll to the input of the second pll. figure 4-30 ? cascade pll configuration figure 4-31 ? first-stage pll showing input of 2 mhz and output of 256 mhz clock conditioning circuits in igloo and proasic3 devices 4-40 v1.1 figure 4-33 shows the simulation results, where the first pll?s outp ut period is 3.9 ns (~256 mhz), and the stage 2 (final) output period is 3.56 ns (~280 mhz). figure 4-32 ? second-stage pll showing input of 256 mhz from first stage and final output of 280 mhz figure 4-33 ? model sim simulation results stage 1 output clock period stage 2 output clock period clock conditioning circuits in igloo and proasic3 devices v1.1 4-41 recommended board-level considerations the power to the pll core is supplied by v ccpla/b/c/d/e/f (v ccplx) , and the associated ground connections are supplied by v compla/b/c/d/e/f (v complx ). when the plls are not used, the actel designer place-and-route tool automatically disables the unused plls to lower power consumption. the user should tie unused v ccplx and v complx pins to ground. optionally, the pll can be turned on/off during normal devi ce operation via the powerdown port (see table 4-3 on page 4-7 ). pll power supply decoupling scheme the pll core is designed to tole rate noise levels on the pll po wer supply as specified in the datasheets. when operated within the noise limits, the pll will meet the ou tput peak-to-peak jitter specifications specified in the datasheets. user applications should al ways ensure the pll power supply is powered from a no ise-free or low-no ise power source. however, in situations where the pll power supply noise level is higher th an the tolerable limits, various decoupling schemes can be designed to suppress noise to th e pll power supply. an example is provided in figure 4-34 . the v ccplx and v complx pins correspond to the pll analog power supply and ground. actel strongly recommends that tw o ceramic capacitors (10 nf in parallel with 100 nf) be placed close to the power pins (less than 1 inch away ). a third generic 10 f electrolytic capacitor is recommended for low-frequency noise and should be placed farther away due to its large physical size. actel recommends that a 6.8 h inductor be placed between the supply source and the capacitors to filter out any low-/medium- and hi gh-frequency noise. in addition, the pcb layers should be controlled so the v ccplx and v complx planes have the minimum separation possible, thus generating a good-quality rf capacitor. for more recommendations, refer to the board-level considerations application note. recommended 100 nf capacitor: ? producer bc components, type x7r, 100 nf, 16 v ? bc components part number: 0603b104k160bt ? digi-key part number: bc1254ct-nd ? digi-key part number: bc1254tr-nd recommended 10 nf capacitor: ? surface-mount ceramic capacitor ? producer bc components, type x7r, 10 nf, 50 v ? bc components part number: 0603b103k500bt ? digi-key part number: bc1252ct-nd ? digi-key part number: bc1252tr-nd figure 4-34 ? decoupling scheme for one pll (should be replicated for each pll used) igloo/e or proasic3/e device power supply v ccplx v complx 10 nf 100 nf 10 f clock conditioning circuits in igloo and proasic3 devices 4-42 v1.1 conclusion the advanced cccs of th e igloo and proasic3 families are idea l for applications requiring precise clock management. they integrat e easily with the inte rnal low-skew clock networks and provide flexible frequency synthesis, clock de-skewing, and/or time shifting operations. related documents application notes board-level considerations http://www.actel.com/documents/boardlevelcons_an.pdf handbook documents ujtag applications in acte l?s low-power flash devices http://www.actel.com/documents/lpd_ujtag_hbs.pdf global resources in actel low-power flash devices http://www.actel.com/documents/lpd_global_hbs.pdf user i/o naming conventions in i/o stru ctures in igloo an d proasic3 devices http://www.actel.com/doc uments/lpd_io_hbs.pdf user?s guides igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-006-1 revised march 2008 clock conditioning circuits in igloo and proasic3 devices v1.1 4-43 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.1) page v1.0 (january 2008) table 4-1 low-power flash families and the associated text were updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 4-3 the "global input selections" section was updated to include 15 k gate devices as supported i/o type s for globals, for ccc only. 4-9 table 4-5 number of cccs by device size and package was revised to include proasic3l, igloo plus, a3 p015, agl015, aglp030, aglp060, and aglp125. 4-13 the "igloo and proasic3 ccc locations" section was revised to include 15 k gate devices in the exception stateme nts, as they do not contain plls. 4-14 51900133-0/5.06 information about unlocking the p ll was removed from the "dynamic pll configuration" section . 4-19 in the "dynamic pll configuration" section , information was added about running layout and determining the exact setting of the ports. 4-29 in table 4-7 configuration bit descriptions for the ccc blocks , the following bits were updated to delete "trans port to the user" and reference the footnote at the bottom of the table: 79 to 71. 4-22 embedded memories v1.1 5-1 flashrom in actel?s lo w-power flash devices 5 ? flashrom in actel?s low-power flash devices introduction the igloo, ? proasic ? 3, and fusion families of low-power flash-based fpgas have a dedicated nonvolatile flashrom memory of 1,024 bits, which provides a unique feature in the fpga market. the flashrom can be read, modified, and written using the jtag (or ujtag) interface. it can be read but not modified from th e fpga core. only low-power flash fpgas contain on-chip user nonvolatile memory (nvm). architecture of user nonvolatile flashrom low-power flash devices have 1 kbit of user-acce ssible nonvolatile flash me mory on-chip that can be read from the fpga core fabr ic. the flashrom is arranged in eight banks of 128 bits (16 bytes) during programming. the 128 bits in each bank are addressable as 16 bytes during the read-back of the flashrom from the fpga core. figure 5-1 shows the flashrom logical structure. the flashrom can only be programmed via the ieee 1532 jtag port. it cannot be programmed directly from the fpga core. when programming, each of the eight 128-bit banks can be selectively reprogrammed. the flashrom ca n only be reprogrammed on a bank boundary. programming involves an automatic, on-chi p bank erase prior to reprogramming the bank. the flashrom supports synchronous read. the ad dress is latched on the rising ed ge of the clock, and the new output data is stable after the fa lling edge of the same clock cycl e. for more information, refer to the timing diagrams in the appropriate family data sheet dc and switching characteristics chapter. the flashrom can be read on by te boundaries. the upper three bi ts of the flashrom address from the fpga core define the bank being accessed. th e lower four bits of th e flashrom address from the fpga core define which of the 16 by tes in the bank is being accessed. figure 5-1 ? flashrom architecture bank number 3 msb of addr (read) byte number in bank 4 lsb of addr (read) 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 flashrom in actel?s lo w-power flash devices 5-2 v1.1 flashrom support in low-power devices the low-power flash families listed in table 5-1 support the flashrom fe ature and the functions described in this document. actel's low-power flas h devices (listed in table 5-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 5-1 . where the information applies to only one fami ly or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 5-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 5-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze technology and enhanced i/o capabilities. igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1.2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher de nsity, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-pe rformance fpgas qualif ied for automotive applications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. flashrom in actel?s lo w-power flash devices v1.1 5-3 figure 5-2 ? fusion device architecture overview (afs600) figure 5-3 ? proasic3 and igloo de vice architecture 4,608-bit dual-port sram or fifo block versatile ram block ccc pro i/os isp aes decryption nonvolatile memory flashrom (from) charge pumps 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ram block ccc pro i/os isp aes decryption nonvolatile memory flashrom (from) charge pumps 4,608-bit dual-port sram or fifo block ram block flashrom in actel?s lo w-power flash devices 5-4 v1.1 flashrom applications the smartgen core generator is used to configure flashrom content. you can configure each page independently. smartgen enables you to create and modify regions within a page; these regions can be 1 to 16 bytes long ( figure 5-4 ). the flashrom content can be changed independentl y of the fpga core content. it can be easily accessed and programmed via jtag, depending on the security settings of the device. the smartgen core generator enables each region to be independently updated (described in the "programming and accessing flashrom" section on page 5-6 ). this enables you to change the flashrom content on a per-part ba sis while keeping some regions "constant" for all parts. these features allow the flashrom to be used in dive rse system applications. consider the following possible uses of flashrom: ? internet protocol (ip) addressing (wireless or fixed) ? system calibration settings ? restoring configuration after unpredictable system power-down ? device serialization and/or inventory control ? subscription-based business mo dels (e.g., set-top boxes) ? secure key storage ? asset management tracking ? date stamping ? version management figure 5-4 ? flashrom configuration 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 byte number in page page number flashrom in actel?s lo w-power flash devices v1.1 5-5 flashrom security low-power flash devices have an on-chip advanc ed encryption standard (aes) decryption core, combined with an enhanced version of the actel flash-based lock technology (flashlock ? ). together, they provide unmatched levels of securi ty in a programmable logi c device. this security applies to both the fpga core and flashrom content. these de vices use the 128-b it aes (rijndael) algorithm to encr ypt programming files for se cure transmission to the on-chip aes decryption core. the same algorithm is then used to decrypt the programming file. this key size provides approximately 3.4 10 38 possible 128-bit keys. a computing sy stem that could find a des key in a second would take approximately 149 trillion years to crack a 128-bit aes key. the 128-bit flashlock feature in low-power flash devices wo rks via a flashlock secu rity pass key mechanism, where the user locks or un locks the device with a us er-defined key. refer to security in low-power flash devices . if the device is locked with cert ain security settings, fu nctions such as device read, write, and erase are disabled. this unique feature helps to pr otect against invasive and noninvasive attacks. without the correct pass key, access to the fpga is denied. to gain access to the fpga, the device first must be unlocked us ing the correct pass key. during pr ogramming of the flashrom or the fpga core, you can generate the security header programming file, which is used to program the aes key and/or flashlock pass key. the security header programming file can also be generated independently of the flashrom and fpga core conten t. the flashlock pass key is not stored in the flashrom. low-power flash devices with aes-based security al low for secure remote field updates over public networks such as the internet, and ensure that va luable intellectual prop erty (ip) remains out of the hands of ip thieves. figure 5-5 shows this flow diagram. figure 5-5 ? programming flashrom using aes fusion aes encryption encr yp ted data aes-128 decryption core encr yp ted data flashrom fpga core programming data untrusted medium same aes key flashrom in actel?s lo w-power flash devices 5-6 v1.1 programming and accessing flashrom the flashrom content can only be programmed via jtag, but it can be read back selectively through the jtag programming interface, the ujtag interface, or via direct fpga core addressing. the pages of the flashrom can be made secure to prevent read-back via jtag. in that case, read- back on these secured pages is only possibl e by the fpga core fabric or via ujtag. a 7-bit address from the fpga core defines which of the eight pages (three msbs) is being read, and which of the 16 bytes with in the selected page (four lsbs) are being read. the flashrom content can be read on a random basis; the access time is 10 ns for a device supporting commercial specifications. the fpga core will be powered down during writing of the flashrom content. fpga power-down during flashrom programming is ma naged on-chip, and fpga core functionality is not available during programming of the flashrom. table 5-2 summarizes various flashrom access scenarios. figure 5-6 shows the accessing of the flashrom using th e ujtag macro. this is similar to fpga core access, where the 7-bit address defines which of the eight pages (three msbs) is being read and which of the 16 bytes within the selected page (four lsbs) are being read. refer to ujtag applications in actel?s low-power flash devices for details on using the ujtag macro to read the flashrom. figure 5-7 on page 5-7 and figure 5-8 on page 5-7 show the flashrom access from the jtag port. the flashrom content can be read on a random ba sis. the three-bit addres s defines which page is being read or updated. table 5-2 ? flashrom read/write capa bilities by access mode access mode flashrom read flashrom write jtag yes yes ujtag yes no fpga core yes no figure 5-6 ? block diagram of using ujtag to read flashrom contents flashrom addr [6:0] data[7:0] clk enable sdo sdi reset addr [6:0] data [7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg [7:0] control ujtag address generation and data serialization flashrom in actel?s lo w-power flash devices v1.1 5-7 figure 5-7 ? accessing flashrom using fpga core figure 5-8 ? accessing flashrom using jtag port 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 word number in page 4 lsb of addr (read) page number 3 msb of addr (read) 3-bit page address 111 1110000 7-bit address from core 0000 4-bit word address 8-bit data 8-bit data to fpga core 8-bit data from page 7 word 0 0 1 2 3 4 5 6 7 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 word number in page 4 lsb of addr (read) page number 3 msb of addr (read) 4-bit page address from jtag interface to/from jtag interface ...........................00001:128 bit data flashrom in actel?s lo w-power flash devices 5-8 v1.1 flashrom design flow the actel libero ? integrated design environment (ide) software has extensive flashrom support, including flashrom generation, instanti ation, simulation, and programming. figure 5-9 shows the user flow diagram. in the design flow, ther e are three main steps: 1. flashrom generation and instantiation in the design 2. simulation of flashrom design 3. programming file genera tion for flashrom design flashrom generation and in stantiation in the design the smartgen core genera tor, available in libero ide and designer, is the only tool that can be used to generate the flashrom content. smartgen has several user-friendly features to help generate the flashrom contents. instead of selecting each byte and assigning values, you can create a region within a page, mo dify the region, and assign properties to that region. the flashrom user interface, shown in figure 5-10 on page 5-9 , includes the configuration grid, existing regions list, and properties field. the properti es field specifies the region-spe cific information and defines the data used for that region. you can assi gn values to the following properties: 1. static fixed data?enables yo u to fix the data so it canno t be changed during programming time. this option is useful when you have fixe d data stored in this region, which is required for the operation of the design in the fpga. key storage is one example. 2. static modifiable data?select this option when th e data in a particular region is expected to be static data (such as a version number, wh ich remains the same for a long duration but could conceivably change in th e future). this op tion enables you to avoid changing the value every time you enter new data. figure 5-9 ? flashrom design flow simulator flashpoint smartgen programmer synthesis designer security header options programming files ufc file flashrom netlist user design user netlist core map mem file back- annotated netlist flashrom in actel?s lo w-power flash devices v1.1 5-9 3. read from file?this provides the full flexibil ity of flashrom usage to the customer. if you have a customized algorithm fo r generating the flashrom data, you can specify this setting. you can then generate a text file with data fo r as many devices as you wish to program, and load that into the flashpoint programming file generation softw are to get programming files that include all the data. smartgen will optionally pass the location of the file where the data is stored if the file is specified in smartgen. each text file has only one type of data format (binary, decimal, hex, or ascii text). the length of each data file must be shorter than or equal to the selected region length. if the data is shorter th an the selected region length, the most signific ant bits will be padded with 0s. fo r multiple text files for multiple regions, the first li nes are for the first device. in smartgen, load sim. value from file allows you to load the first device data in the mem file for simulation. 4. auto increment/decrement?this scenario is useful when you specify the contents of flashrom for a large number of devices in a series. you can specify the step value for the serial number and a maximum value for in ventory control. during programming file generation, the actual number of devices to be programmed is specified and a start value is fed to the software. smartgen allows you to generate the flashrom netl ist in vhdl, verilog, or edif format. after the flashrom netlist is generated, the core can be instantiated in the main design like other smartgen cores. note that the macro library name for flashrom is ufrom. the following is a sample flashrom vhdl netlist that can be instantiated in the main design: library ieee; use ieee.std_logic_1164.all; library fusion; entity from_a is port( addr : in std_logic_vector(6 downto 0); dout : out std_logic_vector(7 downto 0)); end from_a; architecture def_arch of from_a is component ufrom generic (memoryfile:string); port(do0, do1, do2, do3, do4, do5, do6, do7 : out std_logic; addr0, addr1, addr2, addr3, addr4, addr5, addr6 : in std_logic := 'u') ; figure 5-10 ? smartgen gui of the flashrom flashrom in actel?s lo w-power flash devices 5-10 v1.1 end component; component gnd port( y : out std_logic); end component; signal u_7_pin2 : std_logic ; begin gnd_1_net : gnd port map(y => u_7_pin2); ufrom0 : ufrom generic map(memoryfile => "from_a.mem") port map(do0 => dout(0), do1 => dout(1), do2 => dout(2), do3 => dout(3), do4 => dout(4), do5 => dout(5), do6 => dout(6), do7 => dout(7), addr0 => addr(0), addr1 => addr(1), addr2 => addr(2), addr3 => addr(3), addr4 => addr(4), addr5 => addr(5), addr6 => addr(6)); end def_arch; smartgen generates the following files along with the netlist. th ese are located in the smartgen folder for the li bero ide project. 1. mem (memory initialization) file 2. ufc (user flash configuration) file 3. log file the mem file is used for simulation, as explained in the "simulation of flashrom design" section . the ufc file, generated by smar tgen, has the flashrom configur ation for single or multiple devices and is used during stapl generation. it contains the region properties and simulation values. note that any changes in the mem file will not be reflected in th e ufc file. do not modify the ufc to change flashrom content. instead, use the smartgen gui to modify the flashrom content. see the "programming file generation for fl ashrom design" section on page 5-11 for a description of how the ufc file is used during the programming file gene ration. the log file has information regarding the file type and file location. simulation of flashrom design the mem file has 128 rows of 8 bits, each repres enting the contents of the flashrom used for simulation. for example, the first row represents page 0, byte 0; the next row is page 0, byte 1; and so the pattern continues. note that the three msbs of the addr ess define the page number, and the four lsbs define the byte number . so, if you send address 0000100 to flashrom, this corresponds to the page 0 and byte 4 location, which is the fifth row in the mem file. smartgen defaults to 0s for any unspecified location of the flashrom. besides using the mem file generated by smartgen, you can create a binary file with 128 rows of 8 bits each and use this as a mem file. actel recommends that you use different file names if you plan to genera te multiple mem files. during simulation, libero ide passes the mem file used as the generic fi le in the netlist, along with the design files and testbench. if you want to use different mem f iles during simulation, you need to modify the generic file reference in the netlist. ??????? ufrom0: ufrom --generic map(memoryfile => "f:\appsnotes\from\test_designs\testa\smartgen\from_a.mem") --generic map(memoryfile => "f:\appsnotes\from\test_designs\testa\smartgen\from_b.mem") ????????. the vital and verilog simulation mo dels accept the generics passed by the netlist, read the mem file, and perform simulation wi th the data in the file. flashrom in actel?s lo w-power flash devices v1.1 5-11 programming file generation for flashrom design flashpoint is the programming software used to generate the programming files for flash devices. depending on the applications, you can use the fl ashpoint software to generate a stapl file with different flashrom contents. in each case, optional aes decryption is available. to generate a stapl file that contains the same fpga core content and different flashrom contents, the flashpoint software needs an array map file fo r the core and ufc file(s ) for the flashrom. this final stapl file represents the combination of the logic of the fpga core and flashrom content. flashpoint generates the stapl files you can use to program the desired flashrom page and/or fpga core of the fpga device contents. flashp oint supports the encryp tion of the flashrom content and/or fpga array configuration data. in the case of using the flashrom for device serialization, a sequence of un ique flashrom contents will be generated. when generating a programming file with mu ltiple unique flashrom contents, yo u can specify in flashpoint whether to include all flashrom content in a single stapl file or generate a different stapl file for each flashrom ( figure 5-11 ). the programming software (flashpro) handles the single stapl file that contains the flashr om content from multiple devices. it enables you to program the flashrom content into a series of devices sequentially ( figure 5-11 ). see the flashpro user?s guide for information on serial programming. figure 5-12 on page 5-12 shows the programming file generato r, which enables different stapl file generation methods. when you select program flashrom and choose the ufc file, the flashrom settings window appears, as shown in figure 5-13 on page 5-12 . in this window, you can select the flashrom page you want to program and the data value for the configured regions. this enables you to use a different page for different programming files. figure 5-11 ? single or multiple programming file generation flashpoint fpga arrary map file fpga arrary map file security settings security settings ufc file for multiple flashrom content ufc file for single flashrom content flashpoint single stapl file single stapl file single stapl file flashrom in actel?s lo w-power flash devices 5-12 v1.1 the programming hardware and software can load the flashrom with the appropriate stapl file. programming software handles the single stapl file that contains multiple flashrom contents for multiple devices, and programs th e flashrom in sequential order (e .g., for device serialization). this feature is supported in the programming so ftware. after programming with the stapl file, you can run device_info to check the flashrom content. figure 5-12 ? programming file generator figure 5-13 ? setting flashrom during pr ogramming file generation flashrom in actel?s lo w-power flash devices v1.1 5-13 device_info displays the flashrom content, serial number, de sign name, and checksum as shown below: export idcode[32] = 123261cf export silsig[32] = 00000000 user information : checksum: 61a0 design name: top programming method: stapl algorithm version: 1 programmer: unknown ========================================= flashrom information : export region_7_0[128] = ffffffffffffffffffffffffffffffff ========================================= security setting : encrypted flashrom programming enabled. encrypted fpga array programming enabled. ========================================= the libero ide file manager re cognizes the ufc and mem files and displays them in the appropriate view. libero ide also recognizes the multiple progra mming files, if you choose the option to generate multiple files for multiple fl ashrom content in design er. these features enable a user-friendly flow for the flashrom ge neration and programming in libero ide. custom serialization using flashrom you can use flashrom for device serialization or inventory control by using the auto inc region or read from file region. flashpoint will automatica lly generate the serial number sequen ce for the auto inc region with the start value , max value , and step value provided. if you have a unique serial number generation scheme that you prefer, the read from file region allows you to import the file with your serial number scheme programmed into the region. see the flashpro user's guide for custom serialization file format information. the following steps describe ho w to perform device serializatio n or inventory control using flashrom: 1. generate flashrom using smartgen. from the properties section in the flashrom settings dialog box, select auto inc or read from file region. for auto inc region, specify the desired step value. you will not be able to modify this value in the flashpoint software. 2. go through the regula r design flow and finish place-and-route. 3. select programming file in designer and open generate programming file ( figure 5-12 on page 5-12 ). 4. click program flashrom , browse to the ufc file, and click next . the flashrom settings window appears, as shown in figure 5-13 on page 5-12 . 5. select the flashrom page you want to pr ogram and the data value for the configured regions. the stapl file generated will contai n only the data that targets the selected flashrom page. 6. modify properties fo r the serialization. ? for auto inc region, specify the start and max values. ? for read from file region, select the file name of the custom serialization file. 7. select the flashrom programming file type you want to generate from the two options below: ? single programming file for all devices: generates one programming file with all flashrom values. ? one programming file per device: genera tes a separate programming file for each flashrom value. 8. enter the number of devices you want to program and generate the required programming file. flashrom in actel?s lo w-power flash devices 5-14 v1.1 9. open the programm ing software and load the pr ogramming file. the programming software, flashpro3 and silicon sc ulptor ii, supports the device serialization feature. if, for some reason, the device fails to program a part during serialization, th e software allows you to reuse the serial data or skip the serial data. refer to the flashpro user?s guide for details. conclusion the igloo, fusion, and proasic3 families are the only fpgas that offer on-chip flashrom support. this document presents informa tion on the flashrom archit ecture, possible applications, programming, access through the jtag and ujtag in terface, and integration into your design. in addition, the libero ide tool set enables easy creation and mo dification of the flashrom content. the nonvolatile flashrom block in the fpga can be customized, enabling multiple applications. additionally, the security offered by the low-p ower flash devices keep s both the contents of flashrom and the fpga design sa fe from system over-builders, sy stem cloners, and ip thieves. related documents handbook documents security in low-pow er flash devices www.actel.com/documents/lpd_security_hbs.pdf ujtag applications in acte l?s low-power flash devices http://www.actel.com/documents/lpd_ujtag_hbs.pdf user?s guides flashpro user?s guide http://www.actel.com/documents/flashpro_ug.pdf flashpoint user?s guide http://www.actel.com/documents/flashpoint_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-007-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. the "igloo terminology" section and "proasic3 terminology" section are new. n/a v1.1 6-1 sram and fifo memories in ac tel?s low-power flash devices 6 ? sram and fifo memories in actel's low- power flash devices introduction as design complexity grows, gr eater demands are placed upon an fpga's embedded memory. actel igloo, ? fusion, and proasic ? 3 devices provide the flexibility of true dual-port and two-port sram blocks. the embedded memory, along with built-in, dedicated fifo control logic, can be used to create cascading ram blocks and fifos without using additional logic gates. igloo, igloo plus, and proasic3l fpgas contain an additional feature that allows the device to be put in a low-power mode calle d flash*freeze.? in this mode, the core draws minimal power (on the order of 4 to 127 w) and still retains va lues on the embedded sram/fifo and registers. flash*freeze technology allows th e user to switch to active mo de on demand, thus simplifying power management and the use of sram/fifos. device architecture the low-power flash devices feature up to 504 kbits of ram in 4,608-bit blocks ( figure 6-1 on page 6-2 and figure 6-2 on page 6-3 ). the total embedded sram for each device can be found in the datasheets. these memory blocks are arrang ed along the top and bo ttom of the device to allow better access from the core and i/o (in some devices, they are only available on the north side of the device). every ram block has a flexible, hardwired, embedded fifo controller, enabling the user to implement efficient fifo s without sacrificing user gates. in the igloo and proasic3 families of devi ces, the following memories are supported: ? 15 k and 30 k gate devices do not support sram and fifo. ? 60 k and 125 k gate devices support memories on the north side of the device only. ? 250 k devices and larger support memories on the north and south sides of the device. in fusion devices, the foll owing memories are supported: ? afs090 and afs250 support memories on the north side of the device only. ? afs600 and afs1500 support memories on th e north and south si des of the device. sram and fifo memori es in actel's low-p ower flash devices 6-2 v1.1 notes: 1. aes decryption not supported in 15 k and 30 k gate devices 2. flash*freeze is supported only in igloo, igloo plus, and iglooe and proasic3l devices. figure 6-1 ? igloo and proasic3 device architecture overview isp aes decryption user nonvolatile flashrom flash*freeze technology charge pumps 2 ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 1 sram and fifo memories in ac tel?s low-power flash devices v1.1 6-3 figure 6-2 ? fusion device architecture overview (afs600) flash array flash array adc analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad versatile ccc/pll i/os osc ccc isp aes decryption user nonvolatile flashrom (from) charge pumps bank 0 bank 4 bank 2 bank 1 bank 3 ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block sram and fifo memori es in actel's low-p ower flash devices 6-4 v1.1 sram/fifo support in low-power devices the low-power flash families listed in table 6-1 support sram and fifo blocks and the functions described in this document. actel's low-power flas h devices (listed in table 6-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 6-1 . where the information applies to only one fami ly or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 6-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 6-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1. 2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-perfo rmance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher de nsity, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fp gas qualified for automotive applications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. sram and fifo memories in ac tel?s low-power flash devices v1.1 6-5 sram and fifo architecture to meet the needs of high-perfo rmance designs, the memo ry blocks operate strictly in synchronous mode for both read and write operations. the r ead and write clocks are completely independent, and each can operate at any desired frequency up to 250 mhz. ? 4k1, 2k2, 1k4, 5129 (dual-port ram?2 read / 2 write or 1 read / 1 write) ? 5129, 25618 (2-port ram?1 read / 1 write) ? sync write, sync pipelined / nonpipelined read automotive proasic3 devices supp ort single-port sram capabilities or dual-port sram only under specific conditions. dual-port mode is supported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the port a clock is the inverse of the port b clock). the actel libero ? integrated design environment (i de) software macro libraries supp ort a dual-port macro only. for use of this macro as a single-port sram, the inputs and clock of one port should be tied off (grounded) to prevent errors du ring design compile. for use in dual-port mode, the same clock with an inversion between the two clock pins of th e macro should be used in the design to prevent errors during compile. the iglooe and proasic3e memory block includes dedicated fifo control logic to generate internal addresses and external flag logic (full, empty, afull, aempty). simultaneous dual-port read/write and write/writ e operations at the same address are allowed when certain timing requirements are met. during ram operation, addresses are sourced by the user logic, and the fifo controller is ignored. in fifo mode, the internal addresses are generate d by the fifo controller and routed to the ram array by internal muxes. the low-power flash device architec ture enables the read and write sizes of rams to be organized independently, allowing for bus conversion. for ex ample, the write size can be set to 25618 and the read size to 5129. both the write width and read width for the ram blocks can be specified independently with the ww (write width) and rw (read width) pins. th e different dw configurations are 25618, 5129, 1k4, 2k2, and 4k1. when widths of one, two, or four are select ed, the ninth bit is unused. for example, when writing nine-bit values and reading four-bit values, only the first four bits and the second four bits of each nine-bit value are addres sable for read operations. the ninth bit is not accessible. conversely, when writing four-bit values and reading nine-bit values, the ninth bit of a read operation will be undefined. the ram blocks empl oy little-endian byte or der for read and write operations. memory blocks and macros memory blocks can be configured with many diff erent aspect ratios, but are generically supported in the macro libraries as one of two memory elements: ram4k9 or ram512x18. the ram4k9 is configured as a true dual-port memory block, and the ram512x18 is configured as a two-port memory block. dual-port memory allows the ra m to both read from an d write to either port independently. two-port memory allows the ram to read from one port and write to the other using a common clock or independent read and write clocks. if needed, the ram4k9 blocks can be configured as two-port memory blocks. the memory block can be configured as a fifo by combining the basi c memory block with dedicated fifo controller logic. the fifo macro is named fifo4kx18 ( figure 6-3 on page 6-6 ). clocks for the ram blocks can be driven by the versanet (global resource s) or by regular nets. when using local clock segments, the clock segm ent region that encompasses the ram blocks can drive the rams. in the dual-port configuration (ram4k9), each memory block port can be driven by either rising-edge or falling-edge clocks. each po rt can be driven by clocks with different edges. though only a rising-edge clock can drive the physica l block itself, the actel designer software will automatically bubble-push the inve rsion to properly implement th e falling-edge trigger for the ram block. sram and fifo memori es in actel's low-p ower flash devices 6-6 v1.1 note: automotive proasic3 devices restrict ram4k9 to a single port or to dual ports with the same clock 180 out of phase (inverted) between clock pins. in singl e-port mode, inputs to port b should be tied to ground to prevent errors during compile. for fifo4k18, the sa me clock 180 out of phase (inverted) between clock pins should be used. figure 6-3 ? supported basic ram macros fifo4k18 rw2 rd17 rw1 rd16 rw0 ww2 ww1 ww0 rd0 estop fstop full afull empty afval11 aempty afval10 afval0 aeval11 aeval10 aeval0 ren rblk rclk wen wblk wclk rpipe wd17 wd16 wd0 reset addra11 douta8 douta7 douta0 doutb8 doutb7 doutb0 addra10 addra0 dina8 dina7 dina0 widtha1 widtha0 pipea wmodea blka wena clka addrb11 addrb10 addrb0 dinb8 dinb7 dinb0 widthb1 widthb0 pipeb wmodeb blkb wenb clkb ram4k9 raddr8 rd17 raddr7 rd16 raddr0 rd0 wd17 wd16 wd0 ww1 ww0 rw1 rw0 pipe ren rclk ram512x18 waddr8 waddr7 waddr0 wen wclk reset reset sram and fifo memories in ac tel?s low-power flash devices v1.1 6-7 sram features ram4k9 macro ram4k9 is the dual-port configuration of the ram block ( figure 6-4 ). the ram4k9 nomenclature refers to both the deepest possibl e configuration and the widest possible configuration the dual- port ram block can assume, and does not denote a possible memory aspect ratio. the ram block can be configured to the followin g aspect ratios: 4,096x1, 2,048x2, 1,024x4, and 512x9. ram4k9 is fully synchronous and has the following features: ? two ports that allow fully independent r eads and writes at different frequencies ? selectable pipelined or nonpipelined read ? active-low block enables for each port ? toggle control between read and write mode for each port ? active-low asynchronous reset ? pass-through write data or hold existing da ta on output. in pass-through mode, the data written to the write port will imme diately appear on the read port. ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. signal descriptions for ram4k9 note: automotive proasic3 devices support single-port sram capabilities, or dual-port sram only under specific conditions. dual-port mode is s upported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the por t a clock is the inverse of the port b clock). since actel libero ide macro libraries suppo rt a dual-port macro only, certain modifications must be made. these are detailed below. the following signals are used to co nfigure the ram4k9 memory element: widtha and widthb these signals enable the ram to be configured in one of four allowable aspect ratios ( table 6-2 on page 6-8 ). note: when using the sram in single-port mode for automotive proasic3 devices, widthb should be tied to ground. note: for timing diagrams of the ram signals, refer to the appropriate family datasheet. figure 6-4 ? ram4k9 simplified configuration dina douta doutb write data ram4k9 reset write data read data read data dinb addra address address addrb blka blk blk blkb wena wen wen wenb clka clk clk clkb sram and fifo memori es in actel's low-p ower flash devices 6-8 v1.1 blka and blkb these signals are active-low and will enable the resp ective ports when a sserted. when a blkx signal is deasserted, that port?s outputs hold the previous value. note: when using the sram in single-port mode for automotive proasic3 devices, blkb should be tied to ground. wena and wenb these signals switch the ram between read and write mode s for the respective ports. a low on these signals indicates a write operat ion, and a high indicates a read. note: when using the sram in single-port mode for automotive proasic3 devices, wenb should be tied to ground. clka and clkb these are the clock signals for the synchronous read and write operations. these can be driven independently or with the same driver. note: for automotive proasic3 devices, dual-port mode is supported if the clocks to the two sram ports are the same and 180 out of phase (i.e., the port a clock is the inverse of the port b clock). for use of this macro as a single-port sram, the inputs and clock of one port should be tied off (grounded) to preven t errors during design compile. pipea and pipeb these signals are used to specify pipelined read on the output. a low on pipea or pipeb indicates a nonpipelined read, and the data appears on the corresponding output in the same clock cycle. a high indicates a pipelined read, and data appears on the corresponding output in the next clock cycle. note: when using the sram in single-port mode for automotive proasic3 devices, pipeb should be tied to ground. for use in dual-port mode, the same clock with an inversion between the two clock pins of the macro should be used in the design to prevent errors during compile. wmodea and wmodeb these signals are used to config ure the behavior of the output when the ram is in write mode. a low on these signals makes the output retain data from the previous read. a high indicates pass- through behavior, wherein the data being writte n will appear immediately on the output. this signal is overridden when the ram is being read. note: when using the sram in single-port mode for automotive proasic3 devices, wmodeb should be tied to ground. reset this active-low signal re sets the control logic, fo rces the output hold state registers to zero, disables reads and writes from the sram block, and clears th e data hold registers when asserted. it does not reset the contents of the memory array. while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. addra and addrb these are used as read or write addresses, and th ey are 12 bits wide. when a depth of less than 4 k is specified, the unused high-order bits must be grounded ( table 6-3 on page 6-9 ). table 6-2 ? allowable aspect ratio settings for widtha[1:0] widtha[1:0] widthb[1:0] dw 00 00 4k1 01 01 2k2 10 10 1k4 11 11 5129 note: the aspect ratio settings are consta nt and cannot be changed on the fly. sram and fifo memories in ac tel?s low-power flash devices v1.1 6-9 note: when using the sram in single-port mode for automotive proasic3 devices, addrb should be tied to ground. dina and dinb these are the input data signals, and they are ni ne bits wide. not all nine bits are valid in all configurations. when a data width less than nine is specified, unused hi gh-order signals must be grounded ( table 6-4 ). note: when using the sram in single-port mode for automotive proasic3 devices, dinb should be tied to ground. douta and doutb these are the nine-bit output data signals. not all nine bits are valid in all configurations. as with dina and dinb, high -order bits may not be used ( table 6-4 ). the output data on unused pins is undefined. ram512x18 macro ram512x18 is the two-port configuration of the same ram block ( figure 6-5 on page 6-10 ). like the ram4k9 nomenclature, the ram512x18 nomenc lature refers to both the deepest possible configuration and the widest possible configuration the two-port ram block can assume. in two- port mode, the ram block can be configured to ei ther the 512x9 aspect ratio or the 256x18 aspect ratio. ram512x18 is also fully synchr onous and has the following features: ? dedicated read and write ports ? active-low read and write enables ? selectable pipelined or nonpipelined read ? active-low asynchronous reset ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. table 6-3 ? address pins unused/used for various supported bus widths dw addrx unused used 4k1 none [11:0] 2k2 [11] [10:0] 1k4 [11:10] [9:0] 5129 [11:9] [8:0] note: the "x" in addrx implies a or b. table 6-4 ? unused/used input and output data pins for various supported bus widths dw dinx/doutx unused used 4k1 [8:1] [0] 2k2 [8:2] [1:0] 1k4 [8:4] [3:0] 5129 none [8:0] note: the "x" in dinx or doutx implies a or b. sram and fifo memori es in actel's low-p ower flash devices 6-10 v1.1 signal descripti ons for ram512x18 ram512x18 has slightly different behavior from ram4k9, as it has dedicated read and write ports. ww and rw these signals en able the ram to be configured in one of the two allowable aspect ratios ( table 6-5 ). wd and rd these are the input an d output data signals, and they are 18 bits wide. when a 5129 aspect ratio is used for write, wd[17:9] are unused and must be grounded. if this aspect ratio is used for read, rd[17:9] are undefined. waddr and raddr these are read and write addresse s, and they are nine bits wide . when the 25618 aspect ratio is used for write or read, waddr[8] and radd r[8] are unused and must be grounded. wclk and rclk these signals are the write and read clocks, respecti vely. they can be clocked on the rising or falling edge of wclk and rclk. wen and ren these signals are the writ e and read enables, respectively. th ey are both active-low by default. these signals can be configured as active-high. reset this active-low signal re sets the control logic, fo rces the output hold state registers to zero, disables reads and writes from the sram block, and clears th e data hold registers when asserted. it does not reset the contents of the memory array. while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care must be taken not to assert it too close to the edges of active read and write clocks. note: for timing diagrams of the ram signals, refer to the appropriate family datasheet. figure 6-5 ? 512x18 two-port ram block diagram table 6-5 ? aspect ratio settings for ww[1:0] ww[1:0] rw[1:0] dw 01 01 5129 10 10 25618 00, 11 00, 11 reserved wd waddr radd r write data read data read address write address rd wen write enable read enable ren wclk write clk read clk rclk ram512x18 reset sram and fifo memories in ac tel?s low-power flash devices v1.1 6-11 pipe this signal is used to specify pipelined read on the output. a low on pi pe indicates a nonpipelined read, and the data appears on the output in th e same clock cycle. a high indicates a pipelined read, and data appears on the ou tput in the next clock cycle. sram usage the following descri ptions refer to the usage of both ram4k9 and ram512x18. clocking the dual-port sram blocks are only clocked on the rising edge. smartgen allows falling-edge- triggered clocks by adding inverters to the netlist, hence achieving dual-port sram blocks that are clocked on either edge (rising or falling). for dual-port sram, each port can be clocked on either edge and by separate clocks by port. note that for automotive proasic3, the same clock, with an inversion between the two clock pins of the macro, should be used in design to prevent errors during compile. igloo and proasic3 devices support invers ion (bubble-pushing) throughout the fpga architecture, including the clock input to the sram modu les. inversions adde d to the sram clock pin on the design schematic or in the hdl code will be automatically accounted for during design compile without incurring additional delay in the clock path. the two-port sram can be clocked on the rising or falling edge of wclk and rclk. if negative-edge ram and fifo clocking is se lected for memory macros, clock edge inversion management (bubble-pushing) is automatically used within the igloo and proasic3 development tools, without perf ormance penalty. modes of operation there are two read modes and one write mode: ? read nonpipelined (synchronous?1 clock edge ): in the standard read mode, new data is driven onto the rd bus in the same clock cycle following ra and ren valid. the read address is registered on the read port clock active edge, and data appears at rd after the ram access time. setting pipe to off enables this mode. ? read pipelined (synchronous?2 clock edges): the pipelined mode incurs an additional clock delay from address to data but enables oper ation at a much higher frequency. the read address is registered on the read port active cl ock edge, and the read da ta is registered and appears at rd after the second read clock edge. setting pi pe to on enables this mode. ? write (synchronous?1 clock edge ): on the write clock active ed ge, the write data is written into the sram at the write ad dress when wen is hi gh. the setup times of the write address, write enables, and write data are mini mal with respect to the write clock. ram initialization each sram block can be individually initialized on power-up by means of the jtag port using the ujtag mechanism. the shift register for a target block can be selected a nd loaded with the proper bit configuration to enable seri al loading. the 4,608 bits of da ta can be loaded in a single operation. fifo features the fifo4kx18 macro is created by merging the ram block with dedicated fifo logic ( figure 6-6 on page 6-12 ). since the fifo logic can only be used in conjunction with the memory block, there is no separate fifo controller macro. as with th e ram blocks, the fifo4kx18 nomenclature does not refer to a possible aspect rati o, but rather to th e deepest possible data depth and the widest possible data width. fifo4kx18 can be configured into the following aspect ratios: 4,096x1, 2,048x2, 1,024x4, 512x9, and 256x 18. in addition to being fully synchronous, the fifo4kx18 also has the following features: ? four fifo flags: empty, full, almost-empty, and almost-full ? empty flag is synchronized to the read clock ? full flag is synchronized to the write clock ? both almost-empty and almost-full fl ags have programmable thresholds sram and fifo memori es in actel's low-p ower flash devices 6-12 v1.1 ? active-low asynchronous reset ? active-low block enable ? active-low write enable ? active-high read enable ? ability to configure the fifo to either stop counting after the empty or full states are reached or to allow the fifo counters to continue ? designer software will automati cally facilitate falling-edge clocks by bubble-pushing the inversion to previous stages. the fifos maintain a separate read and write addr ess. whenever the difference between the write address and the read address is greater than or equal to the almost-full value (afval), the almost- figure 6-6 ? fifo4kx18 bl ock diagram note: for fifo4k18, the same clock 180 out of phase (inverted) between clock pins should be used. figure 6-7 ? ram block with embedded fifo controller wd full empty write data fifo4kx18 reset read data empty flag full flag rd afull almost-full flag almost-empty flag aempty wen write enable write clock read enable ren wclk read clock rclk c nt 12 e = e = c nt 12 afval aeval s ub 12 r c lk wd w c lk reset rblk ren e s top wblk wen f s top rd[17:0] wd[17:0] r c lk w c lk radd[ j :0] wadd[ j :0] ren fren fwen wen full aempty afull empty rd rpipe rw[2:0] ww[2:0] ram sram and fifo memories in ac tel?s low-power flash devices v1.1 6-13 full flag is asserted. similarly, the almost-empty flag is asserted whenever the difference between the write address and read address is less th an or equal to the al most-empty value (aeval). due to synchronization between the read and write clocks, the empty flag wi ll deassert after the second read clock edge from the po int that the write enable asser ts. however, since the empty flag is synchronized to the read clock, it will assert after the read clock reads the last data in the fifo. also, since the full flag is dependent on the actual hardware configuration, it will assert when the actual physical implementation of the fifo is full. for example, when a user config ures a 12818 fifo, the actual ph ysical implementation will be a 25618 fifo element. since the actu al implementation is 25618, the full flag will not trigger until the 25618 fifo is full, even th ough a 12818 fifo was requested. for this example, the almost- full flag can be used instead of the full flag to signal when the 128th data word is reached. to accommodate different aspect ratios, the almost-full and almo st-empty values are expressed in terms of data bits instead of data words. smartg en translates the user?s input, expressed in data words, into data bits inte rnally. smartgen allows the user to select the threshol ds for the almost- empty and almost-full flags in terms of either the read data words or the write data words, and makes the appropriate conv ersions for each flag. after the empty or full states are reached, the fi fo can be configured so the fifo counters either stop or continue counting. for timing numbers, refer to the appropriate fami ly datasheet. signal descriptions for fifo4k18 the following signals are used to co nfigure the fifo4k18 memory element: ww and rw these signals enable the fifo to be configured in one of the five allowable aspect ratios ( table 6-6 ). wblk and rblk these signals are acti ve-low and will enable th e respective ports when lo w. when the rblk signal is high, that port?s output s hold the previous value. wen and ren read and write enables. wen is active-low and re n is active-high by defa ult. these signals can be configured as active-high or -low. wclk and rclk these are the clock signals for th e synchronous read and write op erations. for fifo4k18, the same clock 180 out of phase (inverted) between clock pins should be used. note: (for automotive proasic3) these can be dri ven independently or with the same driver. rpipe this signal is used to specify pipelined r ead on the output. a lo w on rpipe indicates a nonpipelined read, and the data ap pears on the output in the same clock cycle. a high indicates a pipelined read, and data appears on the output in the next clock cycle. reset this active-low signal resets the control logic and forces the output hold state registers to zero when asserted. it does not reset the contents of the memory array ( table 6-7 on page 6-14 ). table 6-6 ? aspect ratio settings for ww[2:0] ww[2:0] rw[2:0] dw 000 000 4k1 001 001 2k2 010 010 1k4 011 011 5129 100 100 25618 101, 110, 111 101, 110, 111 reserved sram and fifo memori es in actel's low-p ower flash devices 6-14 v1.1 while the reset signal is active, read and write operations are di sabled. as with any asynchronous reset signal, care mu st be taken not to assert it too close to the edges of active read and write clocks. wd this is the input data bus and is 18 bits wide. not all 18 bits are valid in al l configurations. when a data width less than 18 is specified, unus ed higher-order signals must be grounded ( table 6-7 ). rd this is the output data bus and is 18 bits wide. not all 18 bits are va lid in all configurations. like the wd bus, high-order bits become unusable if the data width is less than 18. the output data on unused pins is undefined ( table 6-7 ). estop, fstop estop is used to stop the fifo re ad counter from further counting on ce the fifo is empty (i.e., the empty flag goes high). a high on this signal inhibits the counting. fstop is used to stop th e fifo write counter from further coun ting once the fifo is full (i.e., the full flag goes high). a high on this signal inhibits the counting. for more information on th ese signals, refer to the "estop and fstop usage" section on page 6-15 . full, empty when the fifo is full and no more data can be written, the full flag asse rts high. the full flag is synchronous to wclk to inhibit writing immediately upon detection of a full condition and to prevent overflows. since the write address is co mpared to a resynchron ized (and thus time- delayed) version of the read addr ess, the full flag will remain asserted until two wclk active edges after a read operation el iminates the full condition. when the fifo is empty and no more data can be read, the empty flag asserts high. the empty flag is synchronous to rclk to inhibit reading immediately upon detection of an empty condition and to prevent underflows. since th e read address is compared to a resynchronized (and thus time- delayed) version of the write address, the empt y flag will remain asserted until two rclk active edges after a write operation removes the empty condition. for more information on these signals, refer to the "fifo flag usage cons iderations" section on page 6-15 . afull, aempty these are programmable flags and will be asse rted on the threshold specified by afval and aeval, respectively. when the number of words store d in the fifo reaches the am ount specified by aeval while reading, the aempty output will go high. likewis e, when the number of words stored in the fifo reaches the amount specified by afval while writing, the afull output will go high. afval, aeval the aeval and afval pins are used to specify th e almost-empty and almost -full threshold values. they are 12-bit signals. for more information on thes e signals, refer to the "fifo flag usage considerations" section on page 6-15 . table 6-7 ? input data signal usage fo r different aspect ratios dw wd/rd unused 4k1 wd[17:1], rd[17:1] 2k2 wd[17:2], rd[17:2] 1k4 wd[17:4], rd[17:4] 5129 wd[17:9], rd[17:9] 25618 ? sram and fifo memories in ac tel?s low-power flash devices v1.1 6-15 fifo usage estop and fstop usage the estop pin is used to stop th e read counter from co unting any further once the fifo is empty (i.e., the empty flag goes high). likewise, the fstop pin is used to stop the wr ite counter from counting any further once the fifo is full (i.e., the full flag goes high). the fifo counters in the iglooe and proasic3e device start the co unt at zero, reach the maximum depth for the configuration (e.g., 511 for a 5129 configuration), and then restart at zero. an example application for estop, wh ere the read counter keeps counting, would be writing to the fifo once and reading the same content ov er and over without doing another write. fifo flag usage considerations the aeval and afval pins are used to specify th e 12-bit aempty and afull threshold values. the fifo contains separate 12-bit write address (waddr) and read address (raddr) counters. waddr is incremented every time a write operation is pe rformed, and raddr is in cremented every time a read operation is performed. whenever the di fference between waddr and raddr is greater than or equal to afval, the afull output is a sserted. likewise, whenever the difference between waddr and raddr is less than or equal to aeva l, the aempty output is asserted. to handle different read and write aspect ratios, afval and aeval are expressed in terms of total data bits instead of total data words. when users specify afval and aeval in terms of read or write words, the smartgen tool translates them into bit addr esses and configures these signals automatically. smartgen configures the afull flag to assert wh en the write address exceeds the read address by at least a predefined value. in a 2k8 fifo, for example, a value of 1,500 for afval means that the afull flag will be asserted after a write when th e difference between the write address and the read address reaches 1,500 (there have been at least 1,500 more writes than reads). it will stay asserted until the difference between the writ e and read addresses drops below 1,500. the aempty flag is asserted when the difference between the write address and the read address is less than a predefined value. in the exampl e above, a value of 200 for aeval means that the aempty flag will be asserted when a read causes the difference between the write address and the read address to drop to 200. it will stay asserted un til that difference rises above 200. note that the fifo can be configured with different read and write widths; in this case, the afval setting is based on the number of write data entries, and th e aeval setting is based on the number of read data entries. for aspect ratios of 5129 and 25618, only 4,096 bits can be addressed by the 12 bits of afval and aeval. the number of words must be multiplied by 8 an d 16 instead of 9 and 18. the smartgen tool automatically uses the proper values. to avoid halfwords being written or read, which could happen if different read and write as pect ratios were specified, the fifo will assert full or empty as soon as at least one word canno t be written or read. for example, if a two-bit word is written and a four-bit word is being read, the fifo will re main in the empty state when the first word is written. this occurs even if the fifo is not completely empty, because in this case, a complete word cannot be read. the sa me is applicable in the full stat e. if a four-bit word is written and a two-bit word is read, the fi fo is full and one word is read . the full flag will remain asserted because a complete word cannot be written at this point. variable aspect ra tio and cascading variable aspect ratio and cascading allow users to configure the memory in the width and depth required. the memory block can be configured as a fifo by combining the basic memory block with dedicated fifo controller logic. the fifo macro is named fifo4kx18. low-power flash device ram can be configured as 1, 2, 4, 9, or 18 bits wide. by cascading the memory blocks, any multiple of those widths can be created. the ram blocks can be from 256 to 4,096 bits deep, depending on the aspect ratio, and the blocks can also be casc aded to create deeper areas. refer to the aspect ratios available for ea ch macro cell in the "sram features" se ction on page 6-7 . the largest continuous configurable memory area is equal to half the total memory available on the device, because the ram is separated into two groups, one on each side of the device. the actel smartgen core generator will automati cally configure and cascade both ram and fifo blocks. cascading is accomplished using dedicated memory logic and does not consume user gates for depths up to 4,096 bits deep and widths up to 18, depending on the configuration. deeper memory will utilize some user gates to multiplex the outputs. sram and fifo memori es in actel's low-p ower flash devices 6-16 v1.1 generated ram and fifo macros ca n be created as either structural vhdl or verilog for easy instantiation into the design. us ers of actel libero ide can crea te a symbol for the macro and incorporate it into a design schematic. table 6-10 on page 6-17 shows the number of memory blocks required for each of the supported depth and width memory configurations, and for each depth and width combination. for example, a 256-bit deep by 32-bit wide two-port ram woul d consist of two 25618 ram blocks. the first 18 bits would be stored in the first ram block, and the remaining 14 bits would be implemented in the other 25618 ram block. this second ram block would have four bits of unused storage. similarly, a dual-port memory bloc k that is 8,192 bits d eep and 8 bits wide would be implemented using 16 memory blocks. the dual -port memory would be configur ed in a 4,0961 aspect ratio. these blocks would then be casc aded two deep to achi eve 8,192 bits of depth, and eight wide to achieve the eight bits of width. table 6-8 and table 6-9 show the maximum potential widt h and depth configuration for each device. note that 15 k and 30 k gate devices do not support ram or fifo. table 6-8 ? memory availability per igloo and proasic3 devices device ram blocks maximum potential width 1 maximum potential depth 2 igloo/ igloo plus proasic3/ proasic3l depth width depth width agl060 / aglp060 a3p060 4 256 72 (418) 16,384 (4,0964) 1 agl125 aglp125 a3p125 8 256 144 (818) 32,768 (4,0948) 1 agl250 a3p250/l 8 256 144 (818) 32,768 (4,0968) 1 a3p400 12 256 216 (1218) 49,152 (4,09612) 1 agl600 a3p600/l 24 256 432 (2418) 98,304 (4,09624) 1 agl1000 a3p1000/l 32 256 576 (3218) 131,072 (4,09632) 1 agle600 a3pe600 24 256 432 (2418) 98,304 (4,09624) 1 a3pe1500 60 256 1,080 (6018) 245,760 (4,09660) 1 agle3000 a3pe3000/l 112 256 2,016 (11218) 458,752 (4,096112) 1 notes: 1. maximum potential width uses the two-port configuration. 2. maximum potential depth uses the dual-port configuration. table 6-9 ? memory availability per fusion device device ram blocks maximum potential width 1 maximum potential depth 2 depth width depth width afs090 6 256 108 (618) 24,576 (4,0946) 1 afs250 8 256 144 (818) 32,768 (4,0948) 1 afs600 24 256 432 (2418) 98,304 (4,09624) 1 afs1500 60 256 1,080 (6018) 245,760 (4,09660) 1 notes: 1. maximum potential width uses the two-port configuration. 2. maximum potential depth uses the dual-port configuration. v1.1 6-17 sram and fifo memories in ac tel?s low-power flash devices table 6-10 ? ram and fifo memory block consumption depth 256 512 1,024 2,048 4,096 8,192 16,384 32,768 65,536 two-port dual-port dual-port dual-port dual-port du al-port dual-port dual-port dual-port dual-port width 1 number block 1 1 1 1 1 1 2 4 8 16 1 configuration any any any 1,024 4 2,048 2 4,096 1 2 (4,096 1) cascade deep 4 (4,096 1) cascade deep 8 (4,096 1) cascade deep 16 (4,096 1) cascade deep 2 number block 1 1 1 1 1 2 4 8 16 32 configuration any any any 1,0244 2,048 2 2 (4,096 1) cascaded wide 4 (4,096 1) cascaded 2 deep and 2 wide 8 (4,096 1) cascaded 4 deep and 2 wide 16 (4,096 1) cascaded 8 deep and 2 wide 32 (4,096 1) cascaded 16 deep and 2 wide 4 number block 1 1 1 1 2 4 8 16 32 64 configuration any any any 1,024 4 2 (2,048 2) cascaded wide 4 (4,096 1) cascaded wide 4 (4,096 1) cascaded 2 deep and 4 wide 16 (4,096 1) cascaded 4 deep and 4 wide 32 (4,096 1) cascaded 8 deep and 4 wide 64 (4,096 1) cascaded 16 deep and 4 wide 8 number block 1 1 1 2 4 8 16 32 64 configuration any any any 2 (1,024 4) cascaded wide 4 (2,048 2) cascaded wide 8 (4,096 1) cascaded wide 16 (4,096 1) cascaded 2 deep and 8 wide 32 (4,096 1) cascaded 4 deep and 8 wide 64 (4,096 1) cascaded 8 deep and 8 wide 9 number block 1 1 1 2 4 8 16 32 configuration any any any 2 (512 9) cascaded deep 4 (512 9) cascaded deep 8 (512 9) cascaded deep 16 (512 9) cascaded deep 32 (512 9) cascaded deep 16 number block 1 1 1 4 8 16 32 64 configuration 256 18 256 18 256 18 4 (1,024 4) cascaded wide 8 (2,048 2) cascaded wide 16 (4,096 1) cascaded wide 32 (4,096 1) cascaded 2 deep and 16 wide 32 (4,096 1) cascaded 4 deep and 16 wide 18 number block 1 2 2 4 8 18 32 configuration 256 8 2 (512 9) cascaded wide 2 (512 9) cascaded wide 4 (512 9) cascaded 2 deep and 2 wide 8 (512 9) cascaded 4 deep and 2 wide 16 (512 9) cascaded 8 deep and 2 wide 16 (512 9) cascaded 16 deep and 2 wide 32 number block 2 4 4 8 16 32 64 configuration 2 (256 18) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded wide 8 (1,024 4) cascaded wide 16 (2,048 2) cascaded wide 32 (4,096 1) cascaded wide 64 (4,096 1) cascaded 2 deep and 32 wide 36 number block 2 4 4 8 16 32 configuration 2 (256 18) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded wide 4 (512 9) cascaded 2 deep and 4 wide 16 (512 9) cascaded 4 deep and 4 wide 16 (512 9) cascaded 8 deep and 4 wide 64 number block 4 8 8 16 32 64 configuration 4 (256 18) cascaded wide 8 (512 9) cascaded wide 8 (512 9) cascaded wide 16 (1,024 4) cascaded wide 32 (2,048 2) cascaded wide 64 (4,096 1) cascaded wide 72 number block 4 8 8 16 32 configuration 4 (256 18) cascaded wide 8 (512 9) cascaded wide 8 (512 9) cascaded wide 16 (512 9) cascaded wide 16 (512 9) cascaded 4 deep and 8 wide note: memory configurations represented by grayed cells are not supported. sram and fifo memori es in actel's low-p ower flash devices 6-18 v1.1 initializing the ram/fifo the sram blocks can be initialized with data to us e as a lookup table (lut). data initialization can be accomplished either by loading the data th rough the design logic or through the ujtag interface. the ujtag macro is used to allow access from the jtag port to the internal logic in the device. by sending the appropriate initializati on string to the jtag test access port (tap) controller, the designer can put th e jtag circuitry into a mode that allows the user to shift data into the array logic through the jtag port using the ujtag macro. for a mo re detailed explanation of the ujtag macro, refer to ujtag applications in acte l?s low-power flash devices . a user interface is required to receive the user command, initiali zation data, and clock from the ujtag macro. the interface must synchronize and lo ad the data into the correct ram block of the design. the main outputs of the user interface block are the following: ? memory block chip select: selec ts a memory block for initializa tion. the chip selects signals for each memory bloc k that can be generated from different user-defined pockets or simple logic, such as a ring counter (see below). ? memory block write address: identifies the ad dress of the memory cell that needs to be initialized. ? memory block write data: the interface block re ceives the data serially from the utdi port of the ujtag macro and loads it in parallel in to the write data ports of the memory blocks. ? memory block write clock: drives the wclk of the memory block and synchronizes the write data, write address, and chip select signals. figure 6-8 shows the user interface between ujtag and the memory blocks. an important component of the interface between the ujt ag macro and the ram blocks is a serial-in/parallel-out shift register. the width of the shift register should equal the data width of the ram blocks. the ram data arrives serially fro m the utdi output of the ujtag macro. the data must be shifted into a shift regi ster clocked by the jtag clock (provided at the udrck output of the ujtag macro). then, after the shift register is fu lly loaded, the data must be tran sferred to the write data port of the ram block. to synchronize the loading of th e write data with the write address and write clock, the output of the shift register can be pipelined before driving the ram block. the write address can be generated in different ways. it can be imported through the tap using a different instruction opcode and another shift re gister, or generated internally using a simple figure 6-8 ? interfacing tap ports and sram blocks trst ujtag tdo tdi tms tck trst tdo tdi tms tck urstb udrupd udrsh udrcap udrck utdi utdo uireg[7:0] ir[7:0] user interface wdata waddr wclk wen1 wen2 wen3 reset dr_update dr_shift dr_capture dr_clk din dout wd waddr wclk wen ram1 wd waddr wclk wen ram2 wd waddr wclk wen ram3 sram and fifo memories in ac tel?s low-power flash devices v1.1 6-19 counter. using a counter to gene rate the address bits and sweep through the address range of the ram blocks is recommended, since it reduces the complexity of the user interface block and the board-level jtag driver. moreover, using an intern al counter for address ge neration speeds up the initialization procedure, since the user only needs to import the data through the jtag port. the designer may use different me thods to select among the multiple ram blocks. using counters along with demultiplexers is one approach to set the write enable signals. basicall y, the number of ram blocks needing initialization determines the mo st efficient approach. for example, if all the blocks are initialized with the same data, one enable signal is enough to activate the write procedure for all of them at the same time. an other alternative is to use different opcodes to initialize each memory block. for a small number of ram blocks, using counters is an optimal choice. for example, a ring counter can be used to select from multiple ram blocks. the clock driver of this counter needs to be con trolled by the address generation process. once the addressing of one block is finished, a clock pulse is sent to the (ring) counter to select the next memory block. figure 6-9 illustrates a simple block diagram of an interface block between ujtag and ram blocks. in the circuit shown in figure 6-9 , the shift register is enabled by the udrsh output of the ujtag macro. the counters and chip sele ct outputs are contro lled by the value of the tap instruction register. the comparison block compares the uire g value with the "start initialization" opcode value (defined by the user). if the result is true, the counters start to generate addresses and activate the wen inputs of appropriate ram blocks. the udrupd output of the ujtag macro, also shown in figure 6-9 , is used for generating the write clock (wclk) and synchronizing the data register and address counter with wclk. udrupd is high when the tap controller is in th e data register update state, which is an indication of completing the loading of one data word. once the tap controller goes into the data register update state, the udrupd output of the ujtag macro goes hi gh. therefore, the pipe line register and the address counter place the proper data and ad dress on the outputs of the interface block. meanwhile, wclk is defined as th e inverted udrupd. this will prov ide enough time (equal to the udrupd high time) for the data and address to be placed at the proper ports of the ram block before the rising ed ge of wclk. the inverter is not required if the ram blocks are clocked at the falling edge of the write clock. an example of this is described in the "example of ram initialization" section on page 6-20 . figure 6-9 ? block diagram of a sample user interface n n m m utdi udrsh udrck utdo udrupdi uireg urstb clk enable sin serial-to-port shift register pout sout d en reset clk en reset clk q q clk wdata wclk wen1 wen2 weni waddr chip select data reg. addr counter ring counter binary counter compare with defined opcode in result sram and fifo memori es in actel's low-p ower flash devices 6-20 v1.1 example of ram initialization this section of the document presents a sample design in which a 44 ram block is being initialized through the jtag port. a test feature ha s been implemented in the design to read back the contents of the ram after init ialization to verify the procedure. the interface block of th is example performs two major functions: initialization of the ram block and running a test procedure to read back the cont ents. the clock output of the interface is either the write clock (for initialization) or the read cl ock (for reading back the contents). the verilog code for the interface bl ock is included in the "sample verilog code" section on page 6-21 . for simulation purposes, users can declare the input ports of the ujtag macro for easier assignment in the testbench. however, the ujtag input ports should not be declared on the top level during synthesis. if the input ports of the uj tag are declared during synthesis, the synthesis tool will instantiate input buffer s on these ports. the input buffers on the ports will cause compile to fail in designer. figure 6-10 shows the simulation resu lts for the initiali zation step of the example design. the clk_out signal, which is the clock output of the interface bl ock, is the inverted dr_update output of the ujtag macro. it is clear that it give s sufficient time (while the tap controller is in the data register update state) for the write address and data to become stab le before loading them into the ram block. figure 6-11 presents the test procedure of the example. the data read back from the memory block matches the written data, thus ve rifying the design functionality. figure 6-10 ? simulation of initialization step figure 6-11 ? simulation of the test procedure of the example sram and fifo memories in ac tel?s low-power flash devices v1.1 6-21 the rom emulation application is based on ram bloc k initialization. if the user's main design has access only to the read ports of the ram bloc k (raddr, rd, rclk, and ren), and the contents of the ram are already initialized through the tap, then the memory bloc ks will emulate rom functionality for the core design. in this case, the write ports of the ram blocks are accessed only by the user interface block, and the interface is activated only by the tap instruction register contents. users should note that the contents of the ram blocks are lost in the absence of applied power. however, the 1 kbit of flash memory, flashrom, in low-power flash devices can be used to retain data after power is removed from the device. refer to flashrom in actel?s lo w-power flash devices for more information. sample verilog code interface block `define initialize_start 8'h22 //initialization start command value `define initialize_stop 8'h23 //initialization start command value module interface(ir, rst_n, data_shift, clk_in, data_update, din_ser, dout_ser, test, test_out,test_clk,clk_out,wr_en,rd_en,write_word,read_word,rd_addr, wr_addr); input [7:0] ir; input [3:0] read_word; //ram data read back input rst_n, data_shift, clk_in, data_update, din_ser; //initialization signals input test, test_clk; //test procedure clock and command input output [3:0] test_out; //read data output [3:0] write_word; //write data output [1:0] rd_addr; //read address output [1:0] wr_addr; //write address output dout_ser; //tdo driver output clk_out, wr_en, rd_en; wire [3:0] write_word; wire [1:0] rd_addr; wire [1:0] wr_addr; wire [3:0] q_out; wire enable, test_active; reg clk_out; //select clock for initialization or readback test always @(enable or test_clk or data_update) begin case ({test_active}) 1 : clk_out = test_clk ; 0 : clk_out = !data_update; default : clk_out = 1'b1; endcase end assign test_active = test && (ir == 8'h23); assign enable = (ir == 8'h22); assign wr_en = !enable; assign rd_en = !test_active; assign test_out = read_word; assign dout_ser = q_out[3]; //4-bit sin/pout shift register shift_reg data_shift_reg (.shiften(data_shift), .shiftin(din_ser), .clock(clk_in), .q(q_out)); //4-bit pipeline register d_pipeline pipeline_reg (.data(q_out), .clock(data_update), .q(write_word)); sram and fifo memori es in actel's low-p ower flash devices 6-22 v1.1 // addr_counter counter_1 (.clock(data_update), .q(wr_addr), .aset(rst_n), .enable(enable)); addr_counter counter_2 (.clock(test_clk), .q(rd_addr), .aset(rst_n), .enable( test_active)); endmodule interface block / ujtag wrapper this example is a sample wrap per, which connects the interface block to the ujtag and the memory blocks. // wrapper module top_init (tdi, trstb, tms, tck, tdo, test, test_clk, test_ out); input tdi, trstb, tms, tck; output tdo; input test, test_clk; output [3:0] test_out; wire [7:0] ir; wire reset, dr_shift, dr_cap, init_clk, dr_update, data_in, data_out; wire clk_out, wen, ren; wire [3:0] word_in, word_out; wire [1:0] write_addr, read_addr; ujtag ujtag_u1 (.uireg0(ir[0]), .uireg1(ir[1]), .uireg2(ir[2]), .uireg3(ir[3]), .uireg4(ir[4]), .uireg5(ir[5]), .uireg6(ir[6]), .uireg7(ir[7]), .urstb(reset), .udrsh(dr_shift), .udrcap(dr_cap), .udrck(init_clk), .udrupd(dr_update), .ut-di(data_in), .tdi(tdi), .tms(tms), .tck(tck), .trstb(trstb), .tdo(tdo), .ut-do(data_out)); mem_block ram_block (.do(word_out), .rclock(clk_out), .wclock(clk_out), .di(word_in), .wrb(wen), .rdb(ren), .wad-dr(write_addr), .raddr(read_addr)); interface init_block (.ir(ir), .rst_n(reset), .data_shift(dr_shift), .clk_in(init_clk), .data_update(dr_update), .din_ser(data_in), .dout_ser(data_out), .test(test), .test_out(test_out), .test_clk(test_clk), .clk_out(clk_out), .wr_en(wen), .rd_en(ren), .write_word(word_in), .read_word(word_out), .rd_addr(read_addr), .wr_addr(write_addr)); endmodule address counter module addr_counter (clock, q, aset, enable); input clock; output [1:0] q; input aset; input enable; reg [1:0] qaux; always @(posedge clock or negedge aset) begin if (!aset) qaux <= 2'b11; else if (enable) qaux <= qaux + 1; end assign q = qaux; endmodule sram and fifo memories in ac tel?s low-power flash devices v1.1 6-23 pipeline register module d_pipeline (data, clock, q); input [3:0] data; input clock; output [3:0] q; reg [3:0] q; always @ (posedge clock) q <= data; endmodule 4x4 ram block (created by sm artgen core generator) module mem_block(di,do,waddr,raddr,wrb,rdb,wclock,rclock); input [3:0] di; output [3:0] do; input [1:0] waddr, raddr; input wrb, rdb, wclock, rclock; wire webp, weap, vcc, gnd; vcc vcc_1_net(.y(vcc)); gnd gnd_1_net(.y(gnd)); inv webubbleb(.a(wrb), .y(webp)); ram4k9 ramblock0(.addra11(gnd), .addra10(gnd), .addra9(gnd), .addra8(gnd), .addra7(gnd), .addra6(gnd), .addra5(gnd), .addra4(gnd), .addra3(gnd), .addra2(gnd), .addra1(raddr[1]), .addra0(raddr[0]), .addrb11(gnd), .addrb10(gnd), .addrb9(gnd), .addrb8(gnd), .addrb7(gnd), .addrb6(gnd), .addrb5(gnd), .addrb4(gnd), .addrb3(gnd), .addrb2(gnd), .addrb1(waddr[1]), .addrb0(waddr[0]), .dina8(gnd), .dina7(gnd), .dina6(gnd), .dina5(gnd), .dina4(gnd), .dina3(gnd), .dina2(gnd), .dina1(gnd), .dina0(gnd), .dinb8(gnd), .dinb7(gnd), .dinb6(gnd), .dinb5(gnd), .dinb4(gnd), .dinb3(di[3]), .dinb2(di[2]), .dinb1(di[1]), .dinb0(di[0]), .widtha0(gnd), .widtha1(vcc), .widthb0(gnd), .widthb1(vcc), .pipea(gnd), .pipeb(gnd), .wmodea(gnd), .wmodeb(gnd), .blka(weap), .blkb(webp), .wena(vcc), .wenb(gnd), .clka(rclock), .clkb(wclock), .reset(vcc), .douta8(), .douta7(), .douta6(), .douta5(), .douta4(), .douta3(do[3]), .douta2(do[2]), .douta1(do[1]), .douta0(do[0]), .doutb8(), .doutb7(), .doutb6(), .doutb5(), .doutb4(), .doutb3(), .doutb2(), .doutb1(), .doutb0()); inv webubblea(.a(rdb), .y(weap)); endmodule sram and fifo memori es in actel's low-p ower flash devices 6-24 v1.1 software support the smartgen core generator is the easiest wa y to select and config ure the memory blocks ( figure 6-12 ). smartgen automatically selects the proper memory block type an d aspect ratio, and cascades the memory blocks based on the user's se lection. smartgen also configures any additional signals that may require tie-off. smartgen will attempt to use the minimum number of blocks required to implement the desired memory. when cascading, smartgen will configure the memory fo r width before configuring for depth. for example, if the user requests a 2568 fifo, smartgen will use a 5129 fifo configuration, not 25618. figure 6-12 ? smartgen core generator interface sram and fifo memories in ac tel?s low-power flash devices v1.1 6-25 smartgen enables the user to co nfigure the desired ram element to use either a single clock for read and write, or two independent clocks for read and write. the user can select the type of ram as well as the width/depth and several other parameters ( figure 6-13 ). smartgen also has a port mapping option that allows the user to specify the names of the ports generated in the memory block ( figure 6-14 ). figure 6-13 ? smartgen memory configuration interface figure 6-14 ? port mapping interface for smartgen-generated memory sram and fifo memori es in actel's low-p ower flash devices 6-26 v1.1 smartgen also configures the fifo according to user specifications. users can select no flags, static flags, or dynamic flags. static flag settings are configured using configuration flash and cannot be altered without reprogramming th e device. dynamic flag settings are determined by register values and can be altered without reprogramming the device by reloading the register values either from the design or through the ujtag inte rface described in the "initializing the ram/fifo" section on page 6-18 . smartgen can also configure the fifo to contin ue counting after the fifo is full. in this configuration, the fifo write coun ter will wrap after the counter is full and continue to write data. with the fifo configured to continue to read a fter the fifo is empty, the read counter will also wrap and re-read data that was previously read. this mode can be used to continually read back repeating data patterns stored in the fifo ( figure 6-15 ). fifos configured using smartgen can also make use of the port mapping feature to configure the names of the ports. limitations users should be aware of the following limitatio ns when configuring sram blocks for low-power flash devices: ? smartgen does not track the target device in a family, so it cannot determine if a configured memory block will fit in the target device. ? dual-port rams with different read an d write aspect ratios are not supported. ? cascaded memory blocks can only use a maximum of 64 blocks of ram. ? the full flag of the fifo is sensitive to the maximum depth of the actual physic al fifo block, not the depth requested in the smartgen interface. figure 6-15 ? smartgen fifo configuration interface sram and fifo memories in ac tel?s low-power flash devices v1.1 6-27 conclusion igloo, fusion, and proasic3 devices provide user s with extremely flexible sram blocks for most design needs, wi th the ability to choose between an ea sy-to-use dual-port memory or a wide-word two-port memory. used with the bu ilt-in fifo controllers, these memory blocks also serve as highly efficient fifos that do not consume user gates when impl emented. the actel smartgen core generator provides a fast and easy way to conf igure these memory elem ents for use in designs. related documents handbook documents ujtag applications in acte l?s low-power flash devices www.actel.com/document s/lpd_ujtag_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-008-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.1) page v1.0 (january 2008) the "introduction" section was updated to include the igloo plus family. 6-1 the "device architecture" section was updated to state that 15 k gate devices do not supp ort sram and fifo. 6-1 the first note in figure 6-1 igloo and proasi c3 device architecture overview was updated to include mention of 15 k gate devices, and igloo plus was added to the second note. 6-3 the table 6-1 low-power flash families table and associated text were updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 6-4 the text introducing table 6-8 memory availability per igloo and proasic3 devices was updated to replace "a3p030 and agl030" with "15 k and 30 k gate devices. table 6-8 memory availability per igloo and proasic3 devices was updated to remove agl400 and agle1500 and include igloo plus and proasic3l devices. 6-16 i/o descriptions and usage v1.1 7-1 7 ? i/o structures in igloo and proasic3 devices introduction low-power flash devices feature a flexible i/o structure, supporting a range of mixed voltages (1.2 v, 1.5 v, 1.8 v, 2.5 v, and 3.3 v) through bank-selectable voltages. igloo, ? proasic3 ? l, and proasic3 families support standard, stan dard plus, and advanced i/os. users designing i/o solutions are faced with a number of implementation decisions and configuration choices that can dire ctly impact the efficiency and effectiveness of their final design. the flexible i/o structure, supporting a wide variety of voltages and i/o standards, enables users to meet the growing challenges of their ma ny diverse applications. the actel libero ? integrated design environment (ide) provides an easy way to implement i/os that will result in robust i/o design. this document first describes th e two different i/o types in terms of the standards and features they support. it then explains the individual features and how to implement them in actel's libero ide. figure 7-1 ? i/o block logical representation input register e = enable pin a y pad 1 2 3 4 5 6 oce ice ice input register input register clr/pre clr/pre clr/pre clr/pre clr/pre pull-up/-down resistor control signal drive strength and slew rate control output register output register to fpga core from fpga core output enable register oce i/o / clr or i/o / pre / oce i/o / q0 i/o / q1 i/o / iclk i/o / d0 i/o / d1 / ice i/o / oclk i/o / oe i/o structures in iglo o and proasi c3 devices 7-2 v1.1 low-power flash device i/o support the low-power flash families listed in table 7-1 support i/os and the fu nctions described in this document. actel's low-power flas h devices (listed in table 7-1 ) provide a selection of low-power, secure, live- at-power-up, single-chip solutions. the nonvolat ile flash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design se curity without extern al overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 7-1 . where the information applies to only one fami ly or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 7-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 7-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1.2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher de nsity, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fp gas qualified for automotive applications automotive proasic3 dc and switching characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the relevant timing numbers in the datasheet. i/o structures in igloo and pro asic3 devices v1.1 7-3 advanced i/os?igloo, proasic3l, and proasic3 table 7-2 and table 7-3 show the voltages and compatible i/ o standards for igloo, proasic3l, and proasic3 families. i/os provide programmable slew rates (except 30 k ga te devices), drive streng ths, and weak pull-up and pull-down circuits. 3.3 v pci and 3.3 v pci-x are 5 v?tolerant. see the "5 v input tolerance" section on page 7-20 for possible implementa tions of 5 v tolerance. all i/os are in a known state during power-up, and any power-up sequence is allowed without current impact. refer to the "i/o power-up and supply voltage thresholds for power-on reset (commercial and industrial)" sect ion in the datasheet for more information. during power-up, before reaching activation levels, the i/o inpu t and output buffers are disabled while the weak pull-up is enabled. activation leve ls are described in the datasheet. i/o banks and i/o standards compatibility i/os are grouped into i/o voltage banks. each i/o voltage bank has dedicate d i/o supply and grou nd voltages (vmv/gndq for input buffers and v cci /gnd for output buffers). this isolation is ne cessary to minimize si multaneous switching noise from the input and output (ssi and sso). the switching noise (ground bounce and power bounce) is generated by the output buffers and transferred into input buffer circuits, and vice versa. because of these dedicated supplies, only i/ os with compatible standards can be assigned to the same i/o voltage bank. table 7-3 shows the required voltage co mpatibility values for each of these voltages. there are four i/o banks on the 250 k gate through 1 m gate devices. there are two i/o banks on the 30 k, 60 k, and 125 k gate devices. i/o standards are compatible if their v cci and vmv values are iden tical. vmv and gndq are "quiet" input power supply pins and are not used on 30 k gate devices ( table 7-3 ). table 7-2 ? supported i/o standards igloo agl030 agl060 agl125 agl250 agl600 agl1000 proasic3 a3p030 a3p060 a3p125 a3p250/ a3p250l a3p400 a3p600/ a3p600l a3p1000/ a3p1000l single-ended lvttl/lvcmos 3.3 v, lvcmos 2.5 v / 1.8 v / 1.5 v, lvcmos 2.5/5.0 v ??? ??? ? 3.3 v pci/pci-x ? ????? ? differential lvpecl, lvds, blvds, m-lvds ??? ??? ? table 7-3 ? v cci voltages and compatible ig loo and proasic3 standards v cci and vmv (typical) com patible standards 3.3 v lvttl/lvcmos 3.3, pc i 3.3, pci-x 3.3 lvpecl 2.5 v lvcmos 2.5, lvcmos 2. 5/5.0, lvds, blvds, m-lvds 1.8 v lvcmos 1.8 1.5 v lvcmos 1.5 i/o structures in iglo o and proasi c3 devices 7-4 v1.1 i/o banks advanced i/os are divided into multiple technology banks. each device has two to four banks, and the number of banks is device-dependent as de scribed above. the bank types have different characteristics, such as drive strength, the i/o standards supported, and timing and power differences. there are three types of banks: advanced i/o ba nks, standard plus i/o banks, and standard i/o banks. advanced i/o banks offer single-ended and differ ential capabilities. these banks are available on the east and west sides of 250 k, 400 k, 600 k and 1 m gate devices. standard plus i/o banks offer lvttl/lvcmos and pc i single-ended i/o standards. these banks are available on the north and south sides of 250 k, 40 0 k, 600 k, and 1 m gate devices as well as all sides of 125 k and 60 k devices. standard i/o banks offer lvttl/lvcmos single-end ed i/o standards. these banks are available on all sides of 30 k gate devices. table 7-5 shows the i/o bank types, devices and bank locations supported, dr ive strength, slew rate control, and supported standards. orphan?all inputs and disabled outputs are voltage-tolerant up to 3.3 v. for more information about i/o an d global assignments to i/o ba nks in a device, refer to the specific pin table for the de vice in the packaging sectio n of the datasheet and the "user i/o naming convention" section on page 7-32 . table 7-4 ? igloo and proasic3 bank type definitions and differences i/o bank type device and bank location drive strength i/o standards supported lvttl/ lvcmos pci/pci-x lvpecl, lvds, blvds, m-lvds standard 30 k gate devices (all banks) refer to table 7-14 on page 7-29 ? not supported not supported standard plus 60 k and 125 k gate devices (all banks) refer to table 7-15 on page 7-29 ?? not supported north and south banks of 250 k and 1 m gate devices refer to table 7-15 on page 7-29 ?? not supported advanced east and west banks of 250 k and 1 m gate devices refer to table 7-16 on page 7-30 ?? ? i/o structures in igloo and pro asic3 devices v1.1 7-5 features supported on every i/o table 7-5 lists all features supported by transmitter/receiver for single -ended and diff erential i/os. table 7-6 on page 7-6 lists the performance of each io technology. table 7-5 ? i/o features feature description all i/o ? high performance ( table 7-6 on page 7-6 ) ? electrostatic discharge (esd) protection ? i/o register combining option single-ended transmitter features ? hot-swap: ? 30 k gate devices: hot-swap in every mode ? all other igloo and proasic3 devices: no hot-swap ? output slew rate: 2 sl ew rates (except 30 k gate devices) ? weak pull-up and pull-down resistors ? output drive: 3 drive strengths ? programmable output loading ? skew between output buffer enable/disable time: 2 ns delay on rising edge and 0 ns delay on falling edge (see the "selectable skew between output buffer enable and disa ble times" section on page 7-25 for more information) ? lvttl/lvcmos 3.3 v output s compatible with 5 v ttl inputs single-ended receiver features ? 5 v?input?tolerant receiver ( table 7-12 on page 7-19 ) ? separate ground plan e for gndq pin and power plane for vmv pin are us ed for input buffer to reduce output-induced noise. differential receiver features?250 k through 1 m gate devices ? separate ground plan e for gndq pin and power plane for vmv pin are us ed for input buffer to reduce output-induced noise. cmos-style lvds, blvds, m-lvds, or lvpecl transmitter ? two i/os and external resistors are used to provide a cmos-style lvds, ddr lvds, blvds, and m-lvds/lvpecl transmitter solution. ? high slew rate ? weak pull-up and pull-down resistors ? programmable output loading i/o structures in iglo o and proasi c3 devices 7-6 v1.1 table 7-6 ? maximum i/o frequency for single-ended and differential i/os in all banks in igloo and proasic devices (maximum drive st rength and high slew selected) specification maximum performance proasic3 igloo v2 or v5 devices, 1.5 v dc core supply voltage igloo v2, 1.2 v dc core supply voltage lvttl/lvcmos 3.3 v 200 mhz 180 mhz tbd lvcmos 2.5 v 250 mhz 230 mhz tbd lvcmos 1.8 v 200 mhz 180 mhz tbd lvcmos 1.5 v 130 mhz 120 mhz tbd pci 200 mhz 180 mhz tbd pci-x 200 mhz 180 mhz tbd lvds 350 mhz 300 mhz tbd lvpecl 350 mhz 300 mhz tbd i/o structures in igloo and pro asic3 devices v1.1 7-7 i/o architecture i/o tile the i/o tile provides a flexible, programmable s tructure for implementing a large number of i/o standards. in addition, the regi sters available in the i/o tile can be used to support high- performance register inputs and outputs, with register enable if desired ( figure 7-2 ). the registers can also be used to support the jesd-79c double data rate (ddr) standard within the i/o structure (see ddr for actel?s low-power flash devices for more information). in addition, the registers available in the i/o tile can be used to suppo rt high-performance registe r inputs and outputs, with register enable if desired ( figure 7-2 ). as depicted in figure 7-2 , all i/o registers share one clr port . the output register and output enable register sh are one clk port. figure 7-2 ? i/o block logical representation input register e = enable pin a y pad 1 2 3 4 5 6 oce ice ice input register input register clr/pre clr/pre clr/pre clr/pre clr/pre pull-up/-down resistor control signal drive strength and slew rate control output register output register to fpga core from fpga core output enable register oce i/o / clr or i/o / pre / oce i/o / q0 i/o / q1 i/o / iclk i/o / d0 i/o / d1 / ice i/o / oclk i/o / oe i/o structures in iglo o and proasi c3 devices 7-8 v1.1 i/o bank structure low-power flash device i/os are divided into mult iple technology banks. the number of banks is device-dependent. the iglooe, proasic3el, and proasic3e devices have eight banks (two per side); and igloo, proasic3l, and proasic3 devices have two to four banks. each bank has its own v cci power supply pin. multiple i/o standard s can co-exist within a single i/o bank. in iglooe, proasic3el, and proasic3e devices, each i/o bank is subdivided into v ref minibanks. these are used by volt age-referenced i/os. v ref minibanks contain 8 to 18 i/os. all i/os in a given minibank share a common v ref line (only one v ref pin is needed per v ref minibank). therefore, if an i/o in a v ref minibank is configured as a v ref pin, the remaining i/os in that minibank will be able to use the voltage as signed to that pin. if the location of the v ref pin is selected manually in the software, the user must satisfy v ref rules (refer to the i/o software control in low-power flash devices ). if the user do es not pick the v ref pin manually, the software automatically assigns the v ref pin. figure 7-3 is a snapshot of a section of the i/o ring , showing the basic elements of an i/o tile, as viewed from the designer place-and-ro ute tool?s multiview navigator (mvn). low-power flash device i/os are implemented using tw o tile types: i/o and differential i/o (diffio). the diffio tile is built up using two i/o tiles, wh ich form an i/o pair (p side and n side). these i/o pairs are used according to differential i/o standards. both th e p and n sides of the diffio tile include an i/o buffer and two i/o logi c blocks (auxiliary and main logic). every minibank (e devices only) is built up from multiple diffio tiles. the number of the minibank depends on the different-size dies. refer to the "i/o architecture" section on page 7-7 for an illustration of the minibank structure. figure 7-4 on page 7-9 shows a simplified diagram of the i/o buffer circuitry. the output enable signal (oe) enables the output buffer to pass the signal from the core logic to the pin. the output buffer contains esd protection circuitry, an n-ch annel transistor that shun ts all esd surges (up to the limit of the device esd specific ation) to gnd. this transistor also serves as an output pull-down resistor. each output buffer also contains programmable slew rate, drive strength, programmable power-up state (pull-up/-down resistor), ho t-swap, 5 v tolerance, and clamp diode control circuitry. multiple flash switches (not shown in figure 7-4 on page 7-9 ) are programmed by user selections in the software to activate different i/o features. figure 7-3 ? snapshot of an i/o tile { i/o pad/buffer i/o logic (assigned) n side (assigned) p side (unassigned) diffio tile minibank other minibanks i/o structures in igloo and pro asic3 devices v1.1 7-9 i/o registers each i/o module contains several input, ou tput, and enable registers. refer to figure 7-4 for a simplified representation of the i/o block. the number of input re gisters is selected by a set of switches (not shown in figure 7-2 on page 7-7 ) between registers to implement single-ended or differential data transmission to and from the fpga core. the designer software sets these switches for the user. a common cl r/pre signal is employed by a ll i/o registers when i/o register combining is used. input register 2 does not have a clr/pre pin, as this register is used for ddr implementation. the i/o register combining must satisfy certain rules. notes: 1. all nmos transistors connected to th e i/o pad serve as esd protection. 2. see table 7-2 on page 7-3 for available i/o standards. figure 7-4 ? simplified i/o buffer circuitry programmable input delay control input buffer standard 2 and schmitt trigger control input signal to core logic input buffer oe (from core logic) output signal (from core logic) output buffer logic and enable skew circuit drive strength and output slew rate control clamp diode esd protection 1 weak pull- down control (from core) clamp diode esd protection 1 v cci i/o pad weak pull-up control (from core) hot-swap, 5 v tolerance, and clamp diode control output buffer v cci v cci i/o structures in iglo o and proasi c3 devices 7-10 v1.1 i/o standards single-ended standards these i/o standards use a push-pull cmos output sta ge with a voltage referenced to system ground to designate logical states. the input buffer conf iguration, output drive, and i/o supply voltage (v cci ) vary among the i/o standards ( figure 7-5 ). the advantage of these standards is that a comm on ground can be used for multiple i/os. this simplifies board layout and reduces system cost. their low-edge-rate ( dv / dt ) data transmission causes less electromagnetic interference (emi) on th e board. however, they are not suitable for high-frequency (>200 mhz) switching due to noise impact and higher power consumption. lvttl (low-voltage ttl) this is a general-purpose standard (eia/jesd8-b) for 3.3 v applications . it uses an lvttl input buffer and a push-pull output buffer. the lvttl output bu ffer can have up to six different programmable drive strengths. the default drive strength is 12 ma. v cci is 3.3 v. refer to "i/o programmable features" on page 7-14 for details. lvcmos (low-voltage cmos) the low-power flash devices provide four different kinds of lvcmos: lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 1.8 v, and lvcmos 1.5 v. lvcmos 3.3 v is an extension of the lvcmos standard (jesd8-b? compliant) used for general-purpose 3.3 v applications. lvcmos 2.5 v is an extension of the lvcmos standard (jesd8-5?compliant) used for ge neral-purpose 2.5 v applications. lvcmos 2.5 v for the 30 k gate devices has a clamp diode to v cci , but for all other devices there is no clamp diode. there is yet another standard supported by ig loo and proasic3 devices (except a3p030): lvcmos 2.5/5.0 v. this standard is simila r to lvcmos 2.5 v, with the exception that it can support up to 3.3 v on the input side (2.5 v output drive). lvcm os 1.8 v is an extension of the lvcmos standard (jesd8-7?compliant) used for general-purpose 1.8 v applications. lvcmos 1.5 v is an extension of the lvcmos standard (jesd8-11?compliant) used for general-purpose 1.5 v applications. the v cci values for these standards are 3.3 v, 2.5 v, 1.8 v, and 1.5 v, respectively. all these versions use a 3.3 v?tolerant cmos input buffer and a push-pull output buffer. like lvttl, the output buffer has up to seven different programmable drive strength s (2, 4, 6, 8, 12, 16, and 24 ma). refer to "i/o programmable features" on page 7-14 for details. 3.3 v pci (peripheral component interface) this standard specifies su pport for both 33 mhz and 66 mhz pc i bus applications. it uses an lvttl input buffer and a push-pull output buffer. with the aid of an exte rnal resistor, this i/o standard can be 5 v?compliant for low-power flash devices. it does not have programmable drive strength. figure 7-5 ? single-ended i/o standard topology out gnd in gnd device 1 device 2 v cci v cci i/o structures in igloo and pro asic3 devices v1.1 7-11 3.3 v pci-x (peripheral co mponent interface extended) an enhanced version of the pci specification, 3. 3 v pci-x can support higher average bandwidths; it increases the speed that data can move with in a computer from 66 mhz to 133 mhz. it is backward-compatible, which means devices can op erate at conventional pci frequencies (33 mhz and 66 mhz). pci-x is more fault-tolerant than pc i. it also does not have programmable drive strength. voltage-referenced standards i/os using these standards are referenced to an external reference voltage (v ref ) and are supported on e devices only. hstl class i and ii (hi gh-speed transceiver logic) these are general-purpose, high-s peed 1.5 v bus standards (eia/j esd 8-6) for signaling between integrated circui ts. the signaling range is 0 v to 1.5 v, a nd signals can be either single-ended or differential. hstl requires a differential amplif ier input buffer and a push -pull output buffer. the reference voltage (v ref ) is 0.75 v. these standards are used in the memory bus interface with data switching capability of up to 400 mhz. the other advantages of these standards are low power and fewer emi concerns. hstl has four classes, of which low-power flash devices support class i and ii. these classes are defined by standard eia/jesd 8-6 from th e electronic industri es alliance (eia): ? class i ? unterminated or symmetrically parallel-terminated ? class ii ? series-terminated ? class iii ? asymmetrically parallel-terminated ? class iv ? asymmetrically double-parallel-terminated sstl2 class i and ii (stub ser ies terminated logic 2.5 v) these are general-purpose 2.5 v me mory bus standards (jesd 8-9) for driving transmission lines, designed specifically for driving the ddr sd ram modules used in computer memory. sstl2 requires a differential amplifier input buffer and a push-pull outp ut buffer. the reference voltage (v ref ) is 1.25 v. sstl3 class i and ii (stub ser ies terminated logic 3.3 v) these are general-purpose 3.3 v me mory bus standards (jesd 8-8) for driving transmission lines. sstl3 requires a differential am plifier input buffer and a push-p ull output buffer. the reference voltage (v ref ) is 1.5 v. figure 7-6 ? sstl and hstl topology out gnd in gnd v ref v ref v cci v cci device 1 device 2 i/o structures in iglo o and proasi c3 devices 7-12 v1.1 gtl 2.5 v (gunning tran sceiver logic 2.5 v) this is a low-power standard (jesd 8.3) for electri cal signals used in cmos circuits that allows for low electromagnetic interference at high transfer speeds. it has a voltage swing between 0.4 v and 1.2 v and typically operates at sp eeds of between 20 and 40 mhz. v cci must be connected to 2.5 v. the reference voltage (v ref ) is 0.8 v. gtl 3.3 v (gunning tran sceiver logic 3.3 v) this is the same as gtl 2.5 v above, except v cci must be connected to 3.3 v. gtl+ (gunning transcei ver logic plus) this is an enhanced version of gtl that has define d slew rates and higher voltage levels. it requires a differential amplifier input buffer and an open -drain output buffer. even though the output is open-drain, v cci must be connected to either 2.5 v or 3.3 v. the reference voltage (v ref ) is 1 v. differential standards these standards require two i/os pe r signal (called a ?signal pair?) . logic values are determined by the potential difference between the lines, not wi th respect to ground. th is is why differential drivers and receivers have much better noise immunity than single-ended standards. the differential interface standards offer higher pe rformance and lower power consumption than their single-ended coun terparts. two i/o pins are used for each data transfer channel. both differential standards require resistor termination. lvpecl (low-voltage posit ive emitter coupled logic) lvpecl requires that one data bit be carried thro ugh two signal lines; th erefore, two pins are needed per input or output. it also requires external resisto r termination. th e voltage swing between the two signal lines is approximately 850 mv. when the power supply is +3.3 v, it is commonly referred to as low-voltage pecl (lvpec l). refer to the device datasheet for the full implementation of the lvpecl transmitter and receiver. lvds (low-voltage differential signal) lvds is a moderate-speed differ ential signaling syste m, in which the transmitter generates two different voltages that are compared at the receiver. lvds uses a di fferential driver connected to a terminated receiver through a constant-impedance transmission line. it requires that one data bit be carried through two sign al lines; therefore, the user will n eed two pins per input or output. it also requires external resistor termination. the vo ltage swing between the two signal lines is approximately 350 mv. v cci is 2.5 v. low-power flash devices co ntain dedicated circuitry supporting a high-speed lvds standard that has its own user specification. refer to the device datasheet for the full implementation of the lvds transmitter and receiver. figure 7-7 ? differential topology v cci device 1 gnd v ref outn outp inn inp v cci device 2 gnd v ref i/o structures in igloo and pro asic3 devices v1.1 7-13 blvds/m-lvds bus lvds (blvds) refers to bus interface circuits based on lvds technology. multipoint lvds (m-lvds) specifications extend the lvds sta ndard to high-performance multipoint bus applications. multidrop and multipoint bus config urations may contain any combination of drivers, receivers, and transceivers. actel lvds drivers pr ovide the higher drive current required by blvds and m-lvds to accommodate the lo ading. the driver requires series terminations for better signal quality and to control volt age swing. termination is also required at both ends of the bus, since the driver can be located anywhere on the bus. these configurations can be implemented using tribuf_lvds and bibuf_lvds macros along with appropriate termi nations. multipoint designs using actel lvds macros can achieve up to 200 mhz with a maximum of 20 loads. a sample application is given in figure 7-8 on page 7-13 . the input and output buffe r delays are available in the lvds sections in the datasheet. example: for a bus consisting of 20 equidistan t loads, the termi nations given in eq 7-1 provide the required differential volt age, in worst-case industrial operating conditions, at the farthest receiver: r s =60 , r t =70 , given z o =50 (2") and a z stub = 50 (~1.5"). eq 7-1 figure 7-8 ? a blvds/m-lvds multipoint appl ication using lvds i/o buffers ... r t r t bibuf_lvds r r s r s z 0 receiver +- z stub t r s r s z 0 transceiver +- r r s r s z 0 receiver +- t transceiver +- d r s r s z 0 driver +- en en en en en z stub z stub z stub z stub z stub z stub z stub z 0 z 0 z 0 z 0 r s r s z stub z stub z 0 z 0 z 0 z 0 i/o structures in iglo o and proasi c3 devices 7-14 v1.1 i/o features low-power flash devices support multiple i/o featur es that make board design easier. for example, an i/o feature like schmitt trigger in the proasi c3e input buffer saves the board space that would be used by an external schmitt trigger for a sl ow or noisy input signal. these features are also programmable for each i/o, which in turn gives flexibility in interfacin g with other components. the following is a detailed description of all available features in low-power flash devices. i/o programmable features low-power flash devices offer many flexible i/o features to support a wide variety of board designs. some of the features are prog rammable, with a range for selection. table 7-7 lists programmable i/o features and their ranges. hot-swap support a pull-up clamp diode must not be present in the i /o circuitry if the hot-sw ap feature is used. the 3.3 v pci standard requires a pull-up clamp diode on the i/o, so it cannot be selected if hot-swap capability is requir ed. the a3p030 device does no t support 3.3 v pci, so it is the only device in the proasic3 family that supports the hot-swap feat ure. all devices in the proasic3e family are hot- swappable. all standards except lvcmos 2.5/5.0 v and 3.3 v pci/pci-x suppor t the hot-swap feature. the hot-swap feature appears as a read-only check box in the i/ o attribute editor that shows whether an i/o is hot-sw appable or not. refer to power-up/-down behavior of proasic3/e devices for details on hot-swapping. hot-swapping (also called hot-plugging) is the operation of hot insertion or hot removal of a card in a powered-up system. the levels of hot-swap support and examples of related applications are described in table 7-8 on page 7-15 to table 7-11 on page 7-16 . the i/os also need to be configured in hot-insertion mode if hot- plugging compliance is requir ed. the agl030 and a3p030 devices have an i/o structure that allows the support of level 3 and level 4 hot-sw ap with only two levels of staging. table 7-7 ? programmable i/o features (user c ontrol via i/o attribute editor) feature description range slew control output slew rate high, low output drive (ma) output drive s trength 2, 4, 6, 8, 12, 16, 24 skew control output tristate enable delay option on, off resistor pull resistor pull circuit up, down, none input delay input delay off, 0?7 schmitt trigger schmitt trigger for input only on, off note: limitations of these features with respect to different devices are discussed in later sections. i/o structures in igloo and pro asic3 devices v1.1 7-15 table 7-8 ? hot-swap level 1 description cold-swap power applied to device no bus state ? card ground connection ? device circuitry connected to bus pins ? example application system and card with actel fpga chip are powered down, and the card is plugged into the system. then the power supplies are turned on for the system but not for the fpga on the card. compliance of igloo and proasic3 devices 30 k gate devices: compliant other igloo/proasic3 devi ces: compliant if bus switch used to isolate fpga i/os from rest of system iglooe/proasic3e devices: compliant i/os can but do not have to be set to hot-insertion mode. table 7-9 ? hot-swap level 2 description hot-swap while reset power applied to device yes bus state held in reset state card ground connection reset must be maintained for 1 ms before, during, and after insertion/removal. device circuitry connected to bus pins ? example application in the pci hot-plug specification, reset control circuitry isolates the ca rd busses until the card supplies are at their nominal operating levels and stable. compliance of igloo and proasic3 devices 30 k gate devices, all iglooe/proasic3e devices: compliant i/os can but do not have to be set to hot-insertion mode. other igloo/proasic3 devices: compliant i/o structures in iglo o and proasi c3 devices 7-16 v1.1 table 7-10 ? hot-swap level 3 description hot-swap wh ile bus idle power applied to device yes bus state held idle (no ongoing i/o processes during insertion/removal) card ground connection reset must be maintained for 1 ms before, during, and after insertion/removal. device circuitry connected to bus pins must remain glitch-fre e during power-up or power-down example application board bus shared with ca rd bus is "frozen," and there is no toggling activity on the bus. it is critical that the logic sta tes set on the bus signal not be disturbed during card insertion/removal. compliance of igloo and proasic3 devices 30 k gate devices, all iglooe/proasic3e devices: compliant with two levels of staging (first: gnd; second: all other pins) other igloo/proasic3 devices: compliant: option a ? two levels of staging (first: gnd; second: all other pins) together with bus switch on the i/os option b ? three levels of staging (first: gnd; second: supplies; third: all other pins) table 7-11 ? hot-swap level 4 description hot-swap on an active bus power applied to device yes bus state bus may have active i/o processes ongoing, but device being inserted or removed must be idle. card ground connection reset must be maintained for 1 ms before, during, and after insertion/removal. device circuitry connected to bus pins must remain glitch-fre e during power-up or power-down example application there is activity on th e system bus, and it is critical that the logic sta tes set on the bus signal not be disturbed during card insertion/removal. compliance of igloo and proasic3 devices 30 k gate devices, all iglooe/proasic3e devices: compliant with two levels of staging (first: gnd; second: all other pins) other igloo/proasic3 devices: compliant: option a ? two levels of staging (first: gnd; second: all other pins) together with bus switch on the i/os option b ? three levels of staging (first: gnd; second: supplies; third: all other pins) i/o structures in igloo and pro asic3 devices v1.1 7-17 igloo and proasic3 for boards and cards with three levels of staging, card power supplies must have time to reach their final values before the i/os are connecte d. pay attention to th e sizing of power supply decoupling capacitors on the card to ensure that the po wer supplies are not overloaded with capacitance. cards with three levels of staging should have the following sequence: ? grounds ? powers ? i/os and other pins for level 3 and level 4 compliance with the 30 k gate device, cards with two levels of staging should have the fo llowing sequence: ? grounds ? powers, i/os, and other pins cold-sparing support cold-sparing refers to the ability of a device to leav e system data undisturb ed when the system is powered up, while the component itself is powere d down, or when power supplies are floating. the resistor value is calculated based on the deco upling capacitance on a given power supply. the rc constant should be greater than 3 s. to remove resistor current during operation, it is suggested that the resistor be disconnected (e.g., with an nmos switch) from the po wer supply after the supply has reached its final value. refer to the power-up/-down behavior of proasic3/e devices chapter of the proasic3 and proasic3e handbooks for details on cold-sparing. cold-sparing means that a subsyste m with no power applied (usually a circuit board) is electrically connected to the system that is in operation. th is means that all input buffers of the subsystem must present very high input impedance with no po wer applied so as not to disturb the operating portion of the system. the 30 k gate devices fully supp ort cold-sparing, since the i/o clamp diode is always off (see table 7-12 on page 7-19 ). if the 30 k gate device is used in applications requiring cold-sparing, a discharge path from the power supply to ground should be provided. this can be done with a discharge resistor or a switched resistor. this is necessary because the 30 k gate devices do not have built-in i/o clamp diodes. for other igloo and proasic3 devices, since the i/ o clamp diode is always active, cold-s paring can be accomplished either by employing a bus switch to isolate th e device i/os from the rest of the system or by driving each i/o pin to 0 v. if th e resistor is chosen, the resistor value must be calculated based on decoupling capacitance on a given power supply on the board (this decoupling capacitance is in parallel with th e resistor). the rc time constant should ensure full discharge of supplies before cold-sparing func tionality is required. the resistor is necessary to ensure that the power pins are discharged to grou nd every time there is an interr uption of power to the device. iglooe and proasic3e devices support cold-sparing for all i/o configurations. standards, such as pci, that require i/o clamp diodes can also achiev e cold-sparing compliance, since clamp diodes get disconnected internally when the supplies are at 0 v. when targeting low-power applications, i/o cold-sparing may add additional current if a pin is configured with either a pull-up or pull-down resi stor and driven in the oppo site direction. a small static current is induced on each i/o pin when the pin is driven to a voltage opposite to the weak pull resistor. the current is eq ual to the voltage drop across the input pin divided by the pull resistor. refer to the "detailed i/o dc characterist ics" section of the appr opriate family datasheet for the specific pull resistor valu e for the corresponding i/o standard. for example, assuming an lvttl 3.3 v input pin is configured with a weak pull-up resistor, a current will flow through the pull-up resistor if the input pin is driven low. for lvttl 3.3 v, the pull-up resistor is ~45 k , and the resulting current is equal to 3.3 v / 45 k = 73 a for the i/o pin. this is true also wh en a weak pull-down is chos en and the input pin is driv en high. this current can i/o structures in iglo o and proasi c3 devices 7-18 v1.1 be avoided by driving the input low when a weak pull-down resistor is used and driving it high when a weak pull-up resistor is used. this current draw can occur in the following cases: ? in active and static modes: ? input buffers with pull-up, driven low ? input buffers with pull-down, driven high ? bidirectional buffers with pull-up, driven low ? bidirectional buffers with pull-down, driven high ? output buffers with pull-up, driven low ? output buffers with pull-down, driven high ? tristate buffers with pull-up, driven low ? tristate buffers with pull-down, driven high ? in flash*freeze mode: ? input buffers with pull-up, driven low ? input buffers with pull-down, driven high ? bidirectional buffers with pull-up, driven low ? bidirectional buffers with pull-down, driven high electrostatic discharge protection low-power flash devices are tested per jedec standard jesd22-a114-b. these devices contain clamp diodes at every i/o, global, and power pad. clamp diodes protect all device pads against damage from esd as we ll as from excessive voltage transients. all igloo and proasic3 devices are tested to th e following models: the human body model (hbm) with a tolerance of 2,000 v, the machine model ( mm) with a tolerance of 250 v, and the charged device model (cdm) with a tolerance of 200 v. each i/o has two clamp diodes. one diode has its positive (p) side connected to the pad and its negative (n) side connected to v cci . the second diode ha s its p side connected to gnd and its n side connected to the pad. during operation, these diod es are normally biased in the off state, except when transient voltage is significantly above v cci or below gnd levels. in 30 k gate devices, the first diode is always off. in other devices, the clamp diode is always on and cannot be switched off. by selecting the approp riate i/o configuration, the diode is turned on or off. refer to table 7-12 on page 7-19 for more information about the i/o standards and the clamp diode. the second diode is always connected to the pa d, regardless of the i/o configuration selected. i/o structures in igloo and pro asic3 devices v1.1 7-19 table 7-12 ? i/o hot-swap and 5 v input tolerance capa bilities in igloo an d proasic3 devices i/o assignment clamp diode 1 hot insertion 5 v input tolerance 2 input and output buffer agl030 and a3p030 other igloo and proasic3 devices agl030 and a3p030 other igloo and proasic3 devices agl030 and a3p030 other igloo and proasic3 devices 3.3 v lvttl/lvcmos no yes yes yes yes 2 yes 2 enabled/disabled 3.3 v pci, 3.3 v pci-x n/a yes n/a yes n/a yes 2 enabled/disabled lvcmos 2.5 v 5 no yes yes yes yes 2 yes 4 enabled/disabled lvcmos 2.5 v / 5.0 v 6 n/a yes n/a yes n/a yes 4 enabled/disabled lvcmos 1.8 v no yes yes yes no no enabled/disabled lvcmos 1.5 v no yes yes yes no no enabled/disabled differential, lvds/ blvds/m-lvds/ lvpecl n/a yes n/a yes n/a no enabled/disabled notes: 1. the clamp diode is always off fo r the agl030 and a3p030 device and always active for other igloo and proasic3 devices. 2. can be implemented with an external idt bus sw itch, resistor divider, or zener with resistor. 3. refer to table 7-8 on page 7-15 to table 7-11 on page 7-16 for device-compl iant information. 4. can be implemented with an external resistor and an in ternal clamp diode. 5. the lvcmos 2.5 v i/o standard is supported by th e 30 k gate devices only; select the lvcmos25 macro. 6. the lvcmos 2.5 v / 5.0 v i/o standard is supported by all igloo and proasic3 devices except 30 k gate devices; select the lvcmos5 macro. i/o structures in iglo o and proasi c3 devices 7-20 v1.1 5 v input and output tolerance igloo and proasic3 devices are both 5 v-input? and 5 v?output?tolerant if certain i/o standards are selected. table 7-5 on page 7-5 shows the i/o standards that su pport 5 v input tolerance. only 3.3 v lvttl/lvcmos standards support 5 v output tolerance. refer to the appropriate family datasheet for the detailed descriptio n and configuration information. this feature is not shown in the i/o attribute editor. 5 v input tolerance i/os can support 5 v input tole rance when lvttl 3.3 v, lvcmos 3.3 v, lvcmos 2.5 v, and lvcmos 2.5 v / 5.0 v configurations are used (see table 7-12 on page 7-19 ). there are four recommended solutions for achieving 5 v receiver tolerance (see figure 7-9 on page 7-21 to figure 7-12 on page 7-23 for details of board and macro setups). al l the solutions meet a common requirement of limiting the vo ltage at the input to 3.6 v or less. in fact , the i/o absolute maxi mum voltage rating is 3.6 v, and any voltage abov e 3.6 v may cause long-ter m gate oxide failures. solution 1 the board-level design mu st ensure that the reflected waveform at the pad does not exceed the limits provided in th e recommended operating conditions in the datasheet. this is a requirement to ensure long-term reliability. this scheme will also work for a 3.3 v pci/ pci-x conf iguration, but the internal diode should not be used for clamping, and the voltage must be limited by the two external resistors as explained below. relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. this solution requires two board resistors, as demonstrated in figure 7-9 on page 7-21 . here are some examples of possible resistor values (based on a simplified simula tion model with no line effects and 10 transmitter output resist ance, where rtx_out_high = (v cci ?v oh )/i oh and rtx_out_low = v ol /i ol ). example 1 (high spee d, high current): rtx_out_high = rtx_out_low = 10 r1 = 36 (5%), p(r1)min = 0.069 r2 = 82 (5%), p(r2)min = 0.158 imax_tx = 5.5 v / (82 0.95 + 36 0.95 + 10) = 45.04 ma t rise = t fall = 0.85 ns at c_pad_load = 10 pf (includes up to 25% safety margin) t rise = t fall = 4 ns at c_pad_load = 50 pf (i ncludes up to 25% safety margin) example 2 (low?medium sp eed, medium current): rtx_out_high = rtx_out_low = 10 r1 = 220 (5%), p(r1)min = 0.018 r2 = 390 (5%), p(r2)min = 0.032 imax_tx = 5.5 v / (220 0.95 + 390 0.95 + 10) = 9.17 ma t rise = t fall = 4 ns at c_pad_load = 10 pf (i ncludes up to 25% safety margin) t rise = t fall = 20 ns at c_pad_load = 50 pf (includes up to 25% safety margin) other values of resistors are also allowed as long as the resistors ar e sized appropriat ely to limit the voltage at the receiving end to 2.5 v < vin (rx) < 3.6 v when the transmitt er sends a logic 1. this range of vin_dc(rx) must be assured for an y combination of transmitter supply (5 v 0.5 v), transmitter output resistance, and board resistor tolerances. i/o structures in igloo and pro asic3 devices v1.1 7-21 temporary overshoots are allowe d according to the overshoot and undersh oot table in the datasheet. solution 2 the board-level design mu st ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. this is a requirement to ensure long-term reliability. this scheme will also work for a 3.3 v pci/pci-x configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the external resistors and zener, as shown in figure 7-10 . relying on the diode clamping would create an excessive pad dc voltage of 3.3v+0.7v=4v. figure 7-9 ? solution 1 figure 7-10 ? solution 2 solution 1 5.5 v 3.3 v requires two board resistors, lvcmos 3.3 v i/os i/o input rext1 rext2 solution 2 5.5 v 3.3 v requires one board resistor, one zener 3.3 v diode, lvcmos 3.3 v i/os i/o input rext1 zener 3.3 v i/o structures in iglo o and proasi c3 devices 7-22 v1.1 solution 3 the board-level design mu st ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the datasheet. this is a requirement to ensure long-term reliability. this scheme will also work for a 3.3 v pci/pci-x configuration, but the internal diode should not be used for clamping, and the voltage must be limited by the bus switch, as shown in figure 7-11 . relying on the diode clamping would create an excessive pad dc voltage of 3.3 v + 0.7 v = 4 v. figure 7-11 ? solution 3 solution 3 requires a bus switch on the board, lvttl/lvcmos 3.3 v i/os. i/o input 3.3 v 5.5 v 5.5 v bus switch idtqs32x23 i/o structures in igloo and pro asic3 devices v1.1 7-23 solution 4 the board-level design mu st ensure that the reflected waveform at the pad does not exceed the voltage overshoot/undershoot limits provided in the ds. this is a requirement to ensure long-term reliability. figure 7-12 ? solution 4 solution 4 2.5 v 5.5 v 2.5 v requires one board resistor. available for lvcmos 2.5 v / 5.0 v. i/o input rext on-chip clamp diode i/o structures in iglo o and proasi c3 devices 7-24 v1.1 5 v output tolerance igloo and proasic3 i/os must be set to 3.3 v lvttl or 3.3 v lvcmos mode to reliably drive 5 v ttl receivers. it is also critical that there be no ex ternal i/o pull-up resistor to 5 v, since this resistor would pull the i/o pad voltage beyond the 3.6 v absolute maximum value and consequently cause damage to the i/o. when set to 3.3 v lvttl or 3.3 v lvcmos mode, the i/os can directly drive signals into 5 v ttl receivers. in fact, v ol =0.4v and v oh = 2.4 v in both 3.3 v lvttl and 3.3 v lvcmos modes exceeds the v il =0.8v and v ih = 2 v level requirements of 5 v ttl receivers. therefore, level 1 and level 0 will be recognized correc tly by 5 v ttl receivers. schmitt trigger a schmitt trigger is a buffer used to convert a sl ow or noisy input signal into a clean one before passing it to the fpga. using schmitt trigger buff ers guarantees a fast, noise-free input signal to the fpga. the schmitt trigger is avai lable for the lvttl, lvcmos, and 3.3 v pci i/o standards. this feature can be implemented by using a physical design constr aints (pdc) command ( table 7-5 on page 7-5 ) or by selecting a check box in the i/o a ttribute editor in desi gner. the check box is cleared by default. table 7-13 ? comparison table for 5 v?compliant receiver solutions solution board components speed current limitations 1 two resistors low to high 1 limited by transmitter's drive strength 2 resistor and zener 3.3 v medium limit ed by transmitter's drive strength 3 bus switch high n/a 4 minimum resistor value 2,3,4,5 r = 47 at t j = 70c r = 150 at t j = 85c r = 420 at t j = 100c medium maximum diode current at 100% du ty cycle, signal constantly at 1 52.7 ma at t j = 70c / 10-year lifetime 16.5 ma at t j = 85c / 10-year lifetime 5.9 ma at t j = 100c / 10-year lifetime for duty cycles other than 100%, the currents can be increased by a factor of 1 / (duty cycle). example: 20% duty cycle at 70c maximum current = (1 / 0.2) 52.7 ma = 5 52.7 ma = 263.5 ma notes: 1. speed and current consumption increase as the board resistance values decrease. 2. resistor values ensure i/o diode long-term reliability. 3. at 70c, customers could still use 420 on every i/o. 4. at 85c, a 5 v solution on every other i/o is permitted, since the resistance is lower (150 ) and the current is higher. also, the designer can still use 420 and use the solution on every i/o. 5. at 100c, the 5 v solution on every i/o is permitted, since 420 are used to limit the current to 5.9 ma. i/o structures in igloo and pro asic3 devices v1.1 7-25 selectable skew between output buffer enable and disable times low-power flash devices have a configurable skew block in the output buffer circuitry that can be enabled to delay output buffer a ssertion without affecting deassert ion time. since this skew block is only available for the oe signal, the feature can be used in tristate and bidirectional buffers. a typical 1.2 ns delay is added to the oe signal to prevent potential bus co ntention. refer to the appropriate family datasheet for detail ed timing diagrams and descriptions. the skew feature is available for all i/o standards. this feature can be implemented by using a pdc command ( table 7-5 on page 7-5 ) or by selecting a check box in the i/o attribute editor in designer. the check box is cleared by default. the configurable skew block is us ed to delay output buffer asse rtion (enable) without affecting deassertion (disable) time. figure 7-13 ? block diagram of output enable path figure 7-14 ? timing diagram (option 1: bypasses skew circuit) enable (out) skew circuit output enable (from fpga core) i/o output buffers enable (in) mux skew select enable (in) enable (out) less than 0.1 ns less than 0.1 ns i/o structures in iglo o and proasi c3 devices 7-26 v1.1 at the system level, the skew circuit can be used in applications where tr ansmission activities on bidirectional data lines need to be coordinated. this circuit, when selected, provides a timing margin that can prevent bus contention and subs equent data loss and/or transmitter over-stress due to transmitter-to-tran smitter current shorts. figure 7-16 presents an example of the skew circuit implementation in a bidirectional communication system. figure 7-17 on page 7-27 shows how bus contention is created, and figure 7-18 on page 7-27 shows how it can be avoided with the skew circuit. figure 7-15 ? timing diagram (option 2: enables skew circuit) enable (in) enable (out) 1.2 ns (typical) less than 0.1 ns figure 7-16 ? example of implementation of s kew circuits in bidirectional tr ansmission systems using igloo or proasic3 devices transmitter 1: proasic3 i/o transmitter 2: generic i/o enable(t2) en (b1) en (b2) routing delay (t1) routing delay (t2) en (r1) enable (t1) skew or bypass skew bidirectional data bus transmitter enable/ disable i/o structures in igloo and pro asic3 devices v1.1 7-27 figure 7-17 ? timing diagram (byp asses skew circuit) figure 7-18 ? timing diagram (with skew circuit selected) en (b1) en (b2) enable (r1) transmitter 1: on enable (t2) transmitter 2: on enable (t1) bus contention transmitter 1: off transmitter 1: off transmitter 2: off en (b1) en (b2) transmitter 1: on enable (t2) transmitter 2: on transmitter 2: off enable (t1) result: no bus contention transmitter 1: off transmitter 1: off i/o structures in iglo o and proasi c3 devices 7-28 v1.1 i/o register combining every i/o has several embedded registers in the i/o tile that are close to the i/o pads. rather than using the internal regist er from the core, the user has the opti on of using these registers for faster clock-to-out timing, and external hold and setup. when combining th ese registers at the i/o buffer, some architectural rules must be met. provided th ese rules are met, the user can enable register combining globally during compile (as shown in the "compiling the design" section in the i/o software control in lo w-power flash devices section of the handbook). this feature is supporte d by all i/o standards. rules for registered i/o function: 1. the fanout between an i/o pin (d, y, or e) an d a register must be equa l to one for combining to be considered on that pin. 2. all registers (input, ou tput, and output enable) connected to an i/o must share the same clear or preset function: ? if one of the registers has a clr pin, all th e other registers that are candidates for combining in the i/o must have a clr pin. ? if one of the registers has a pre pin, all th e other registers that are candidates for combining in the i/o must have a pre pin. ? if one of the registers has neither a clr nor a pre pin, all the other registers that are candidates for combining must have neither a clr nor a pre pin. ? if the clear or preset pins are present, they must have the same polarity. ? if the clear or preset pins are present, th ey must be driven by the same signal (net). 3. registers connected to an i/o on the output and output enable pins must have the same clock and enab le function: ? both the output and output en able registers must have an e pin (clock enable), or none at all. ? if the e pins are present, they must have th e same polarity. the clk pins must also have the same polarity. in some cases, the user may want registers to be combined with the input of a bibuf while maintaining the output as-is. this can be achieved by using pdc commands as follows: set_io i/o structures in igloo and pro asic3 devices v1.1 7-29 the slew rate can be implemen ted by using a pdc command ( table 7-5 on page 7-5 ), setting "high" or "low" in the i/o attribute editor in designer, or instantiating a special i/o macro. the default slew rate value is "high." igloo and proasic3 devices support output slew rate control: high and low. actel recommends the high slew rate option to minimize the propagation delay. this high-speed option may introduce noise into the system if appropriate signal integrit y measures are not adopted. selecting a low slew rate reduces this kind of noise but adds some de lays in the system. low slew rate is recommended when bus transients are expected. output drive the output buffers of igloo and proasic3 devices can provide multiple drive strengths to meet signal integrity requirements. the lvttl and lvcmos (except 1.2 v lvcmos) standards have selectable drive strengths. other sta ndards have a preset value. drive strength should also be se lected according to the design requirements and noise immunity of the system. the output slew rate and multiple drive strength controls are available in lvttl/lvcmos 3.3 v, lvcmos 2.5 v, lvcmos 2.5 v / 5.0 v input, lvcmos 1.8 v, and lvcmos 1.5 v. all other i/o standards have a high output slew rate by default. for 30 k gate devices, refer to table 7-14 . for other proasic3 and igloo devices, refer to table 7-15 through table 7-16 on page 7-30 for more information about th e slew rate and drive strength specification. refer to table 7-4 on page 7-4 for i/o bank type definitions. there will be a difference in ti ming between the standard plus i/o banks and the advanced i/o banks. refer to the i/o timing tables in th e datasheet for the standards supported by each device. table 7-14 ? igloo and proasic3 output drive and slew for standard i/o bank type (for 30 k gate devices) i/o standards 2 ma 4 ma 6 ma 8 ma slew lvttl/lvcmos 3.3 v ?? ? ? high low lvcmos 2.5 v ?? ? ? high low lvcmos 1.8 v ?? ? ? high low lvcmos 1.5 v ? ???highlow table 7-15 ? igloo and proasic3 output drive and slew for standard plus i/o bank type i/o standards 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma slew lvttl ??? ??? high low lvcmos 3.3 v ??? ??? high low lvcmos 2.5 v ? ? * ? ? * ? ?highlow lvcmos 1.8 v ?? ? ? ? ? high low lvcmos 1.5 v ?? ? ???high low note: *not available in automotive devices. i/o structures in iglo o and proasi c3 devices 7-30 v1.1 simultaneously switching output s (ssos) and printed circuit board layout each i/o voltage bank has a separate ground and power plane for input and output circuits (vmv/gndq for inpu t buffers and v cci /gnd for output buff ers). this isolation is necessary to minimize simultaneous switchin g noise from the input and output (ssi and sso). the switching noise (ground bounce and power bounce) is generated by the output buffers and transferred into input buffer circuits, and vice versa. since voltage bounce originates on the package inductance, the vmv and v cci supplies have separate package pin assignmen ts. for the same reason, gnd and gndq also have separate pin assignments. the vmv and v cci pins must be shorted to each other on the board. also, the gnd and gndq pins must be shorted to each other on the board. th is will prevent unwanted current draw from the power supply. ssos can cause signal integrity problems on adjacent signals that are not part of the sso bus. both inductive and capacitive coupling parasitics of bo nd wires inside packages and of traces on pcbs will transfer noise from sso busses onto signals adjace nt to those busses. additionally, ssos can produce ground bounce noise and v cci dip noise. these two noise types are caused by rapidly changing currents through gnd and v cci package pin inductances during switching activities ( eq 7-2 and eq 7-3 ). ground bounce noise voltage = l(gnd) di/dt eq 7-2 v cci dip noise voltage = l(v cci ) di/dt eq 7-3 any group of four or more input pins switching on the same clock edge is considered an sso bus. the shielding should be done both on the board and inside the package unless otherwise described. in-package shielding can be achieved in several ways; the required shielding will vary depending on whether pins next to the sso bus are lvttl/lvcmos inputs, lvttl/lvcmos outputs, or gtl/sstl/hstl/lvds/lvpecl inputs and outputs. board traces in the vicinity of the sso bus have to be adequately shielded from mutu al coupling and inductive noise that can be generated by the sso bus. also, noise generated by the sso bus needs to be reduced inside the package. pcbs perform an important function in feeding sta ble supply voltages to the ic and, at the same time, maintaining signal integrity between devices. key issues that need to be considered are as follows: ? power and ground plane design and decoupling network design ? transmission line reflections and terminations for extensive data per package on the sso and pcb issues, refer to proasic3/e sso and pin placement an d guidelines chapter of the handbook. table 7-16 ? igloo and proasic3 output drive and slew for advanced i/o bank type i/o standards 2 ma 4 ma 6 ma 8 ma 12 ma 16 ma 24 ma slew lvttl ??????? high low lvcmos 3.3 v ??????? high low lvcmos 2.5 v ? ? * ? ? * ??? high low lvcmos 2.5/5.0 v ? ? * ? ? * ??? high low lvcmos 1.8 v ?????? ? high low lvcmos 1.5 v ????? ? ? high low note: not available in automotive devices. i/o structures in igloo and pro asic3 devices v1.1 7-31 i/o software support in actel's libero ide software, default settings have been defi ned for the various i/o standards supported. changes can be made to the default settings via the use of attributes; however, not all i/o attributes are applicable for all i/o standards. table 7-17 list the valid i/o attributes that can be manipulated by the user for each i/o standard. single-ended i/o standards in low-power flash devices support up to five different drive strengths. table 7-18 lists the default values for the above selectab le i/o attributes as we ll as those that are preset for that i/o standard. see table 7-14 on page 7-29 to table 7-16 on page 7-30 for slew and out_drive settings. table 7-17 ? igloo and proasic3 i/o attributes vs. i/o standard applications i/o standard slew (output only) out_drive (output only) skew (all macros with oe) res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v ?? ? ? ? ? lvcmos 2.5 v ?? ? ? ? ? lvcmos 2.5/5.0 v ?? ? ? ? ? lvcmos 1.8 v ?? ? ? ? ? lvcmos 1.5 v ?? ? ? ? ? pci (3.3 v) ??? pci-x (3.3 v) ???? lvds, blvds, m-lvds ?? lvpecl ? note: applies to all 30 k gate devices. table 7-18 ? igloo and proasic3 i/ o default attributes i/o standards slew (output only) out_drive (output only) skew (tribuf and bibuf only) res_pull out_load (output only) combine_register lvttl/lvcmos 3.3 v see table 7-14 on page 7-29 to table 7-16 on page 7-30 . see table 7-14 on page 7-29 to table 7-16 on page 7-30 . off none 35 pf ? lvcmos 2.5 v off none 35 pf ? lvcmos 2.5/5.0 v off none 35 pf ? lvcmos 1.8 v off none 35 pf ? lvcmos 1.5 v off none 35 pf ? pci (3.3 v) off none 10 pf ? pci-x (3.3 v) off none 10 pf ? lvds, blvds, m-lvds off none 0 pf ? lvpecl off none 0 pf ? i/o structures in iglo o and proasi c3 devices 7-32 v1.1 user i/o naming convention igloo and proasic3 due to the comprehensive and flex ible nature of igloo and proasi c3 device user i/os, a naming scheme is used to show the details of each i/o ( figure 7-19 on page 7-33 and figure 7-20 on page 7-33 ). the name identifies to which i/o bank it be longs, as well as pair ing and pin polarity for differential i/os. i/o nomenclature = ff/gmn/iouxwby gmn is only used for i/os that also have ccc access?i.e., global pins. ff = indicates the i/o dedicated for the flas h*freeze mode activation pin in igloo and proasic3l devices only g=global m = global pin location associated with each ccc on the device: a (northwest corner), b (northeast corner), c ( east middle), d (southeast corner), e (southwest corner), and f (west middle) n = global input mux and pin number of the associated global location m?either a0, a1, a2, b0, b1, b2, c0, c1 , or c2. refer to global resources in acte l low-power flash devices for information about the three input pins per clock source mux at ccc location m. u = i/o pair number in the bank, starting at 00 from the northwest i/o bank and proceeding in a clockwise direction x = p or u (positive), n or v (negative) for differential pairs, or r (regular?single-ended) for the i/os that support single-end ed and voltage-referenced i/o standards only. u (positive) or v (negative)?for lvds, ddr lvds, blvds, an d m-lvds only?restricts the i/o differential pair from being selected as an lvpecl pair. w = d (differential pair), p (pair), or s (single-ende d). d (differential pair) if both members of the pair are bonded out to adjacent pins or are sepa rated only by one gnd or nc pin; p (pair) if both members of the pair are bonded out but do not meet the adjacency requirement; or s (single-ended) if the i/o pair is not bonded ou t. for differential pairs (d), adjacency for ball grid packages means only ve rtical or horizontal. diagonal adjacency does not meet the requirements for a tru e differential pair. b = bank y = bank number (0?3). the bank number starts at 0 from the no rthwest i/o bank and proceeds in a clockwise direction. i/o structures in igloo and pro asic3 devices v1.1 7-33 note: the 30 k gate devices do not support a pll (v complf and v ccplf pins). figure 7-19 ? naming conventions of igloo and proasic3 devices with two i/o banks ? top view figure 7-20 ? naming conventions of igloo and proasic3 devices with four i/o banks ? top view ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c" agl030/a3p030 agl060/a3p060 agl125/a3p125 gnd v cc gnd v cci b1 v cc gnd v cci b0 bank 1 bank 1 bank 0 bank 0 bank 1 bank 0 v complf v ccplf gnd v cc v cci b1 gnd gnd v cc v cci b0 gnd vmv1 gndq gnd gnd v cci b1 v cci b1 v cc v cci b1 v cc gnd vmv1 gndq gnd tck tdi tms v jtag trst tdo v pump gnd gnd gndq vmv0 gnd vcc gnd v cci b0 v cci b0 vcc v cci b0 gnd vmv0 gndq a3p250 a3p400 a3p600 a3p1000 gnd vcc gnd v cci b3 bank 3 bank 3 bank 1 bank 1 bank 2 bank 0 v complf v ccplf gnd v cc v cci b3 gnd vmv3 gndq gnd gnd v cci b2 v cci b2 v cc v cci b2 v cc gnd vmv2 gndq gnd tck tdi tms v jtag trst tdo v pump gnd gnd v cc v cci b1 gnd v cc gnd v cci b1 gnd gndq vmv1 v cc v cci b0 gnd v cc v cci b0 gnd v cci b0 gnd vmv0 gndq ccc "a" ccc "e" ccc/pll "f" ccc "b" ccc "d" ccc "c" i/o structures in iglo o and proasi c3 devices 7-34 v1.1 board-level considerations low-power flash devices have robust i/o featur es that can help in reducing board-level components. the devices offer si ngle-chip solutions, which makes the board layout simpler and more immune to signal integrity issues. although, in ma ny cases, these devices resolve board-level issues, special attention should always be given to overall signal integrity. this section covers important board-level considerations to facilitate optimum device performance. termination proper termination of all signal s is essential for good signal quality. nonterminated signals, especially clock signals, can cause malfunctioning of the device. for general termination gu idelines, refer to the board-level considerations application note for actel fpgas. also refer to pin descriptions for termination requirem ents for specific pins. low-power flash i/os are equipped with on-chip pu ll-up/-down resistors. the user can enable these resistors by instantiating them either in the top level of the design (refer to the igloo, fusion, and proasic3 macro library guide for the available i/o macros wi th pull-up/-down) or in the i/o attribute editor in designer if generic input or output buffers are instantiated in the top level. unused i/o pins are configured as inputs with pull-up resistors. as mentioned earlier, low-power flash devices ha ve multiple programmable drive strengths, and the user can eliminate unwanted overshoot an d undershoot by adjustin g the drive strengths. power-up behavior low-power flash devices are power-up/-down friendly; i.e., no particular sequ encing is required for power-up and power-down. this eliminates extra board componen ts for power-up sequencing, such as a power-up sequencer. during power-up, all i/os are tri stated, irrespective of i/o macro type (input buffers, output buffers, i/o buffers with weak pull-ups or weak pull-downs, etc.). once i/os become activated, they are set to the user-selected i/o macros. refer to the power-up/-down behavior of proasic3/e devices chapter of the proasic3 and proasic3e handbooks for details. drive strength low-power flash devices have up to seven prog rammable output drive strengths. the user can select the drive strength of a particular output in the i/o attribute editor or can instantiate a specialized i/o macro, su ch as outbuf_s_12 (slew = low, out_drive = 12 ma). the maximum available drive strength is 24 ma pe r i/o. though no i/o should be forced to source or sink more than 24 ma indefinitely, i/os may handle a higher amount of current (refer to the device ibis model for maximum so urce/sink current) during signal transition (ac current). every device package has its own power dissipation lim it; hence, power calculation must be performed accurately to determine how much current can be tolerate d per i/o within that limit. i/o interfacing low-power flash devices are 5 v?input? and 5 v?output?tolerant without adding any extra circuitry. along with other low-vol tage i/o macros, this 5 v tolera nce makes these devices suitable for many types of boar d component interfacing. i/o structures in igloo and pro asic3 devices v1.1 7-35 table 7-19 shows some high-level in terfacing examples using low-power flash devices. conclusion igloo and proasic3 support for multiple i/o st andards minimizes board- level components and makes possible a wide variety of applications. th e actel designer software, integrated with actel libero ide, presents a clear visual display of i/o as signments, allowing users to verify i/o and board- level design requirements before programming th e device. the igloo and proasic3 device i/o features and functionalities en sure board designers can produce low-cost and low-power fpga applications fulfilling the complexiti es of contemporary design needs. table 7-19 ? high-level interface examples interface clock i/o type frequency type signals in signals out data i/o gm src sync 125 mhz lvttl 8 8 125 mbps tbi src sync 125 mhz lvttl 10 10 125 mbps xsbi src sync 644 mhz lvds 16 16 644 mbps xgmi src sync ddr 156 mhz hstl1 32 32 312 mbps flexbus 3 sys sync 104 mhz lvttl 32 32 104 pos-phy3/spi-3 sys syn c 104 lvttl 8,16,32 8,16,32 104 mbps flexbus 4/spi-4.1 src sync 200 mhz hstl1 16,64 16,64 200 mbps pos-phy4/spi-4.2 src sync ddr 311 mhz lvds 16 16 622 mbps sfi-4.1 src sync 622 mhz lvds 16 16 622 mbps csix l1 sys sync 250 mhz hstl1 32,64,96,128 32,64,96,128 250 mbps hyper transport sys sync ddr 800 mhz lvds 2,4,8,16 2,4,8,16 1.6 gbps rapid i/o parallel sys sync ddr 250 mhz ? 1 ghz lvds 8,16 8,16 2 gbps star fabric cdr lvds 4 4 622 mbps note: sys sync = system synchr onous clocking, src sync = source sync hronous clocking, and cdr = clock and data recovery. i/o structures in iglo o and proasi c3 devices 7-36 v1.1 related documents handbook documents board-level considerations http://www.actel.com/documents/boardlevelcons_an.pdf ddr for actel?s low- power flash devices http://www.actel.com/documents/lpd_ddr_hbs.pdf flash*freeze technology an d low-power modes in iglo o and proasic3l devices http://www.actel.com/documen ts/lpd_flashfreeze_hbs.pdf global resources in actel low-power flash devices http://www.actel.com/documents/lpd_global_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions.hbs.pdf power-up/-down behavior of proasic3/e devices http://www.actel.com/documents/ proasic3_e_powerup_hbs.pdf proasic3/e sso and pin placement an d guidelines http://www.actel.c om/documents/pa 3_e_sso_hbs.pdf user?s guides actel libero ide user?s guide http://www.actel.com/documents/libero_ug.pdf igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf smartgen core reference guide http://www.actel.com/documents/genguide_ug.pdf i/o structures in igloo and pro asic3 devices v1.1 7-37 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-009-1 revised march 2008 list of changes the following table lists critical changes that were made in the current ve rsion of the document. previous version changes in current version (v1.1) page v1.0 (january 2008) originally, this document contained information on all igloo and proasic3 families. with the addition of new fa milies and to highlight the differences between the features, the document ha s been separated into 3 documents: this document contains information specific to igloo, proasic3, and proasic3l. i/o structures in iglooe and proasic3e devices contains information specific to iglooe, proasic3e, and proasic3el i/o features. i/o structures in igloo plus devices contains information specific to igloo plus i/o features. n/a v1.1 8-1 i/o software control in low-power flash devices 8 ? i/o software control in low-power flash devices actel fusion, ? igloo, ? and proasic ? 3 i/os provide more design flexibility, allowing the user to control specific features by enabling certain i/o standards. some features are selectable only for certain i/o standards, whereas others are available fo r all i/o standards. for example, slew control is not supported by differential i/o standards. conve rsely, i/o register combinin g is supported by all i/o standards. for detailed information about whic h i/o standards and features are available on each device and each i/o type, refer to the i/o structures sectio n of the handbook for the device you are using. figure 8-1 shows the various points in the software de sign flow where a user can provide input or control of the i/o selection and parameters. a de tailed description is provided throughout this document. figure 8-1 ? user i/o assignment flow chart design entry 1. i/o macro using smartgen 2. i/o buffer cell schematic entry 3. instantiating i/o library macro in hdl code 4. generic buffer using 1, 2, 3 method 5. synthesis 6. compile 6.1 i/o assignments by pdc import 7. i/o assignments by multi-view navigator (mvn) i/o standard selection for generic i/o macro i/o standards and v ref assignment by i/o bank assigner i/o attribute selection for i/o standards 8. layout and other steps i/o software control in low-power flash devices 8-2 v1.1 igloo and proasic3 i/o support the low-power flash families listed in table 8-1 support i/os and the fu nctions described in this document. actel's low-power flas h devices (listed in table 8-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the ab ility to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 8-1 . where the information applies to only one fami ly or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 8-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 8-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1.2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher de nsity, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fp gas qualified for automotive applications automotive proasic3 dc and switching characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. i/o software control in low-power flash devices v1.1 8-3 software-controlled i/o attributes users may modify these programmable i/o attribut es using the i/o attribute editor. modifying an i/o attribute may result in a change of state in designer. table 8-2 details which steps have to be re- run as a function of mo dified i/o attribute. table 8-2 ? designer state (resulting from i/o attribute modification) i/o attribute designer states compile layout fuse timing power slew control no no yes yes yes output drive (ma) no no yes yes yes skew control no no yes yes yes resistor pull no no yes yes yes input delay no no yes yes yes schmitt trigger no no yes yes yes out_load no no no yes yes combine_register yes yes n/a n/a n/a notes: 1. no = remains the same, yes = re-r un the step, n/a = not applicable 2. skew control and input delay do not apply to igloo plus. i/o software control in low-power flash devices 8-4 v1.1 implementing i/os in actel software actel libero ? integrated design environmen t (ide) is integrated with de sign entry tools such as the smartgen macro builder, the viewdraw schemati c entry tool, and an hdl editor. it is also integrated with the synthesis and designer tools. in this section, all necessary steps to implement the i/os are discussed. design entry there are three ways to implement i/os in a design: 1. use the smartgen macro builder to configure i/os by generating specific i/o library macros and then instantiating th em in top-level code. this is especially useful when creating i/o bus structures. 2. use an i/o buffer cell in a schematic design. 3. manually instantiate specific i/o macros in the top-level code. if technology-specific macros, su ch as inbuf_lvcmos33 and outbu f_pci, are used in the hdl code or schematic, the user will not be able to change the i/ o standard later on in designer. if generic i/o macros are used, such as inbuf, outbuf, tribuf, clkbuf, and bibu f, the user can change the i/o standard using the designer i/o attribute editor tool. using smartgen for i/o configuration the smartgen tool in libero id e provides a gui-based method of configuring the i/o attributes. the user can select certain i/o attributes while co nfiguring the i/o macro in smartgen. the steps to configure an i/o macro with specif ic i/o attributes are as follows: 1. open libero ide. 2. on the left hand side of the catalog view, select i/o , as shown in figure 8-2 . figure 8-2 ? smartgen catalog i/o software control in low-power flash devices v1.1 8-5 3. expand the i/o section and do uble-click one of the options ( figure 8-3 ). 4. double-click any of the varieties. the i/o create core window opens ( figure 8-4 ). as seen in figure 8-4 , there are five tabs to configure the i/ o macro: input buffers, output buffers, bidirectional buffers, tristate buffers, and ddr. input buffers there are two variations : regular and special. if the regular variation is selected, only the width (1 to 128) needs to be entered. the default value for width is 1. the special variation has width, technology, voltage level, and resistor pull-up/-down options (see figure 8-4 ). all the i/o standards and supply voltages (v cci ) supported for the device family are available for selection. figure 8-3 ? expanded i/o section figure 8-4 ? i/o create core window i/o software control in low-power flash devices 8-6 v1.1 output buffers there are two variations : regular and special. if the regular variation is selected, only the width (1 to 128) needs to be entered. the default value for width is 1. the special variation has width, technology, output drive, and slew rate options. bidirectional buffers there are two variations : regular and special. the regular variation has enable polarity (active hi gh, active low) in addition to the width option. the special variation has width, technology, output dr ive, slew rate, and resistor pull-up/-down options. tristate buffers same as bidirectional buffers. ddr there are eight variations: ddr wi th regular input buffers, specia l input buffers, regular output buffers, special output buffers, regular trista te buffers, special tristate buffers, regular bidirectional buffers, and special bidirectional buffers. these variations resemble the options of the previous i/o ma cro. for example, the special input buffers variation has width, technology, voltage level, and resistor pull-up/-down options. ddr is not available on igloo plus devices. 5. once the desired configuration is selected, click the generate button. the generate core window opens ( figure 8-5 ). 6. enter a name for the macro. click ok . the core will be generated and saved to the appropriate location with in the project files ( figure 8-6 on page 8-7 ). 7. instantiate the i/o macr o in the top-level code. the user must instantiate the ddr_reg or dd r_out macro in the design. use smartgen to generate both these macros and then instantia te them in your top level. to combine the ddr macros with the i/o, th e following rules must be met: figure 8-5 ? generate core window i/o software control in low-power flash devices v1.1 8-7 rules for the ddr i/o function ? the fanout between an i/o pin (d or y) and a ddr (ddr_reg or ddr_out) macro must be equal to one for th e combining to happen on that pin. ? if a ddr_reg macro and a ddr_out macro are combined on the same bidirectional i/o, they must share the same clear signal. ? registers will not be combined in an i/o in the presence of ddr combining on the same i/o. using the i/o buffe r schematic cell libero ide includes the viewdraw schematic entry too l. using viewdraw, the user can insert any supported i/o buffer cell in the top-level schematic. figure 8-6 shows a top-level schematic with different i/o buffer cells. when synthesized, the netlist will contain the same i/o macro. figure 8-6 ? i/o buffer schematic cell usage i/o software control in low-power flash devices 8-8 v1.1 instantiating in hdl code all the supported i/o macros can be instantiat ed in the top-level hdl code (refer to the igloo, fusion, and proasic3 macro library guide for a detailed list of all i/o macros). the following is an example: library ieee; use ieee.std_logic_1164.all; library proasic3e; entity top is port(in2, in1 : in std_logic; out1 : out std_logic); end top; architecture def_arch of top is component inbuf_lvcmos5u port(pad : in std_logic := 'u'; y : out std_logic); end component; component inbuf_lvcmos5 port(pad : in std_logic := 'u'; y : out std_logic); end component; component outbuf_sstl3_ii port(d : in std_logic := 'u'; pad : out std_logic); end component; other component ?.. signal x, y, z??.other signals : std_logic; begin i1 : inbuf_lvcmos5u port map(pad => in1, y =>x); i2 : inbuf_lvcmos5 port map(pad => in2, y => y); i3 : outbuf_sstl3_ii port map(d => z, pad => out1); other port mapping? end def_arch; synthesizing the design libero ide integrates with the synplify ? synthesis tool. other synthesis tools can also be used with libero ide. refer to the actel libero ide user?s guide or libero ide online help for details on how to set up the libero ide tool profile with synthesis tools from other vendors. during synthesis, the following rules apply: ? generic macros: ? users can instantiate generic inbuf, outbuf, tribuf, and bibuf macros. ? synthesis will automatically infer generic i/o macros. ? the default i/o technology for these macros is lvttl. ? users will need to use the i/ o attribute editor in design er to change the default i/o standard if needed (see figure 8-7 on page 8-9 ). ? technology-specific i/o macros: ? technology-specific i/o macros, such as inbuf_lvcmo25 and outbuf_gtl25, can be instantiated in the design. synthesis will infer these i/o macros in the netlist. i/o software control in low-power flash devices v1.1 8-9 ? the i/o standard of technology-specific i/o macros cannot be changed in the i/o attribute editor (see figure 8-7 ). ? the user must instantiate differential i/o ma cros (lvds/lvpecl) in the design. this is the only way to use these standards in the design. ? to implement the ddr i/o function, the us er must instantiate a ddr_reg or ddr_out macro. this is the only way to use a ddr macro in the design. performing place-and- route on the design the netlist created by the synthe sis tool should now be import ed into designer and compiled. during compile, the user can specify the i/o plac ement and attributes by importing the pdc file. the user can also specify the i/o placement and at tributes using chipplanner and the i/o attribute editor, under mvn. defining i/o assignments in the pdc file a pdc file is a tcl script file specifying physic al constraints. this file can be imported to and exported from designer. table 8-3 shows i/o assignment constraint s supported in the pdc file. figure 8-7 ? assigning a different i/o standa rd to the generic i/o macro table 8-3 ? pdc i/o constraints command action example comment i/o banks setting constraints set_iobank sets the i/o supply voltage, v cci , and the input reference voltage, v ref , for the specified i/o bank. set_iobank bankname [-vcci vcci_voltage] [-vref vref_voltage] set_iobank bank7 -vcci 1.50 -vref 0.75 must use in case of mixed i/o voltage (v cci ) design set_vref assigns a v ref pin to a bank. set_vref -bank [bankname] [pinnum] set_vref -bank bank0 685 704 723 742 761 must use if voltage- referenced i/os are used note: refer to the actel libero ide user?s guide for detailed rules on pdc naming and syntax conventions. i/o software control in low-power flash devices 8-10 v1.1 set_vref_defaults sets the default v ref pins for the specified bank. this command is ignored if the bank does not need a v ref pin. set_vref_defaults bankname set_vref_defaults bank2 i/o attribute constraint set_io sets the attributes of an i/o set_io portname [-pinname value] [-fixed value] [-iostd value] [-out_drive value] [-slew value] [-res_pull value] [-schmitt_trigger value] [-in_delay value] [-skew value] [-out_load value] [-register value] set_io in2 -pinname 28 -fixed yes -iostd lvcmos15 -out_drive 12 -slew high -res_pull none -schmitt_trigger off -in_delay off ?skew off -register no if the i/o macro is generic (e.g., inbuf) or technology- specific (inbuf_lvcmos25), then all i/o attributes can be assigned using this constraint. if netlist has an i/o macro that specifies one of its attributes, that attribute cannot be changed using this constraint, though other attributes can be changed. example: outbuf_s_24 (low slew, output drive 24 ma) slew and output drive cannot be changed. i/o region plac ement constraints define_region defines either a rectangular region or a rectilinear region define_region -name [region_name] -type [region_type] x1 y1 x2 y2 define_region -name test -type inclusive 0 15 2 29 if any number of i/os must be assigned to a particular i/o region, such a region can be created with this constraint. assign_region assigns a set of macros to a specified region assign_region [region name] [macro_name...] assign_region test u12 this constraint assigns i/o macros to the i/o regions. when assigning an i/o macro, pdc naming conventions must be followed if the macro name contains special characters; e.g., if the macro name is \\$1i19\\, the correct use of escape characters is \\\\\$1i19\\\\. table 8-3 ? pdc i/o constraints (continued) command action example comment note: refer to the actel libero ide user?s guide for detailed rules on pdc naming and syntax conventions. i/o software control in low-power flash devices v1.1 8-11 compiling the design during compile, a pdc i/o constraint file can be imported along with the netlist file. if only the netlist file is compiled, certain i/o assignments n eed to be completed before proceeding to layout. all constraints that can be entered in pdc can al so be entered using chipplanner, i/o attribute editor, and pineditor. there are certain rules that must be followed in implementing i/o register combining and the i/o ddr macro (refer to the i/o registers section of the handbook for the device that you are using and the "ddr" section on page 8-6 for details). provided these rules are met, the user can enable or disable i/o register combin ing by using the pdc command set_io portname ?register yes|no in the i/o attribute editor or selecting a ch eck box in the compile options dialog box (see figure 8-8 ). the compile options dialog box appears when the design is compiled for the first time. it can also be accessed by choosing options > compile during successive runs. i/o register combining is off by default. the pdc command ov errides the setting in th e compile options dialog box. understanding the compile report the i/o bank report is generated during compile and displayed in the log window. this report lists the i/o assignments necessary before layout can proceed. when designer is started, the i/o bank assigner to ol is run automatically if the layout command is executed. the i/o bank assigner takes care of the necessary i/o assignments. however, these assignments can also be made manually with mv n or by importing the pdc file. refer to the "assigning technologies and v ref to i/o banks" section on page 8-14 for further description. the i/o bank report can also be extra cted from designer by choosing to o l s > report and setting the report type to iobank . this report has the following tables: i/o function , i/o technology, i/o bank resource usage, and i/o voltage usage. this report is useful if th e user wants to do i/o assignments manually. figure 8-8 ? setting register combining during compile i/o software control in low-power flash devices 8-12 v1.1 i/o function figure 8-9 shows an example of the i/o function table included in the i/o bank report: this table lists the number of input i/os, output i/os, bidirectional i/os, and differential input and output i/o pairs that us e i/o and ddr registers. certain rules must be met to implement registe red and ddr i/o functions (refer to the i/o structures section of the handbook for the device you are using and the "ddr" section on page 8-6 ). i/o technology the i/o technology table (shown in figure 8-10 ) gives the values of v cci and v ref (reference voltage) for all the i/o standards used in the design. the user should assign these voltages appropriately. figure 8-9 ? i/o function table figure 8-10 ? i/o technology table i/o software control in low-power flash devices v1.1 8-13 i/o bank res ource usage this is an important portion of the report. th e user must meet the requirements stated in this table. figure 8-11 shows the i/o bank resource usage ta ble included in the i/o bank report: the example in figure 8-11 shows that none of the i/o macros is assigned to the bank because more than one v cci is detected. i/o voltage usage the i/o voltage usage table provides the number of v ref (e devices only) and v cci assignments required in the design. if the us er decides to make i/o assignme nts manually (pdc or mvn), the issues listed in this ta ble must be resolved be fore proceeding to layout. as stated earlier, v ref assignments must be made if there are any voltage-referenced i/os. figure 8-12 shows the i/o voltage usage table included in the i/o bank report. the table in figure 8-12 indicates that there are two voltage- referenced i/os used in the design. even though both of the voltage-referenc ed i/o technologies have the same v cci voltage, their v ref voltages are different. as a result, tw o i/o banks are needed to assign the v cci and v ref voltages. figure 8-11 ? i/o bank resource usage table figure 8-12 ? i/o voltage usage table i/o software control in low-power flash devices 8-14 v1.1 in addition, there are six single-end ed i/os used that have the same v cci voltage. since two banks are already assigned with the same v cci voltage and there are enough unused bonded i/os in those banks, the user does not ne ed to assign the same v cci voltage to another ba nk. the user needs to assign the other three v cci voltages to three more banks. assigning technologies and v ref to i/o banks low-power flash devices offer a wide variety of i/o standards, includ ing voltage-referenced standards. before proceeding to layout, each bank must have the required v cci voltage assigned for the correspondin g i/o technologies used for that ba nk. the voltage-referenced standards require the use of a reference voltage (v ref ). this assignment can be done manually or automatically. the following sections describe this in detail. manually assigning technologies to i/o banks the user can import the pdc at this point an d resolve this requirem ent. the pdc command is set_iobank [bank name] ?vcci [vcci value] another method is to use the i/o bank settings dialog box ( mvn > edit > i/o bank settings ) to set up the v cci voltage for the bank ( figure 8-13 ). figure 8-13 ? setting v cci for a bank i/o software control in low-power flash devices v1.1 8-15 the procedure is as follows: 1. select the bank to which you want v cci to be assigned from the choose bank list. 2. select the i/o standards for that bank. if you select any standard, the tool will automatically show all compatible standar ds that have a common v cci voltage requirement. 3. click apply . 4. repeat steps 1?3 to assign v cci voltages to other banks. refer to figure 8-12 on page 8-13 to find out how many i/o banks are needed for v cci bank assignment. manually assigning v ref pins voltage-referenced inputs require an input reference voltage (v ref ). the user must assign v ref pins before running layout. before assigning a v ref pin, the user must set a v ref technology for the bank to which the pin belongs. v ref rules for the implementation of voltage-referenced i/o standards the v ref rules are as follows: 1. any i/o (except jtag i/os) can be used as a v ref pin. 2. one v ref pin can support up to 15 i/os. it is re commended, but not required, that eight of them be on one side and seven on the other side (in other words, all 15 can still be on one side of v ref ). 3. sstl3 (i) and (ii): up to 40 i/os per north or south bank in any position 4. lvpecl / gtl+ 3.3 v / gtl 3.3 v: up to 48 i/os per north or south bank in any position 5. sstl2 (i) and (ii) / gtl+ 2.5 v / gtl 2.5 v: up to 72 i/os per north or south bank in any position. 6. v ref minibanks partition rule: each i/o bank is physically partitioned into v ref minibanks. the v ref pins within a v ref minibank are interconnected internally, and consequently, only one v ref voltage can be used within each v ref minibank. if a bank does not require a v ref signal, the v ref pins of that bank are available as user i/os. 7. the first v ref minibank includes all i/os starting from one end of the bank to the first power triple and eight more i/os after the power triple . therefore, the first v ref minibank may contain (0 + 8), (2 + 8), (4 + 8 ), (6 + 8), or (8 + 8) i/os. the second v ref minibank is adjacent to the first v ref minibank and contains eight i/os, a power triple, and eight mo re i/os after the triple. an analogous rule applies to all other v ref minibanks but the last. the last v ref minibank is adjacent to the previous one but contains eight i/os, a power triple, and all i/os left at th e end of the bank. this bank may also contain (8 + 0), (8 + 2), (8 + 4), (8 + 6), or (8 + 8) available i/os. example: 4 i/os triple 8 i/os, 8 i/os triple 8 i/os, 8 i/os triple 2 i/os i.e., minibank a = (4 + 8) i/ os, minibank b = (8 + 8) i/os, minibank c = (8 + 2) i/os assigning the v ref voltage to a bank when importing th e pdc file, the v ref voltage can be assigned to the i/o bank. the pdc command is as follows: set_iobank ?vref [value] another method for assigning v ref is by using mvn > edit > i/o bank settings ( figure 8-14 on page 8-16 ). i/o software control in low-power flash devices 8-16 v1.1 assigning v ref pins for a bank the user can use default pins for v ref . in this case, select the use default pins for v ref s check box ( figure 8-14 ). this option guarantees full v ref coverage of the bank. th e equivalent pdc command is as follows: set_vref_default [bank name] to be able to choose v ref pins, adequate v ref pins must be created to a llow legal placement of the compatible voltage-referenced i/os. to assign v ref pins manually, the pdc command is as follows: set_vref ?bank [bank name] [package pin numbers] for chipplanner/pineditor to show the range of a v ref pin, perform the following steps: 1. assign v cci to a bank using mvn > edit > i/o bank settings . 2. open chipplanner . zoom in on an i/o package pin in that bank. 3. highlight the pin and th en right-click. choose use pin for v ref . figure 8-14 ? selecting v ref voltage for the i/o bank v ref for gtl+ 3.3 v i/o software control in low-power flash devices v1.1 8-17 4. right-click and then choose show v ref range . all the pins covered by that v ref pin will be highlighted ( figure 8-15 ). using pineditor or chipplanner, v ref pins can also be assigned ( figure 8-16 ). to unassign a v ref pin: 1. select the pin to unassign. 2. right-click and choose use pin for v ref . the check mark next to the command disappears. the v ref pin is now a regular pin. resetting the pin may result in una ssigning i/o cores, even if they are locked. in this case, a warning message appears so you can cancel the operation. after you assign the v ref pins, right-click a v ref pin and choose highlight vref range to see how many i/os are covered by this pin. to unhighlight the range, choose unhighlight all from the edit menu. figure 8-15 ? v ref range figure 8-16 ? assigning v ref from pineditor i/o software control in low-power flash devices 8-18 v1.1 automatically assigning technologies to i/o banks the i/o bank assigner (ioba) to ol runs automatically when you run layout. you can also use this tool from with in the multiview navigator ( figure 8-18 ). the ioba tool au tomatically assigns technologies and v ref pins (if required) to every i/o bank that does not currently have any technologies assigned to it. this tool is avai lable when at least one i/o bank is unassigned. to automatically assign techno logies to i/o banks, choose i/o bank assigner from the to o l s menu (or click the i/o bank assigner's toolbar button, shown in figure 8-17 ). messages will appear in the output window informing you when the automatic i/o bank assignment begins and ends. if the assignment is successful, the message "i/o bank assigner completed successfully" appears in the output window, as shown in figure 8-18 . figure 8-17 ? i/o bank assigner?s toolbar button figure 8-18 ? i/o bank assigner displays messages in output window i/o software control in low-power flash devices v1.1 8-19 if the assignment is not successful, an er ror message appears in the output window. to undo the i/o bank assignments, choose undo from the edit menu. undo removes the i/o technologies assigned by the ioba . it does not remove the i/o te chnologies previously assigned. to redo the changes undone by the undo command, choose redo from the edit menu. to clear i/o bank assignments made before using the undo command, manually unassign or reassign i/o technologies to banks. to do so, choose i/o bank settings from the edit menu to display the i/o bank settings dialog box. conclusion igloo and proasic3 support for multiple i/o st andards minimizes board- level components and makes possible a wide variety of applications. th e actel designer software, integrated with actel libero ide, presents a clear visual display of i/o as signments, allowing users to verify i/o and board- level design requirements before programmin g the device. the device i/o features and functionalities en sure board designers can produce low-cost and low-power fpga applications fulfilling the comple xities of contempora ry design needs. related documents handbook documents ddr for actel?s low- power flash devices http://www.actel.com/documents/lpd_ddr_hbs.pdf flash*freeze technology an d low-power modes in iglo o and proasic3l devices http://www.actel.com/documen ts/lpd_flashfreeze_hbs.pdf global resources in actel low-power flash devices http://www.actel.com/documents/lpd_global_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglooe and proasic3e devices http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf power-up/-down behavior of proasic3/e devices http://www.actel.com/documents/ proasic3_e_powerup_hbs.pdf proasic3/e sso and pin placement an d guidelines http://www.actel.c om/documents/pa 3_e_sso_hbs.pdf user?s guides actel libero ide user?s guide http://www.actel.com/documents/libero_ug.pdf igloo, fusion, and proasic3 macro library guide http://www.actel.com/documents/pa3_libguide_ug.pdf smartgen core reference guide http://www.actel.com/documents/genguide_ug.pdf i/o software control in low-power flash devices 8-20 v1.1 part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-026-0 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the document. previous version changes in current version (v1.1) page v1.0 (january 2008) this document was previously part of the i/o structures in igloo and proasic3 devices document. the conten t was separated and made into a new document. n/a table 8-2 designer state (resulting from i/o attribute modification) was updated to include note 2 for igloo plus. 8-3 v1.1 9-1 ddr for actel?s low-power flash devices 9 ? ddr for actel?s low-power flash devices introduction the i/os in igloo, ? fusion, and proasic ? 3 devices support double data rate (ddr) mode. in this mode, new data is present on every transition (or clock edge) of the clock signal. this mode doubles the data transfer rate compared with single data rate (sdr) mode, where new data is present on one transition (or cloc k edge) of the clock signal. low-power flash devices have ddr circuitry built into the i/o tiles. i/os are config ured to be ddr receivers or transmitters by instantiating the appropriate spec ial macros (examples shown in figure 9-4 on page 9-6 and figure 9-5 on page 9-7 ) and buffers (ddr_out or ddr_reg) in the rtl design. this document discusses the opti ons the user can choose to configure the i/os in this mode and how to instantiate them in the design. double data rate (ddr) architecture low-power flash devices support 350 mhz ddr in puts and outputs. in ddr mode, new data is present on every transition of the clock signal. clock and data lines have identical bandwidths and signal integrity requirements, making them very ef ficient for implementi ng very high-speed systems. high-speed ddr interfaces can be implemented using lvds. in iglooe and proasic3e devices, ddr interfaces can also be implemented using the hstl , sstl, and lvpecl i/o standards. the ddr feature is primarily impl emented in the fpga core periphery and is not tied to a specific i/o technology or limited to any i/o standard. figure 9-1 ? ddr support in low-power flash devices dqr qf clr pad y inbuf_sstl2_i ddr_reg pad clk clr q pad dr q clr df datar dataf outbuf_sstl3_i ddr_out ddr for actel?s low-power flash devices 9-2 v1.1 ddr support in low-power devices the low-power flash families listed in table 9-1 support the ddr feature and the functions described in this document. actel's low-power flas h devices (listed in table 9-1 ) provide a selection of secure, low-power, live- at-power-up, single-chip solutions. the nonvolat ile flash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design se curity without extern al overhead. only low-power flash fpgas can offer these advantages. actel igloo fpgas are the only 1.2 v ultra-lo w-power programmable logic devices (plds) and consume 30% less static power and over 50 % less dynamic power than pld alternatives. flash*freeze technology used in igloo and proasic3l devices enab les easy entry to and exit from the ultra-low power mode, which consumes as li ttle as 5 w, while retaining sram and register data. flash*freeze technology si mplifies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digital converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 9-1 . where the information applies to only one fami ly or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 9-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 9-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s iglooe igloo devices enhanced with hi gher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1.2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-perfo rmance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher density, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fpgas qualified for automotive ap plications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. ddr for actel?s low-power flash devices v1.1 9-3 i/o cell architecture low-power flash devices support ddr in the i/o ce lls in four different modes: inpu t, output, tristate, and bidirectional pins. for each mode, different i/o stan dards are supported, with most i/o standards having special sub-options. refer to table 9-2 for a sample of the available i/o options. additional i/o options can be found in the relevant family datasheet. table 9-2 ? ddr i/o options ddr register type i/o type i/o standard sub-options comments receive register input normal none 3.3 v ttl (default) lvcmos voltage 1.5 v, 1.8 v, 2.5 v, 5 v (1.5 v default) pull-up none (default) pci/pci-x none gtl/gtl+ voltage 2.5 v, 3.3 v (3.3 v default) hstl class i / ii (i default) sstl2/sstl3 class i / ii (i default) lvpecl none lvds none transmit register output norma l none 3.3 v ttl (default) lvttl output drive 2, 4, 6, 8, 12, 16, 24, 36 ma (8 ma default) slew rate low/high (high default) lvcmos voltage 1.5 v, 1.8 v, 2.5 v, 5 v (1.5 v default) pci/pci-x none gtl/gtl+ voltage 1.8 v, 2.5 v, 3.3 v (3.3 v default) hstl class i / ii (i default) sstl2/sstl3 class i / ii (i default) lvpecl none lvds none ddr for actel?s low-power flash devices 9-4 v1.1 transmit register (continued) tristate buffer normal enable polarity low/high (low default) lvttl output drive 2, 4, 6, 8, 12,16, 24, 36 ma (8 ma default) slew rate low/high (high default) enable polarity low/ high (low default) pull-up/-down none (default) lvcmos voltage 1.5 v, 1.8 v, 2.5 v, 5 v (1.5 v default) output drive 2, 4, 6, 8, 12, 16, 24, 36 ma (8 ma default) slew rate low/high (high default) enable polarity low/ high (low default) pull-up/-down none (default) pci/pci-x enable polarity low/high (low default) gtl/gtl+ voltage 1.8 v, 2.5 v, 3.3 v (3.3 v default) enable polarity low/ high (low default) hstl class i / ii (i default) enable polarity low/ high (low default) sstl2/sstl3 class i / ii (i default) enable polarity low/ high (low default) bidirectional buffer normal enable polarity lo w/high (low default) lvttl output drive 2, 4, 6, 8, 12, 16, 24, 36 ma (8 ma default) slew rate low/high (high default) enable polarity low/ high (low default) pull-up/-down none (default) lvcmos voltage 1.5 v, 1.8 v, 2.5 v, 5 v (1.5 v default) enable polarity low/ high (low default) pull-up none (default) pci/pci-x none enable polarity low/ high (low default) gtl/gtl+ voltage 1.8 v, 2.5 v, 3.3 v (3.3 v default) enable polarity low/ high (low default) hstl class i / ii (i default) enable polarity low/ high (low default) sstl2/sstl3 class i / ii (i default) enable polarity low/ high (low default) table 9-2 ? ddr i/o options (continued) ddr register type i/o type i/o standard sub-options comments ddr for actel?s low-power flash devices v1.1 9-5 input support for ddr the basic structure to suppor t a ddr input is shown in figure 9-2 . three input registers are used to capture incoming data, which is pr esented to the core on each risi ng edge of the i/o register clock. each i/o tile su pports ddr inputs. output support for ddr the basic ddr output structure is shown in figure 9-1 on page 9-1 . new data is presented to the output every half clock cycle. note: ddr macros and i/o registers do not require addi tional routing. the combiner automatically recognizes the ddr macro and pushes its registers to the i/o register area at the edge of the chip. the routing delay from the i/o registers to the i/o buffers is already taken into account in the ddr macro. figure 9-2 ? ddr input register support in low-power flash devices d qr qf clr pad y inbuf_sstl2_i ddr_reg qr qf pad clk clr figure 9-3 ? ddr output register (sstl3 class i) q pad dr q clr df datar dataf clr clk outbuf_sstl3_i ddr_out ddr for actel?s low-power flash devices 9-6 v1.1 instantiating ddr registers using smartgen is the simplest way to generate the appropriate rtl files for use in the design. figure 9-4 shows an example of using smartgen to ge nerate a ddr sstl2 class i input register. smartgen provides the capability to generate all of the ddr i/o cells as described. the user, through the graphical user interface, can select from among the many supported i/o standards. the output formats supported are verilog, vhdl, and edif. figure 9-5 on page 9-7 through figure 9-8 on page 9-10 show the i/o cell configured for ddr using sstl2 class i technology. for each i/o standard, th e i/o pad is buffered by a special primitive that indicates the i/o standard type. figure 9-4 ? example of using smartgen to generate a ddr sstl2 class i input register ddr for actel?s low-power flash devices v1.1 9-7 ddr input register the corresponding structural representations, as generated by smar tgen, are shown below: verilog module ddr_inbuf_sstl2_i(pad,clr,clk,qr,qf); input pad, clr, clk; output qr, qf; wire y; inbuf_sstl2_i inbuf_sstl2_i_0_inst(.pad(pad),.y(y)); ddr_reg ddr_reg_0_inst(.d(y),.clk(clk),.clr(clr),.qr(qr),.qf(qf)); endmodule vhdl library ieee; use ieee.std_logic_1164.all; --the correct library will be inserted automatically by smartgen library proasic3; use proasic3.all; --library fusion; use fusion.all; --library igloo; use igloo.all; entity ddr_inbuf_sstl2_i is port(pad, clr, clk : in std_logic; qr, qf : out std_logic) ; end ddr_inbuf_sstl2_i; architecture def_arch of ddr_inbuf_sstl2_i is component inbuf_sstl2_i port(pad : in std_logic := 'u'; y : out std_logic) ; end component; component ddr_reg port(d, clk, clr : in std_logic := 'u'; qr, qf : out std_logic) ; end component; signal y : std_logic ; begin inbuf_sstl2_i_0_inst : inbuf_sstl2_i port map(pad => pad, y => y); ddr_reg_0_inst : ddr_reg port map(d => y, clk => clk, clr => clr, qr => qr, qf => qf); end def_arch; figure 9-5 ? ddr input register (sstl2 class i) d qr qf clr pad y inbuf_sstl2_i ddr_reg qr qf pad clk clr ddr for actel?s low-power flash devices 9-8 v1.1 ddr output register verilog module ddr_outbuf_sstl3_i(datar,dataf,clr,clk,pad); input datar, dataf, clr, clk; output pad; wire q, vcc; vcc vcc_1_net(.y(vcc)); ddr_out ddr_out_0_inst(.dr(datar),.df(dataf),.clk(clk),.clr(clr),.q(q)); outbuf_sstl3_i outbuf_sstl3_i_0_inst(.d(q),.pad(pad)); endmodule vhdl library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity ddr_outbuf_sstl3_i is port(datar, dataf, clr, clk : in std_logic; pad : out std_logic) ; end ddr_outbuf_sstl3_i; architecture def_arch of ddr_outbuf_sstl3_i is component ddr_out port(dr, df, clk, clr : in std_logic := 'u'; q : out std_logic) ; end component; component outbuf_sstl3_i port(d : in std_logic := 'u'; pad : out std_logic) ; end component; component vcc port( y : out std_logic); end component; signal q, vcc_1_net : std_logic ; begin vcc_2_net : vcc port map(y => vcc_1_net); ddr_out_0_inst : ddr_out port map(dr => datar, df => dataf, clk => clk, clr => clr, q => q); outbuf_sstl3_i_0_inst : outbuf_sstl3_i port map(d => q, pad => pad); end def_arch; figure 9-6 ? ddr output register (sstl3 class i) q pad dr q clr df datar dataf clr clk outbuf_sstl3_i ddr_out ddr for actel?s low-power flash devices v1.1 9-9 ddr tristate output register verilog module ddr_tristatebuf_lvttl_8ma_highslew_lowenb_pullup(datar, dataf, clr, clk, trien, pad); input datar, dataf, clr, clk, trien; output pad; wire trienaux, q; inv inv_tri(.a(trien),.y(trienaux)); ddr_out ddr_out_0_inst(.dr(datar),.df(dataf),.clk(clk),.clr(clr),.q(q)); tribuff_f_8u tribuff_f_8u_0_inst(.d(q),.e(trienaux),.pad(pad)); endmodule vhdl library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity ddr_tristatebuf_lvttl_8ma_highslew_lowenb_pullup is port(datar, dataf, clr, clk, trien : in std_logic; pad : out std_logic) ; end ddr_tristatebuf_lvttl_8ma_highslew_lowenb_pullup; architecture def_arch of ddr_tristatebuf_lvttl_8ma_highslew_lowenb_pullup is component inv port(a : in std_logic := 'u'; y : out std_logic) ; end component; component ddr_out port(dr, df, clk, clr : in std_logic := 'u'; q : out std_logic) ; end component; component tribuff_f_8u port(d, e : in std_logic := 'u'; pad : out std_logic) ; end component; signal trienaux, q : std_logic ; begin inv_tri : inv figure 9-7 ? ddr tristate output register, low enable, 8 ma, pull-up (lvttl) q pad dr q clr df datar dataf clr clk tribuff_f_8u ddr_out trien ay trienaux inv ddr for actel?s low-power flash devices 9-10 v1.1 port map(a => trien, y => trienaux); ddr_out_0_inst : ddr_out port map(dr => datar, df => dataf, clk => clk, clr => clr, q => q); tribuff_f_8u_0_inst : tribuff_f_8u port map(d => q, e => trienaux, pad => pad); end def_arch; ddr bidirectional buffer verilog module ddr_bidir_hstl_i_lowenb(datar,dataf,clr,clk,trien,qr,qf,pad); input datar, dataf, clr, clk, trien; output qr, qf; inout pad; wire trienaux, d, q; inv inv_tri(.a(trien), .y(trienaux)); ddr_out ddr_out_0_inst(.dr(datar),.df(dataf),.clk(clk),.clr(clr),.q(q)); ddr_reg ddr_reg_0_inst(.d(d),.clk(clk),.clr(clr),.qr(qr),.qf(qf)); bibuf_hstl_i bibuf_hstl_i_0_inst(.pad(pad),.d(q),.e(trienaux),.y(d)); endmodule figure 9-8 ? ddr bidirectional buffer, low output enable (hstl class ii) d pad dr q clr df datar dataf clr clk bibuf_hstl_i ddr_out trien ay e y d qr qf clr qr qf inv ddr_reg ddr for actel?s low-power flash devices v1.1 9-11 vhdl library ieee; use ieee.std_logic_1164.all; library proasic3; use proasic3.all; entity ddr_bidir_hstl_i_lowenb is port(datar, dataf, clr, clk, trien : in std_logic; qr, qf : out std_logic; pad : inout std_logic) ; end ddr_bidir_hstl_i_lowenb; architecture def_arch of ddr_bidir_hstl_i_lowenb is component inv port(a : in std_logic := 'u'; y : out std_logic) ; end component; component ddr_out port(dr, df, clk, clr : in std_logic := 'u'; q : out std_logic) ; end component; component ddr_reg port(d, clk, clr : in std_logic := 'u'; qr, qf : out std_logic) ; end component; component bibuf_hstl_i port(pad : inout std_logic := 'u'; d, e : in std_logic := 'u'; y : out std_logic) ; end component; signal trienaux, d, q : std_logic ; begin inv_tri : inv port map(a => trien, y => trienaux); ddr_out_0_inst : ddr_out port map(dr => datar, df => dataf, clk => clk, clr => clr, q => q); ddr_reg_0_inst : ddr_reg port map(d => d, clk => clk, clr => clr, qr => qr, qf => qf); bibuf_hstl_i_0_inst : bibuf_hstl_i port map(pad => pad, d => q, e => trienaux, y => d); end def_arch; ddr for actel?s low-power flash devices 9-12 v1.1 design example figure 9-9 shows a simple example of a design using bo th ddr input and ddr ou tput registers. the user can copy the hdl code in actel libero ? integrated design environment (ide) and go thorough the design flow. figure 9-10 and figure 9-11 on page 9-13 show the netlist an d chipplanner views of the ddr_test design. diagrams may va ry slightly for different families. figure 9-9 ? design example figure 9-10 ? ddr test design as seen by netlistviewer for igloo/e devices dqr qf clr pad y inbuf_sstl2_i ddr_reg pad clk clr q pad dr q clr df datar dataf outbuf_sstl3_i ddr_out ddr for actel?s low-power flash devices v1.1 9-13 verilog module inbuf_ddr(pad,clr,clk,qr,qf); input pad, clr, clk; output qr, qf; wire y; ddr_reg ddr_reg_0_inst(.d(y), .clk(clk), .clr(clr), .qr(qr), .qf(qf)); inbuf inbuf_0_inst(.pad(pad), .y(y)); endmodule module outbuf_ddr(datar,dataf,clr,clk,pad); input datar, dataf, clr, clk; output pad; wire q, vcc; vcc vcc_1_net(.y(vcc)); ddr_out ddr_out_0_inst(.dr(datar), .df(dataf), .clk(clk), .clr(clr), .q(q)); outbuf outbuf_0_inst(.d(q), .pad(pad)); endmodule figure 9-11 ? ddr input/output cells as seen by chipplanner for igloo/e devices ddr for actel?s low-power flash devices 9-14 v1.1 module ddr_test(din, clk, clr, dout); input din, clk, clr; output dout; inbuf_ddr inbuf_ddr (.pad(din), .clr(clr), .clk(clk), .qr(qr), .qf(qf)); outbuf_ddr outbuf_ddr (.datar(qr),.dataf(qf), .clr(clr), .clk(clk),.pad(dout)); inbuf inbuf_clr (.pad(clr), .y(clr)); inbuf inbuf_clk (.pad(clk), .y(clk)); endmodule simulation consideration actel ddr simulation models use inertial dela y modeling by default (versus transport delay modeling). as such, pulses that ar e shorter than the actual gate de lays should be avoided, as they will not be seen by the simulator and may be an issue in post-routed simu lations. the user must be aware of the default delay modeling and must set the correct delay model in the simulator as needed. conclusion igloo, fusion, and proasic3 devices support a wi de range of ddr applications with different i/o standards and include built-in ddr macros. the powe rful capabilities provided by smartgen and its gui can simplify the process of including ddr macros in desi gns and minimize design errors. additional considerations should be taken into account by the designer in design floorplanning and placement of i/o flip-flops to minimize datapath skew and to help improve system timing margins. other system-related issues to c onsider include pll and clock partitioning. part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-010-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.1) page v1.0 (january 2008) the "igloo terminology" section and "proasic3 terminology" section are new. 9-2 packaging and pin descriptions v1.1 10-1 pin descriptions 10 ? pin descriptions supply pins gnd ground ground supply voltage to the core, i/o outputs, and i/o logic. gndq ground (quiet) quiet ground supply voltage to input buffers of i/o banks. with in the package, the gndq plane is decoupled from the simultaneous switching noi se originated from the output buffer ground domain. this minimizes the noise transfer within the pa ckage and improves in put signal integrity. gndq must always be connected to gnd on the board. v cc core supply voltage supply voltage to the fpga co re, nominally 1.5 v for proasic ? 3/e devices, 1.5 v for igloo ? /e v5 devices, and 1.2 v or 1.5 v for ig loo/e v2 and proa sic3l devices. v cc is required fo r powering the jtag state machine in addition to v jtag . even when a device is in bypass mode in a jtag chain of interconnected devices, both v cc and v jtag must remain powered to al low jtag signals to pass through the device. for igloo/e v2 and pr oasic3l devices, v cc can be switched dynamically from 1.2 v to 1.5 v or vice versa. this allows in-system programming (isp) when v cc is at 1.5 v and the benefit of low-power operation when v cc is at 1.2 v. v cci bx i/o supply voltage supply voltage to the bank's i/o output buffers an d i/o logic. bx is the i/ o bank number. there are up to eight i/o banks on low-power flash devices plus a dedicated v jtag bank. each bank can have a separate v cci connection. all i/os in a bank will run off the same v cci bx supply. v cci can be 1.2 v (not supported on proasic3/e devices), 1.5 v, 1. 8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding v cci pins tied to gnd. vmvx i/o supply voltage (quiet) quiet supply voltage to the input buffers of each i/o bank. x is the bank number. within the package, the vmv plane is decoupled from the simu ltaneous switching nois e originated from the output buffer v cci domain. this minimizes the noise transfer within the package and improves input signal integrity. each bank must have at least one vmv connection, and no vmv should be left unconnected. all i/os in a bank run off the same vmvx supply. vmv is used to provide a quiet supply voltage to th e input buffers of each i/o bank. vmvx can be 1.2 v (proasic3l and igloo/e devices only), 1.5 v, 1.8 v, 2.5 v, or 3.3 v, nominal voltage. unused i/o banks should have their corresponding vmv pins tied to gnd. vmv and v cci should be at the same voltage within a given i/o bank. used vmv pins must be connected to the corresponding v cci pins of the same bank (i.e., vmv0 to v cci b0, vmv1 to v cci b1, etc.). v ccpla/b/c/d/e/f pll supply voltage supply voltage to analog pll, nominally 1.5 v or 1.2 v, depending on the device family. ? 1.5 v for igloo v5, iglooe v5, proasic3, and proasic3e devices ? 1.2 v or 1.5 v for igloo v2, iglooe v2, proasic3l, and proasic3el devices when the plls are not used, the actel designer place-and-route t ool automaticall y disables the unused plls to lower power consumption. the user should tie unused v ccplx and v complx pins to ground. actel recommends tying v ccplx to v cc and using proper filtering circuits to decouple v cc noise from pll. refer to the pll power supply decoupling section of clock conditioning circuits in igloo and proasic3 devices for a complete board so lution for the pll analog power supply and ground. ? there is one v ccplf pin on igloo, igloo plus, proasic3l, and proasic3 devices. ? there are six v ccplx pins on iglooe, proasic3el, and proasic3e devices. pin descriptions 10-2 v1.1 v compla/b/c/d/e/f pll ground ground to analog pll power supp lies. when the plls are not used , the actel designer place-and- route tool automatically disables the unused plls to lower power co nsumption. the user should tie unused v ccplx and v complx pins to ground. ? there is one v complf pin on igloo, proasic3l, and proasic3 devices. ? there are six v compl pins (pll ground) on iglooe, proasic3el, and proasic3e devices. v jtag jtag supply voltage low-power flash devices have a separate bank for the dedi cated jtag pins. the jtag pins can be run at any voltage from 1.5 v to 3.3 v (nominal). isolating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither used nor planned for use, the v jtag pin together with the trst pin could be tied to gnd. it should be noted that v cc is required to be powered for jtag operation; v jtag alone is insufficient. if a device is in a jtag ch ain of interconnected boards, the board containing the device can be powered down, provided both v jtag and v cc to the part remain powered; otherwise, jtag signals will not be able to transition the device, even in bypass mode. actel recommends that v pump and v jtag power supplies be kept se parate with independent filtering capacitors rather than supplying them fro m a common rail. v pump programming supply voltage igloo, proasic3l, and proasic3 devices support si ngle-voltage isp of the configuration flash and flashrom. for programming, v pump should be 3.3 v nominal. during normal device operation, v pump can be left floating or can be tied (pul led up) to any voltage between 0 v and the v pump maximum. programming po wer supply voltage (v pump ) range is listed in the datasheet. when the v pump pin is tied to ground, it will shut of f the charge pump circ uitry, resulting in no sources of oscillation from the charge pump circuitry. for proper programming, 0.01 f and 0.33 f capacito rs (both rated at 16 v) are to be connected in parallel across v pump and gnd, and positioned as close to the fpga pins as possible. actel recommends that v pump and v jtag power supplies be kept se parate with independent filtering capacitors rather than supplying them fro m a common rail. user-defined supply pins v ref i/o voltage reference reference voltage for i/o minibanks in iglooe, proasic3el, and proasic3e devices. v ref pins are configured by the user from regular i/os, an d any i/o in a bank, except jtag i/os, can be designated the voltage re ference i/o. only certain i/o standa rds require a voltage reference?hstl (i) and (ii), sstl2 (i) and (ii), sstl3 (i) and (ii), and gtl/gtl+. one v ref pin can support the number of i/os available in its minibank. pin descriptions v1.1 10-3 user pins i/o user input/output the i/o pin functions as an input, output, tristate , or bidirectional buffer. input and output signal levels are compatible with the i/o standard selected. during programming, i/os become tristated and weakly pulled up to v cci . with v cci , vmv, and v cc supplies continuously powered up, when the devi ce transitions from programming to operating mode, the i/os are instantly configured to the desired us er configuration. unused i/os are configured as follows: ? output buffer is disabled (with tristate value of high impedance) ? input buffer is disabled (with tristate value of high impedance) ? weak pull-up is programmed gl globals gl i/os have access to certain clock conditioning circuitry (and the pll) and/or have direct access to the global network (spines). additionally, the glob al i/os can be used as regular i/os, since they have identical capabilities. unused gl pins ar e configured as inputs wi th pull-up resistors. see more detailed descriptions of global i/o connectivity in clock conditioning circuits in igloo and proasic3 devices . all inputs labeled gc/gf are direct inputs into the quadrant clocks. for example, if gaa0 is used for an input, gaa1 an d gaa2 are no longer avai lable for input to the quadrant globals. all inputs labe led gc/gf are direct inputs into th e chip-level globals, and the rest are connected to the quadrant gl obals. the inputs to th e global network are multiplexed, and only one input can be used as a global input. refer to the i/o structure section of the handbook for the device you are using for an explanation of the naming of global pins. ff flash*freeze mode activation pin flash*freeze? is available on igloo and proasic3l devices. it is not supported on proasic3/e devices. the ff pin is a dedicated input pin used to enter and exit flash*freeze mode. the ff pin is active-low, has the same characteristics as a sing le-ended i/o, and must meet the maximum rise and fall times. when flash*free ze mode is not used in the design, th e ff pin is available as a regular i/o. for iglooe and proasic3el only , the ff pin can be configured as a schmitt trigger input. when flash*freeze mode is used, the ff pin must no t be left floating to avoid accidentally entering flash*freeze mode. wh ile in flash*freeze mo de, the flash*freeze pin should be constantly asserted. the flash*freeze pin can be used with any single-e nded i/o standard supported by the i/o bank in which the pin is located, and input signal levels compatible with the i/o standard selected. the ff pin should be treated as a sensitive asynchrono us signal. when defining pin placement and board layout, simultaneously switching outputs (ssos) and th eir effects on sensit ive asynchronous pins must be considered. unused ff or i/o pins are tristated with weak pull-up. this default configuration applies to both flash*freeze mode and normal operation mode . no user intervention is required. pin descriptions 10-4 v1.1 table 10-1 shows the flash*freeze pin lo cation on the available pac kages for igloo and proasic3l devices. the flash*freeze pin location is indepe ndent of device (except for a pq208 package), allowing migration to larger or smaller igloo de vices while maintaining th e same pin location on the board. refer to flash*freeze technology and low-po wer modes in igloo and proasic3l devices for more information on i/o states during fl ash*freeze mode. jtag pins low-power flash devices have a separate bank for the dedi cated jtag pins. the jtag pins can be run at any voltage from 1. 5v to 3.3v (nominal). v cc must also be powered for the jtag state machine to operate, even if the device is in bypass mode; v jtag alone is insufficient. both v jtag and v cc to the part must be supplied to allow jtag sign als to transition the device. isolating the jtag power supply in a separate i/o bank gives greater flexibility in supply selection and simplifies power supply and pcb design. if the jtag interface is neither us ed nor planned for use, the v jtag pin together with the trst pin could be tied to gnd. tck test clock test clock input for jtag boundary scan, isp, and ujtag. the tck pin does not have an internal pull-up/-down resistor. if jtag is not used, actel recommends tying of f tck to gnd through a resistor placed close to the fpga pin. this prevents jtag operatio n in case tms enters an undesired state. table 10-1 ? flash*freeze pin location in igloo and proasic3l family packages (device- independent) igloo and proasic3l packages flash*freeze pin cs81/uc81 h2 cs121 j5 cs196 p3 qn68 18 qn132 b12 cs281 w2 cs201 (package only available for igloo plus devices) r4 cs289 (package only available for igloo plus devices) tbd vq100 27 fg144 l3 fg256 t3 fg484 w6 fg896 ah4 pq208 (package only availa ble for proasic3l devices) pq208-a3p250 pq208-a3p600l pq2097-a3p1000l pq208-a3pe3000l 56 55 55 58 pin descriptions v1.1 10-5 note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. refer to table 10-2 for more information. tdi test data input serial input for jtag boundary sc an, isp, and ujtag usage. ther e is an internal weak pull-up resistor on the tdi pin. tdo test data output serial output for jt ag boundary scan, isp, and ujtag usage. tms test mode select the tms pin controls the use of the ieee 1532 bounda ry scan pins (tck, tdi, tdo, trst). there is an internal weak pull-up resistor on the tms pin. trst boundary scan reset pin the trst pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. there is an internal weak pull-up resistor on the tr st pin. if jtag is not used, an external pull-down resistor could be included to ensure the test access port (tap) is held in reset mode. the resistor values must be chosen from table 10-2 and must satisfy th e parallel resistance value requirement. the values in table 10-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resist or when multiple devices are connected via a jtag chain. in critical applications, an upset in the jtag circuit could allow entranc e to an undesired jtag state. in such cases, actel recommends tying off tr st to gnd through a resi stor placed close to the fpga pin. note that to operate at all v jtag voltages, 500 to 1 k will satisfy the requirements. special function pins nc no connect this pin is not connected to circuitry within the device. these pins can be driven to any voltage or can be left floating with no effe ct on the operation of the device. dc do not connect this pin should not be connected to any signals on the pcb. these pins should be left unconnected. table 10-2 ? recommended tie-off values for the tck and trst pins v jtag tie-off resistance v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k notes: 1. equivalent parallel resistance if more than one device is on the jtag chain 2. the tck pin can be pulled up/down. 3. the trst pin is pulled down. pin descriptions 10-6 v1.1 related documents handbook documents clock conditioning circuits in igloo and proasic3 devices http://www.actel.com/documents/lpd_ccc_hbs.pdf i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in iglooe and proasic3e devices http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf flash*freeze technology an d low-power modes in iglo o and proasic3l devices http://www.actel.com/documen ts/lpd_flashfreeze_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet. to improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage info rmation. no technical chan ges were made to the content unless explicitly listed. part number 51700094-011-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the "vccibx i/o supply voltage" section was revised to note that 1.2 v is not supported for proasic3/e devices. the "vmvx i/o supply voltage (quiet)" section was updated to state that vmvx ca n also be 1.2 v nominal voltage on proasic3l and igloo/e devices. 10-1 the "handbook documents" section was revised to include the three different i/o structures chapters for iglo o and proasic3 device families. 10-6 the "v ccpla/b/c/d/e/f pll supply voltage" section and "v compla/b/c/d/e/f pll ground" section were revised. the "v ccplf pll supply voltage" section and "v complf pll ground" section were removed. 10-1 to 10-2 the following packages were added to table 10-1 flash*fr eeze pin location in igloo and proasic3l family packages (device-independent) : uc81, qn68, cs201, and cs289. flash*freeze pin w2 was specified for the cs281 package. the pg208 package was changed to the correct designation of pq208. 10-4 v1.0 11-1 packaging 11 ? packaging semiconductor technology is consta ntly shrinking in size while growing in capability and functional integration. to enable next-generation silicon technologies, semiconduc tor packages have also evolved to provide improved performance and flexibility. actel consistently delivers packages that prov ide the necessary mechan ical and environmental protection to ensure consistent reliability and performance. actel ic packaging technology efficiently supports hi gh-density fpgas with large-pin-count ball grid arrays (bgas), but is also flexible enough to acco mmodate stringent form factor requirements for chip scale packaging (csp). in addition, actel offers a variety of packages designed to meet your most demanding application and economic requirements fo r today's embedded and mobile systems. the following documents provide packaging inform ation and device selection for low-power flash devices. package selector guide http://www.actel.com/documents/selguide.pdf lists devices currently recommended for new desi gns and the packages av ailable for each member of the family. use this document or the datash eet tables to determine the best package for your design, and which package drawing to use. package mechanical drawings http://www.actel.com/documents/pckgmechdrwngs.pdf this document contains the pac kage mechanical drawings for all packages currently or previously supplied by actel. use the bo okmarks to navigate to the package mechanical drawings. related documents additional packaging materials are available at http://www.actel.com/products/ solutions/pac kage/docs.aspx . part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 5170009-012-0 revised january 2008 design migration v1.1 12-1 application note ac314 12 ? migrating designs in proasic3 devices from higher-density to mid-density devices introduction the purpose of this document is to as sist in migrating designs in proasic ? 3 a3p1000, a3p600, and a3p400 devices from higher-density to mid-density devices. ther e are three possible migration paths: ? a3p1000 to a3p600 ? a3p1000 to a3p400 ? a3p600 to a3p400 since one of the key factors is pin compatibility, this document addresses pin compatibility for all available packages common to the a3p1000, a3p600, and a3p400 devices. design migration proasic3 family devices are architecturally comp atible with each other. however, designers must pay attention to a few key areas when migrating a design. the specific issues discussed throughout this application note are as follows: ? "design and device evaluation" ? "device and package compatibility" on page 12-2 ? "migration and implementation methodologies" on page 12-3 ? "i/o banks and standards" on page 12-4 ? "power supply and board-level considerations" on page 12-4 ? "pin migration and compatibility" on page 12-5 design and device evaluation when migrating a design, the primary task should be to compare the available resources between the two devices. the desi gner should evaluate effective gate count, ram size, i/o banks, and number of i/os ( table 12-1 ). in addition, necessary design timing analysis and simulations should be validated when porting designs to new proasic3 derivatives. table 12-1 ? device information a3p1000 a3p600 a3p400 system gates 1 m 600 k 400 k tiles (d-flip-flop) 24,576 13,824 9,126 ram (kbits) 144 108 54 ram blocks (4,608 bits) 32 24 12 i/o banks (+ jtag) 444 maximum user i/os per package pq208 fg144 fg256 fg484 154/35 97/25 177/44 300/74 154/35 97/25 177/43 235/60 151/34 97/25 178/38 194/38 note: maximum user i/o is listed as single-ended/double-ended. migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-2 v1.1 device and package compatibility proasic3 devices and packaging we re designed to allow considerab le footprint compatibility for smoother migration. common and convertible i/os be tween a3p400, a3p600, and a3p1000 devices table 12-2 shows the number of i/os that are common be tween any two of these devices, as well as the number of i/os that will require conversion per the suggested design migration rules given in the "migration and implementation me thodologies" section on page 12-3 . table 12-2 ? common and convertible i/os package a3p1000 a3p600 a3p1000 a3p400 a3p600 a3p400 common i/os convertible i/os common i/os convertible i/os common i/os convertible i/os pq208 154015451515 fg144 970970980 fg256 178311775917733 fg484 236 96 192 75 236 166 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-3 migration and implementation methodologies table 12-3 lists some possible migratio n combinations and the recommended implementation rules for compatible design conversions from higher-d ensity to lower-density devices. refer to the "related documents" section on page 12-40 for other relevant actel documentation. the "pin migration and compatibility" section on page 12-5 contains tables that li st the required rules for different pin combinations. if ?rule x? is ment ioned for a pin combinat ion, that combination requires the implementati on methodology given in table 12-3 . note that many combinations of high-density/low-density pins do no t require these rules; the pins ha ve complete type compatibility. these pins are marked in th e pin tables with ?none.? table 12-3 ? migration rules from higher-density to mid-density devices migration rule issue implementation methodology higher density lower density 1 i/o or global i/o nc leave this pin floating or program i/os as unused (software cannot program nc to usable i/o). 2 single-ended i/o global i/o instantiate the i/o buffer as a global single-ended i/o. 3 global i/o single-ended i/o use the physical design constraint (pdc) to promote the single-ended i/o to a global pin. there is an additional delay that affects the setup time on the board. or, do not use this pin as a global input on the higher-density device. 4v cc or v cci b(x) 1,3 nc leave pin connected to board v cc or v cci bx plane. 5v cci b(x) 1 v cci b(y) 2 make sure the two bank voltage levels are the same. tie the pin to the board?s corresponding v cci bx/vmvx plane. 6vmv(x) 1 vmv(y) 2 make sure the two bank voltage levels are the same. tie pin to the board?s corresponding v cci bx/vmvx plane. 7vmv(x) 2 i/o or global i/o leave the pin tied to the board v cci bx/vmvx plane. instantiate the i/os as tristate buffers with oe = 0 and no weak pull-ups/-downs. 8 gndq global i/o leave both pins tied to board gndq plane. instantiate the i/o as tristate buffer with oe = 0 and no weak pull-ups/-downs. 9 gndq nc gndq and nc need to be connected to gnd. notes: 1. (x) = 1, 2, 3, or 4 2. (y) = 1, 2, 3, or 4 3. refer to i/o structures in igloo and proasic3 devices for i/o naming conventions. migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-4 v1.1 i/o banks and standards proasic3 i/os are partitioned into multiple i/o voltage banks. the number of banks is device- dependent. there are four i/o banks in a3p1000, a3p600, and a3p400 devices. package v cci bx pins are routed through the corresponding banks of the devices. the banks have dedicated supplies ; therefore, only i/os with co mpatible voltage standards can be assigned to the same i/o voltage bank. power supply and board-level considerations i/o power supply requirements are one of the key aspects to consider for design migration. since the migration is within the proasi c3 family, there is no issue with respect to the core voltage, v cc . pins that must be approp riately connected are v cci bx (bank supply voltage to i/o output buffer and i/o logic), vmvx (quiet i/o supp ly voltage), gndq (quiet gnd), an d gnd. an important function of gndq and vmvx is to decouple simultaneous swit ching noise for outputs (s sos) to enhance signal integrity and improve noise immunity. the following are the key rules of migration for the above-mentioned pins: ? vmvx and v cci bx must be at the same voltage level for a given bank. ?v cci bx pins and vmvx pins in unus ed banks must be connected to gnd. ? unused i/os are automatica lly disabled by software. a specific power-supply sequence at power-up is not required. any incorrect connection during the migration may affect overall dynamic or inrush power consumption and might even result in device malfunction. additionally, the i/o naming convention in proasic3 devices has significant embedded information (i.e., pin location, bank number, signal type, polarity, and clock conditioning). for a detailed explanation, refer to th e ?user i/o naming conv ention? section in the i/o structures in igloo and proasic3 devices . this datasheet also contains additional information on power issues. migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-5 pin migration and compatibility pq208 package table 12-4 ? pin compatibility and migratio n table for the pq208 package pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 1 gnd gnd gnd none none none 2 gaa2/io225pdb3 gaa2/io170pdb3 gaa2/io155udb3 none none none 3 io225ndb3 io170ndb3 io 155vdb3 none none none 4 gab2/io224pdb3 gab2/io169pdb3 gab2/io154udb3 n one none none 5 io224ndb3 io169ndb3 io 154vdb3 none none none 6 gac2/io223pdb3 gac2/io168pdb3 gac2/io153udb3 n one none none 7 io223ndb3 io168ndb3 io 153vdb3 none none none 8 io222pdb3 io167pdb3 io152udb3 none none none 9 io222ndb3 io167ndb3 io 152vdb3 none none none 10 io220pdb3 io166pdb3 io151udb3 none none none 11 io220ndb3 io166ndb3 io151vdb3 none none none 12 io218pdb3 io165pdb3 io150pdb3 none none none 13 io218ndb3 io165ndb3 io150ndb3 none none none 14 io216pdb3 io164pdb3 io149pdb3 none none none 15 io216ndb3 io164ndb3 io149ndb3 none none none 16 v cc v cc v cc none none none 17 gnd gnd gnd none none none 18 v cci b3 v cci b3 v cci b3 none none none 19 io212pdb3 io163pdb3 io148pdb3 none none none 20 io212ndb3 io163ndb3 io148ndb3 none none none 21 gfc1/io209pdb3 gfc1/io161pdb 3 gfc1/io147pdb3 none none none 22 gfc0/io209ndb3 gfc0/io161ndb 3 gfc0/io147ndb3 none none none 23 gfb1/io208pdb3 gfb1/io160pdb 3 gfb1/io146pdb3 none none none 24 gfb0/io208ndb3 gfb0/io160ndb 3 gfb0/io146ndb3 none none none 25 v complf v complf v complf none none none 26 gfa0/io207npb3 gfa0/io159npb 3 gfa0/io145npb3 none none none 27 v ccplf v ccplf v ccplf none none none 28 gfa1/io207ppb3 gfa1/io159ppb 3 gfa1/io145ppb3 none none none 29 gnd gnd gnd none none none migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-6 v1.1 30 gfa2/io206pdb3 gfa2/io158pdb3 gfa2/io144pdb3 none none none 31 io206ndb3 io158ndb3 io144ndb3 none none none 32 gfb2/io205pdb3 gfb2/io157pdb 3 gfb2/io143pdb3 none none none 33 io205ndb3 io157ndb3 io143ndb3 none none none 34 gfc2/io204pdb3 gfc2/io156pdb 3 gfc2/io142pdb3 none none none 35 io204ndb3 io156ndb3 io142ndb3 none none none 36 v cc v cc nc none rule 4 rule 4 37 io199pdb3 io147pdb3 io141psb3 none none none 38 io199ndb3 io147ndb3 io140pdb3 none none none 39 io197psb3 io146psb3 io140ndb3 none none none 40 v cci b3 v cci b3 v cci b3 none none none 41 gnd gnd gnd none none none 42 io191pdb3 io145pdb3 io138pdb3 none none none 43 io191ndb3 io145ndb3 io138ndb3 none none none 44 gec1/io190pdb3 gec1/io144pd b3 gec1/io137pdb3 none none none 45 gec0/io190ndb3 gec0/io144ndb3 gec0/io137ndb3 none none none 46 geb1/io189pdb3 geb1/io143pd b3 geb1/io136pdb3 none none none 47 geb0/io189ndb3 geb0/io143ndb3 geb0/io136ndb3 none none none 48 gea1/io188pdb3 gea1/io142pdb3 gea1/io135pdb3 none none none 49 gea0/io188ndb3 gea0/io142ndb 3 gea0/io135ndb3 none none none 50 vmv3 vmv3 vmv3 none none none 51 gndq gndq gndq none none none 52 gnd gnd gnd none none none 53 vmv2 vmv2 vmv2 none none none 54 gea2/io187rsb2 gea2/io141r sb2 nc none rule 1 rule 1 55 geb2/io186rsb2 geb2/io140rsb 2 gea2/io134rsb2 none none none 56 gec2/io185rsb2 gec2/io139rsb 2 geb2/io133rsb2 none none none 57 io184rsb2 io138rsb2 gec2/io 132rsb2 none rule 2 rule 2 58 io183rsb2 io137rsb2 i o131rsb2 none none none 59 io182rsb2 io136rsb2 i o130rsb2 none none none 60 io181rsb2 io135rsb2 i o129rsb2 none none none 61 io180rsb2 io134rsb2 i o128rsb2 none none none 62 v cci b2 v cci b2 v cci b2 none none none table 12-4 ? pin compatibility and migration tabl e for the pq208 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-7 63 io178rsb2 io133rsb2 i o125rsb2 none none none 64 io176rsb2 io131rsb2 i o123rsb2 none none none 65 gnd gnd gnd none none none 66 io174rsb2 io129rsb2 i o121rsb2 none none none 67 io172rsb2 io127rsb2 i o119rsb2 none none none 68 io170rsb2 io125rsb2 i o117rsb2 none none none 69 io168rsb2 io123rsb2 i o115rsb2 none none none 70 io166rsb2 io121rsb2 i o113rsb2 none none none 71 v cc v cc v cc none none none 72 v cci b2 v cci b2 v cci b2 none none none 73 io162rsb2 io118rsb2 i o112rsb2 none none none 74 io160rsb2 io117rsb2 i o111rsb2 none none none 75 io158rsb2 io116rsb2 i o110rsb2 none none none 76 io156rsb2 io115rsb2 i o109rsb2 none none none 77 io154rsb2 io114rsb2 i o108rsb2 none none none 78 io152rsb2 io113rsb2 i o107rsb2 none none none 79 io150rsb2 io112rsb2 i o106rsb2 none none none 80 io148rsb2 io110rsb2 i o104rsb2 none none none 81 gnd gnd gnd none none none 82 io143rsb2 io109rsb2 i o102rsb2 none none none 83 io141rsb2 io108rsb2 i o101rsb2 none none none 84 io139rsb2 io107rsb2 i o100rsb2 none none none 85 io137rsb2 io106rsb2 i o99rsb2 none none none 86 io135rsb2 io105rsb2 i o98rsb2 none none none 87 io133rsb2 io104rsb2 i o97rsb2 none none none 88 v cc v cc v cc none none none 89 v cci b2 v cci b2 v cci b2 none none none 90 io128rsb2 io102rsb2 i o94rsb2 none none none 91 io126rsb2 io100rsb2 i o92rsb2 none none none 92 io124rsb2 io98rsb2 i o90rsb2 none none none 93 io122rsb2 io96rsb2 i o88rsb2 none none none 94 io120rsb2 io94rsb2 i o86rsb2 none none none 95 io118rsb2 io90rsb2 i o84rsb2 none none none table 12-4 ? pin compatibility and migration tabl e for the pq208 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-8 v1.1 96 gdc2/io116rsb2 gdc2/io89rsb2 gdc2/io82rsb2 none none none 97 gnd gnd gnd none none none 98 gdb2/io115rsb2 gdb2/io88rsb2 gdb2/io81rsb2 none none none 99 gda2/io114rsb2 gda2/io87rsb 2 gda2/io80rsb2 none none none 100 gndq gndq gndq none none none 101 tck tck tck none none none 102 tdi tdi tdi none none none 103 tms tms tms none none none 104 vmv2 vmv2 vmv2 none none none 105 gnd gnd gnd none none none 106 v pump v pump v pump none none none 107 gndq gndq nc none rule 8 rule 8 108 tdo tdo tdo none none none 109 trst trst trst none none none 110 v jtag v jtag v jtag none none none 111 gda0/io113ndb1 gda0/io86ndb1 g da0/io79vdb1 none none none 112 gda1/io113pdb1 gda1/io86pdb1 gda1/io79udb1 none none none 113 gdb0/io112ndb1 gdb0/io85ndb1 gdb0/io78vdb1 none none none 114 gdb1/io112pdb1 gdb1/io85pdb1 g db1/io78udb1 none none none 115 gdc0/io111ndb1 gdc0/io84ndb1 gdc0/io77vdb1 none none none 116 gdc1/io111pdb1 gdc1/io84pdb1 g dc1/io77udb1 none none none 117 io109ndb1 io82ndb1 io76vdb1 none none none 118 io109pdb1 io82pdb1 io76udb1 none none none 119 io106ndb1 io80ndb1 io75ndb1 none none none 120 io106pdb1 io80pdb1 io75pdb1 none none none 121 io104psb1 io79psb1 i o74rsb1 none none none 122 gnd gnd gnd none none none 123 v cci b1 v cci b1 v cci b1 none none none 124 io99ndb1 io75ndb1 nc none rule 1 rule 1 125 io99pdb1 io75pdb1 nc none rule 1 rule 1 126 nc nc v cc none rule 4 rule 4 127 io96ndb1 io73ndb1 io72ndb1 none none none 128 gcc2/io96pdb1 gcc2/io73pdb1 gcc2/io72pdb1 none none none table 12-4 ? pin compatibility and migration tabl e for the pq208 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-9 129 gcb2/io95psb1 gcb2/io72psb1 gcb2/io71psb1 none none none 130 gnd gnd gnd none none none 131 gca2/io94psb1 gca2/io71psb1 gca2/io70psb1 none none none 132 gca1/io93pdb1 gca1/io70pdb 1 gca1/io69pdb1 none none none 133 gca0/io93ndb1 gca0/io70ndb 1 gca0/io69ndb1 none none none 134 gcb0/io92ndb1 gcb0/io69ndb1 g cb0/io68ndb1 none none none 135 gcb1/io92pdb1 gcb1/io69pdb1 gcb1/io68pdb1 none none none 136 gcc0/io91ndb1 gcc0/io68ndb1 g cc0/io67ndb1 none none none 137 gcc1/io91pdb1 gcc1/io68pdb1 gcc1/io67pdb1 none none none 138 io88ndb1 io66ndb1 io66ndb1 none none none 139 io88pdb1 io66pdb1 io 66pdb1 none none none 140 v cci b1 v cci b1 v cci b1 none none none 141 gnd gnd gnd none none none 142 v cc v cc v cc none none none 143 io86psb1 io65psb1 io65rsb1 none none none 144 io84ndb1 io64ndb1 io64ndb1 none none none 145 io84pdb1 io64pdb1 io 64pdb1 none none none 146 io82ndb1 io63ndb1 io63ndb1 none none none 147 io82pdb1 io63pdb1 io 63pdb1 none none none 148 io80ndb1 io62ndb1 io62ndb1 none none none 149 gbc2/io80pdb1 gbc2/io62pdb1 gbc2/io62pdb1 none none none 150 io79ndb1 io61ndb1 io61ndb1 none none none 151 gbb2/io79pdb1 gbb2/io61pdb1 gbb2/io61pdb1 none none none 152 io78ndb1 io60ndb1 io60ndb1 none none none 153 gba2/io78pdb1 gba2/io60pdb 1 gba2/io60pdb1 none none none 154 vmv1 vmv1 vmv1 none none none 155 gndq gndq gndq none none none 156 gnd gnd gnd none none none 157 vmv0 vmv0 vmv0 none none none 158 gba1/io77rsb0 gba1/io59rsb0 gba1/io59rsb0 none none none 159 gba0/io76rsb0 gba0/io58rsb0 gba0/io58rsb0 none none none 160 gbb1/io75rsb0 gbb1/io57rsb0 gbb1/io57rsb0 none none none 161 gbb0/io74rsb0 gbb0/io56rsb0 gbb0/io56rsb0 none none none table 12-4 ? pin compatibility and migration tabl e for the pq208 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-10 v1.1 162 gnd gnd gnd none none none 163 gbc1/io73rsb0 gbc1/io55rsb0 gbc1/io55rsb0 none none none 164 gbc0/io72rsb0 gbc0/io54rsb0 gbc0/io54rsb0 none none none 165 io70rsb0 io52rsb0 io52rsb0 none none none 166 io67rsb0 io50rsb0 io49rsb0 none none none 167 io63rsb0 io48rsb0 io46rsb0 none none none 168 io60rsb0 io46rsb0 io43rsb0 none none none 169 io57rsb0 io44rsb0 io40rsb0 none none none 170 v cci b0 v cci b0 v cci b0 none none none 171 v cc v cc v cc none none none 172 io54rsb0 io36rsb0 io36rsb0 none none none 173 io51rsb0 io35rsb0 io35rsb0 none none none 174 io48rsb0 io34rsb0 io34rsb0 none none none 175 io45rsb0 io33rsb0 io33rsb0 none none none 176 io42rsb0 io32rsb0 io32rsb0 none none none 177 io40rsb0 io31rsb0 io31rsb0 none none none 178 gnd gnd gnd none none none 179 io38rsb0 io29rsb0 io29rsb0 none none none 180 io35rsb0 io28rsb0 io28rsb0 none none none 181 io33rsb0 io27rsb0 io27rsb0 none none none 182 io31rsb0 io26rsb0 io26rsb0 none none none 183 io29rsb0 io25rsb0 io25rsb0 none none none 184 io27rsb0 io24rsb0 io24rsb0 none none none 185 io25rsb0 io23rsb0 io23rsb0 none none none 186 v cci b0 v cci b0 v cci b0 none none none 187 v cc v cc v cc none none none 188 io22rsb0 io20rsb0 io21rsb0 none none none 189 io20rsb0 io19rsb0 io20rsb0 none none none 190 io18rsb0 io18rsb0 io19rsb0 none none none 191 io16rsb0 io17rsb0 io18rsb0 none none none 192 io15rsb0 io16rsb0 io17rsb0 none none none 193 io14rsb0 io14rsb0 io16rsb0 none none none 194 io13rsb0 io12rsb0 io15rsb0 none none none table 12-4 ? pin compatibility and migration tabl e for the pq208 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-11 195 gnd gnd gnd none none none 196 io12rsb0 io10rsb0 io13rsb0 none none none 197 io11rsb0 io09rsb0 io11rsb0 none none none 198 io10rsb0 io08rsb0 io09rsb0 none none none 199 io09rsb0 io07rsb0 io07rsb0 none none none 200 v cci b0 v cci b0 v cci b0 none none none 201 gac1/io05rsb0 gac1/io05rsb0 gac1/io05rsb0 none none none 202 gac0/io04rsb0 gac0/io04rsb0 gac0/io04rsb0 none none none 203 gab1/io03rsb0 gab1/io03rsb0 gab1/io03rsb0 none none none 204 gab0/io02rsb0 gab0/io02rsb0 gab0/io02rsb0 none none none 205 gaa1/io01rsb0 gaa1/ io01rsb0 gaa1/io01r sb0 none none none 206 gaa0/io00rsb0 gaa0/ io00rsb0 gaa0/io00r sb0 none none none 207 gndq gndq gndq none none none 208 vmv0 vmv0 vmv0 none none none table 12-4 ? pin compatibility and migration tabl e for the pq208 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-12 v1.1 fg144 package table 12-5 ? pin compatibility and migratio n table for the fg144 package pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 a1 gndq gndq gndq none none none a2 vmv0 vmv0 vmv0 none none none a3 gab0/io02rsb0 gab0/io02rsb 0 gab0/io02rsb0 none none none a4 gab1/io03rsb0 gab1/io03rsb 0 gab1/io03rsb0 none none none a5 io10rsb0 io10rsb0 io16rsb0 none none none a6 gnd gnd gnd none none none a7 io44rsb0 io44rsb0 io30rsb0 none none none a8 v cc v cc v cc none none none a9 io69rsb0 io69rsb0 io34rsb0 none none none a10 gba0/io76rsb0 gba0/io76rsb0 gba0/io58rsb0 none none none a11 gba1/io77rsb0 gba1/io77rsb0 gba1/io59rsb0 none none none a12 gndq gndq gndq none none none b1 gab2/io224pdb3 gab2/io224pdb3 gab2/io154udb3 n one none none b2 gnd gnd gnd none none none b3 gaa0/io00rsb0 gaa0/ io00rsb0 gaa0/io00r sb0 none none none b4 gaa1/io01rsb0 gaa1/ io01rsb0 gaa1/io01r sb0 none none none b5 io13rsb0 io13rsb0 io14rsb0 none none none b6 io26rsb0 io26rsb0 io19rsb0 none none none b7 io35rsb0 io35rsb0 io23rsb0 none none none b8 io60rsb0 io60rsb0 io31rsb0 none none none b9 gbb0/io74rsb0 gbb0/io74rsb0 gbb0/io56rsb0 none none none b10 gbb1/io75rsb0 gbb1/io75rsb0 gbb1/io57rsb0 none none none b11 gnd gnd gnd none none none b12 vmv1 vmv1 vmv1 none none none c1 io224ndb3 io224ndb3 io154vdb3 none none none c2 gfa2/io206ppb3 gfa2/io206ppb 3 gfa2/io144ppb3 n one none none c3 gac2/io223pdb3 gac2/io223pdb3 gac2/io153udb3 n one none none c4 v cc v cc v cc none none none c5 io16rsb0 io16rsb0 io12rsb0 none none none c6 io29rsb0 io29rsb0 io17rsb0 none none none c7 io32rsb0 io32rsb0 io25rsb0 none none none migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-13 c8 io63rsb0 io63rsb0 io32rsb0 none none none c9 io66rsb0 io66rsb0 io53rsb0 none none none c10 gba2/io78pdb1 gba2/io78pdb1 gba2/io60pdb1 none none none c11 io78ndb1 io78ndb1 i o60ndb1 none none none c12 gbc2/io80ppb1 gbc2/io80ppb 1 gbc2/io62ppb1 none none none d1 io213pdb3 io213pdb3 io 149ndb3 none none none d2 io213ndb3 io213ndb3 io149pdb3 none none none d3 io223ndb3 io223ndb3 io153vdb3 none none none d4 gaa2/io225ppb3 gaa2/io225ppb3 gaa2/io155upb3 none none none d5 gac0/io04rsb0 gac0/io04rsb 0 gac0/io04rsb0 none none none d6 gac1/io05rsb0 gac1/io05rsb 0 gac1/io05rsb0 none none none d7 gbc0/io72rsb0 gbc0/io72rsb0 gbc0/io54rsb0 none none none d8 gbc1/io73rsb0 gbc1/io73rsb0 gbc1/io55rsb0 none none none d9 gbb2/io79pdb1 gbb2/io79pdb 1 gbb2/io61pdb1 n one none none d10 io79ndb1 io79ndb1 i o61ndb1 none none none d11 io80npb1 io80npb1 io62npb1 none none none d12 gcb1/io92ppb1 gcb1/io92ppb 1 gcb1/io68ppb1 none none none e1 v cc v cc v cc none none none e2 gfc0/io209ndb3 gfc0/io209ndb 3 gfc0/io147ndb3 none none none e3 gfc1/io209pdb3 gfc1/io209pdb3 gfc1/io147pdb3 none none none e4 v cci b3 v cci b3 v cci b3 none none none e5 io225npb3 io225npb3 io155vpb3 none none none e6 v cci b0 v cci b0 v cci b0 none none none e7 v cci b0 v cci b0 v cci b0 none none none e8 gcc1/io91pdb1 gcc1/io91pdb 1 gcc1/io67pdb1 n one none none e9 v cci b1 v cci b1 v cci b1 none none none e10 v cc v cc v cc none none none e11 gca0/io93ndb1 gca0/io93ndb 1 gca0/io69ndb1 none none none e12 io94ndb1 io94ndb1 io7 0ndb1 none none none f1 gfb0/io208npb3 gfb0/io208npb3 gfb0/io146npb3 none none none f2 v complf v complf v complf none none none f3 gfb1/io208ppb3 gfb1/io208pp b3 gfb1/io146ppb3 none none none f4 io206npb3 io206npb3 io144npb3 none none none table 12-5 ? pin compatibility and migration tabl e for the fg144 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-14 v1.1 f5 gnd gnd gnd none none none f6 gnd gnd gnd none none none f7 gnd gnd gnd none none none f8 gcc0/io91ndb1 gcc0/io91ndb1 g cc0/io67ndb1 none none none f9 gcb0/io92npb1 gcb0/io92npb 1 gcb0/io68npb1 none none none f10 gnd gnd gnd none none none f11 gca1/io93pdb1 gca1/io93pdb1 gca1/io69pdb1 none none none f12 gca2/io94pdb1 gca2/io94pdb1 gca2/io70pdb1 none none none g1 gfa1/io207ppb3 gfa1/io207ppb 3 gfa1/io145ppb3 n one none none g2 gnd gnd gnd none none none g3 v ccplf v ccplf v ccplf none none none g4 gfa0/io207npb3 gfa0/io207npb3 gfa0/io145npb3 none none none g5 gnd gnd gnd none none none g6 gnd gnd gnd none none none g7 gnd gnd gnd none none none g8 gdc1/io111ppb1 gdc1/ io111ppb1 gdc1/io77upb1 none none none g9 io96ndb1 io96ndb1 io7 2ndb1 none none none g10 gcc2/io96pdb1 gcc2/io96pdb 1 gcc2/io72pdb1 n one none none g11 io95ndb1 io95ndb1 i o71ndb1 none none none g12 gcb2/io95pdb1 gcb2/io95pdb 1 gcb2/io71pdb1 n one none none h1 v cc v cc v cc none none none h2 gfb2/io205pdb3 gfb2/io205pdb3 gfb2/io143pdb3 none none none h3 gfc2/io204psb3 gfc2/io204psb3 g fc2/io142psb3 none none none h4 gec1/io190pdb3 gec1/io190pd b3 gec1/io137pdb3 none none none h5 v cc v cc v cc none none none h6 io105pdb1 io105pdb1 io 75pdb1 none none none h7 io105ndb1 io105ndb1 io75ndb1 none none none h8 gdb2/io115rsb2 gdb2/ io115rsb2 gdb2/io81rsb2 none none none h9 gdc0/io111npb1 gdc0/io111npb 1 gdc0/io77vpb1 none none none h10 v cci b1 v cci b1 v cci b1 none none none h11 io101psb1 io101psb1 io73psb1 none none none h12 v cc v cc v cc none none none j1 geb1/io189pdb3 geb1/io189pd b3 geb1/io136pdb3 none none none table 12-5 ? pin compatibility and migration tabl e for the fg144 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-15 j2 io205ndb3 io205ndb3 io143ndb3 none none none j3 v cci b3 v cci b3 v cci b3 none none none j4 gec0/io190ndb3 gec0/io190ndb 3 gec0/io137ndb3 none none none j5 io160rsb2 io160rsb2 io125rsb2 none none none j6 io157rsb2 io157rsb2 io116rsb2 none none none j7 v cc v cc v cc none none none j8 tck tck tck none none none j9 gda2/io114rsb2 gda2/io114rsb 2 gda2/io80rsb2 none none none j10 tdo tdo tdo none none none j11 gda1/io113pdb1 gda1/io113pdb1 gda1/io79udb1 none none none j12 gdb1/io112pdb1 gdb1/io112pdb 1 gdb1/io78udb1 none none none k1 geb0/io189ndb3 geb0/io189ndb 3 geb0/io136ndb3 none none none k2 gea1/io188pdb3 gea1/io188pdb3 gea1/io135pdb3 none none none k3 gea0/io188ndb3 gea0/io188ndb 3 gea0/io135ndb3 none none none k4 gea2/io187rsb2 gea2/io187rsb2 gea2/io134rsb2 none none none k5 io169rsb2 io169rsb2 io127rsb2 none none none k6 io152rsb2 io152rsb2 io121rsb2 none none none k7 gnd gnd gnd none none none k8 io117rsb2 io117rsb2 io104rsb2 none none none k9 gdc2/io116rsb2 gdc2/io116rsb2 gdc2/io82rsb2 none none none k10 gnd gnd gnd none none none k11 gda0/io113ndb1 gda0/io113ndb 1 gda0/io79vdb1 none none none k12 gdb0/io112ndb1 gdb 0/io112ndb1 gdb0/io 78vdb1 none none none l1 gnd gnd gnd none none none l2 vmv3 vmv3 vmv3 none none none l3 geb2/io186rsb2 geb2/io186rsb 2 geb2/io133rsb2 none none none l4 io172rsb2 io172rsb2 io128rsb2 none none none l5 v cci b2 v cci b2 v cci b2 none none none l6 io153rsb2 io153rsb2 io119rsb2 none none none l7 io144rsb2 io144rsb2 io114rsb2 none none none l8 io140rsb2 io140rsb2 io110rsb2 none none none l9 tms tms tms none none none l10 v jtag v jtag v jtag none none none table 12-5 ? pin compatibility and migration tabl e for the fg144 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-16 v1.1 l11 vmv2 vmv2 vmv2 none none none l12 trst trst trst none none none m1 gndq gndq gndq none none none m2 gec2/io185rsb2 gec2/io185rsb 2 gec2/io132rsb2 none none none m3 io173rsb2 io173rsb2 io129rsb2 none none none m4 io168rsb2 io168rsb2 io126rsb2 none none none m5 io161rsb2 io161rsb2 io124rsb2 none none none m6 io156rsb2 io156rsb2 io122rsb2 none none none m7 io145rsb2 io145rsb2 io117rsb2 none none none m8 io141rsb2 io141rsb2 io115rsb2 none none none m9 tdi tdi tdi none none none m10 v cci b2 v cci b2 v cci b2 none none none m11 v pump v pump v pump none none none m12 gndq gndq gndq none none none table 12-5 ? pin compatibility and migration tabl e for the fg144 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-17 fg256 package table 12-6 ? pin compatibility and migratio n table for the fg256 package pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 a1 gnd gnd gnd none none none a2 gaa0/io00rsb0 gaa0/ io00rsb0 gaa0/io00r sb0 none none none a3 gaa1/io01rsb0 gaa1/ io01rsb0 gaa1/io01r sb0 none none none a4 gab0/io02rsb0 gab0/io02rsb0 gab0/io02rsb0 none none none a5 io16rsb0 io11rsb0 io16rsb0 none none none a6 io22rsb0 io16rsb0 io17rsb0 none none none a7 io28rsb0 io18rsb0 io22rsb0 none none none a8 io35rsb0 io28rsb0 io28rsb0 none none none a9 io45rsb0 io34rsb0 io34rsb0 none none none a10 io50rsb0 io37rsb0 i o37rsb0 none none none a11 io55rsb0 io41rsb0 i o41rsb0 none none none a12 io61rsb0 io43rsb0 i o43rsb0 none none none a13 gbb1/io75rsb0 gbb1/io57rsb0 gbb1/io57rsb0 none none none a14 gba0/io76rsb0 gba0/io58rsb0 gba0/io58rsb0 none none none a15 gba1/io77rsb0 gba1/io59rsb0 gba1/io59rsb0 none none none a16 gnd gnd gnd none none none b1 gab2/io224pdb3 gab2/io173pdb3 gab2/io154udb3 n one none none b2 gaa2/io225pdb3 gaa2/io174pdb3 gaa2/io155udb3 none none none b3 gndq gndq io12rsb0 none rule 8 rule 8 b4 gab1/io03rsb0 gab1/io03rsb0 gab1/io03rsb0 none none none b5 io17rsb0 io13rsb0 io13rsb0 none none none b6 io21rsb0 io14rsb0 io14rsb0 none none none b7 io27rsb0 io21rsb0 io21rsb0 none none none b8 io34rsb0 io27rsb0 io27rsb0 none none none b9 io44rsb0 io32rsb0 io32rsb0 none none none b10 io51rsb0 io38rsb0 io38rsb0 none none none b11 io57rsb0 io42rsb0 io42rsb0 none none none b12 gbc1/io73rsb0 gbc1/io55rsb0 gbc1/io55rsb0 none none none b13 gbb0/io74rsb0 gbb0/io56rsb0 gbb0/io56rsb0 none none none b14 io71rsb0 io52rsb0 io44rsb0 none none none b15 gba2/io78pdb1 gba2/io60pdb 1 gba2/io60pdb1 none none none migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-18 v1.1 b16 io81pdb1 io60ndb1 io60ndb1 none none none c1 io224ndb3 io173ndb3 io154vdb3 none none none c2 io225ndb3 io174ndb3 io155vdb3 none none none c3 vmv3 vmv3 io11rsb0 none rule 7 rule 7 c4 io11rsb0 io07rsb0 io07rsb0 none none none c5 gac0/io04rsb0 gac0/io04rsb0 gac0/io04rsb0 none none none c6 gac1/io05rsb0 gac1/io05rsb0 gac1/io05rsb0 none none none c7 io25rsb0 io20rsb0 io20rsb0 none none none c8 io36rsb0 io24rsb0 io24rsb0 none none none c9 io42rsb0 io33rsb0 io33rsb0 none none none c10 io49rsb0 io39rsb0 io39rsb0 none none none c11 io56rsb0 io44rsb0 io45rsb0 none none none c12 gbc0/io72rsb0 gbc0/io54rsb0 gbc0/io54rsb0 none none none c13 io62rsb0 io51rsb0 io48rsb0 none none none c14 vmv0 vmv0 vmv0 none none none c15 io78ndb1 io61npb1 io61npb1 none none none c16 io81ndb1 io63pdb1 io63pdb1 none none none d1 io222ndb3 io171ndb3 io151vdb3 none none none d2 io222pdb3 io171pdb3 io151udb3 none none none d3 gac2/io223pdb3 gac2/io172pdb3 gac2/io153udb3 n one none none d4 io223ndb3 io06rsb0 io06rsb0 none none none d5 gndq gndq gndq none none none d6 io23rsb0 io10rsb0 io10rsb0 none none none d7 io29rsb0 io19rsb0 io19rsb0 none none none d8 io33rsb0 io26rsb0 io26rsb0 none none none d9 io46rsb0 io30rsb0 io30rsb0 none none none d10 io52rsb0 io40rsb0 i o40rsb0 none none none d11 io60rsb0 io45rsb0 i o46rsb0 none none none d12 gndq gndq gndq none none none d13 io80ndb1 io50rsb0 io47rsb0 none none none d14 gbb2/io79pdb1 gbb2/io61ppb 1 gbb2/io61ppb1 n one none none d15 io79ndb1 io53rsb0 io53rsb0 none none none d16 io82nsb1 io63ndb1 io63ndb1 none none none table 12-6 ? pin compatibility and migration tabl e for the fg256 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-19 e1 io217pdb3 io166pdb3 io150pdb3 none none none e2 io218pdb3 io167npb3 io08rsb0 none none none e3 io221ndb3 io172ndb3 io153vdb3 none none none e4 io221pdb3 io169ndb3 io152vdb3 none none none e5 vmv0 vmv0 vmv0 none none none e6 v cci b0 v cci b0 v cci b0 none none none e7 v cci b0 v cci b0 v cci b0 none none none e8 io38rsb0 io25rsb0 io25rsb0 none none none e9 io47rsb0 io31rsb0 io31rsb0 none none none e10 v cci b0 v cci b0 v cci b0 none none none e11 v cci b0 v cci b0 v cci b0 none none none e12 vmv1 vmv1 vmv1 none none none e13 gbc2/io80pdb1 gbc2/io62pdb1 gbc2/io62pdb1 none none none e14 io83ppb1 io67ppb1 io6 5rsb1 none none none e15 io86ppb1 io64ppb1 io5 2rsb0 none none none e16 io87pdb1 io66pdb1 io66pdb1 none none none f1 io217ndb3 io166ndb3 io150ndb3 none none none f2 io218ndb3 io168npb3 io149npb3 none none none f3 io216pdb3 io167ppb3 io09rsb0 none none none f4 io216ndb3 io169pdb3 io152udb3 none none none f5 v cci b3 v cci b3 v cci b3 none none none f6 gnd gnd gnd none none none f7 v cc v cc v cc none none none f8 v cc v cc v cc none none none f9 v cc v cc v cc none none none f10 v cc v cc v cc none none none f11 gnd gnd gnd none none none f12 v cci b1 v cci b1 v cci b1 none none none f13 io83npb1 io62ndb1 io62ndb1 none none none f14 io86npb1 io64npb1 i o49rsb0 none none none f15 io90ppb1 io65ppb1 i o64ppb1 none none none f16 io87ndb1 io66ndb1 io66ndb1 none none none g1 io210psb3 io165ndb3 io148ndb3 none none none table 12-6 ? pin compatibility and migration tabl e for the fg256 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-20 v1.1 g2 io213ndb3 io165pdb3 io148pdb3 none none none g3 io213pdb3 io168ppb3 io149ppb3 none none none g4 gfc1/io209ppb3 gfc1/io164ppb 3 gfc1/io147ppb3 n one none none g5 v cci b3 v cci b3 v cci b3 none none none g6 v cc v cc v cc none none none g7 gnd gnd gnd none none none g8 gnd gnd gnd none none none g9 gnd gnd gnd none none none g10 gnd gnd gnd none none none g11 v cc v cc v cc none none none g12 v cci b1 v cci b1 v cci b1 none none none g13 gcc1/io91ppb1 gcc 1/io69ppb1 gcc 1/io67ppb1 non e none none g14 io90npb1 io65npb1 i o64npb1 none none none g15 io88pdb1 io75pdb1 io73pdb1 none none none g16 io88ndb1 io75ndb1 io73ndb1 none none none h1 gfb0/io208npb3 gfb0/io163npb 3 gfb0/io146npb3 none none none h2 gfa0/io207ndb3 gfa0/io162ndb 3 gfa0/io145ndb3 none none none h3 gfb1/io208ppb3 gfb1/io163ppb 3 gfb1/io146ppb3 n one none none h4 v complf v complf v complf none none none h5 gfc0/io209npb3 gfc0/io164npb 3 gfc0/io147npb3 none none none h6 v cc v cc v cc none none none h7 gnd gnd gnd none none none h8 gnd gnd gnd none none none h9 gnd gnd gnd none none none h10 gnd gnd gnd none none none h11 v cc v cc v cc none none none h12 gcc0/io91npb1 gcc0/io69npb1 gcc0/io67npb1 none none none h13 gcb1/io92ppb1 gcb 1/io70ppb1 gcb 1/io68ppb1 non e none none h14 gca0/io93npb1 gca0/io71npb 1 gca0/io69npb1 none none none h15 io96npb1 io67npb1 n c none rule 1 rule 1 h16 gcb0/io92npb1 gcb0/io70npb1 gcb0/io68npb1 none none none j1 gfa2/io206psb3 gfa2/io161ppb 3 gfa2/io144ppb3 none none none j2 gfa1/io207pdb3 gfa1/io162pdb3 gfa1/io145pdb3 none none none table 12-6 ? pin compatibility and migration tabl e for the fg256 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-21 j3 v ccplf v ccplf v ccplf none none none j4 io205ndb3 io160ndb3 io143ndb3 none none none j5 gfb2/io205pdb3 gfb2/io160pdb 3 gfb2/io143pdb3 none none none j6 v cc v cc v cc none none none j7 gnd gnd gnd none none none j8 gnd gnd gnd none none none j9 gnd gnd gnd none none none j10 gnd gnd gnd none none none j11 v cc v cc v cc none none none j12 gcb2/io95ppb1 gcb 2/io73ppb1 gcb 2/io71ppb1 non e none none j13 gca1/io93ppb1 gca1/io71ppb 1 gca1/io69ppb1 none none none j14 gcc2/io96ppb1 gcc 2/io74ppb1 gcc 2/io72ppb1 non e none none j15 io100ppb1 io80ppb1 n c none rule 1 rule 1 j16 gca2/io94psb1 gca2/io72pdb 1 gca2/io70pdb1 none none none k1 gfc2/io204pdb3 gfc2/io159pdb 3 gfc2/io142pdb3 none none none k2 io204ndb3 io161npb3 io144npb3 none none none k3 io203ndb3 io156ppb3 io141ppb3 none none none k4 io203pdb3 io129rsb2 i o120rsb2 none none none k5 v cci b3 v cci b3 v cci b3 none none none k6 v cc v cc v cc none none none k7 gnd gnd gnd none none none k8 gnd gnd gnd none none none k9 gnd gnd gnd none none none k10 gnd gnd gnd none none none k11 v cc v cc v cc none none none k12 v cci b1 v cci b1 v cci b1 none none none k13 io95npb1 io73npb1 i o71npb1 none none none k14 io100npb1 io80npb1 io74rsb1 none none none k15 io102ndb1 io74npb1 io72npb1 none none none k16 io102pdb1 io72ndb1 io70ndb1 none none none l1 io202ndb3 io159ndb3 io142ndb3 none none none l2 io202pdb3 io156npb3 io141npb3 none none none l3 io196ppb3 io151ppb3 io125rsb2 none none none table 12-6 ? pin compatibility and migration tabl e for the fg256 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-22 v1.1 l4 io193ppb3 io158psb3 io139rsb3 none none none l5 v cci b3 v cci b3 v cci b3 none none none l6 gnd gnd gnd none none none l7 v cc v cc v cc none none none l8 v cc v cc v cc none none none l9 v cc v cc v cc none none none l10 v cc v cc v cc none none none l11 gnd gnd gnd none none none l12 v cci b1 v cci b1 v cci b1 none none none l13 gdb0/io112npb1 gdb0/io87npb 1 gdb0/io78vpb1 none none none l14 io106ndb1 io85ndb1 io76vdb1 none none none l15 io106pdb1 io85pdb1 io76udb1 none none none l16 io107pdb1 io84pdb1 io75pdb1 none none none m1 io197nsb3 io150pdb3 io140pdb3 none none none m2 io196npb3 io151npb3 io 130rsb2 none none none m3 io193npb3 io147npb3 io138npb3 none none none m4 gec0/io190npb3 gec0/io146np b3 gec0/io137npb3 none none none m5 vmv3 vmv3 vmv3 none none none m6 v cci b2 v cci b2 v cci b2 none none none m7 v cci b2 v cci b2 v cci b2 none none none m8 io147rsb2 io117rsb2 i o108rsb2 none none none m9 io136rsb2 io110rsb2 i o101rsb2 none none none m10 v cci b2 v cci b2 v cci b2 none none none m11 v cci b2 v cci b2 v cci b2 none none none m12 vmv2 vmv2 vmv2 none none none m13 io110ndb1 io94rsb2 io83rsb2 none none none m14 gdb1/io112ppb1 gdb1/io87ppb 1 gdb1/io78upb1 n one none none m15 gdc1/io111pdb1 gdc1/io86pdb 1 gdc1/io77udb1 none none none m16 io107ndb1 io84ndb1 io75ndb1 none none none n1 io194psb3 io150ndb3 io140ndb3 none none none n2 io192ppb3 io147ppb3 io138ppb3 none none none n3 gec1/io190ppb3 gec1/io146ppb3 gec1/io137ppb3 none none none n4 io192npb3 io140rsb2 i o131rsb2 none none none table 12-6 ? pin compatibility and migration tabl e for the fg256 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-23 n5 gndq gndq gndq none none none n6 gea2/io187rsb2 gea2/io143rsb 2 gea2/io134rsb2 none none none n7 io161rsb2 io126rsb2 i o117rsb2 none none none n8 io155rsb2 io120rsb2 i o111rsb2 none none none n9 io141rsb2 io108rsb2 i o99rsb2 none none none n10 io129rsb2 io103rsb2 i o94rsb2 none none none n11 io124rsb2 io99rsb2 i o87rsb2 none none none n12 gndq gndq gndq none none none n13 io110pdb1 io92rsb2 io93rsb2 none none none n14 v jtag v jtag v jtag none none none n15 gdc0/io111ndb1 gdc0/io86ndb 1 gdc0/io77vdb1 none none none n16 gda1/io113pdb1 gda1/io88pdb1 gda1/io79udb1 none none none p1 geb1/io189pdb3 geb1/io145pd b3 geb1/io136pdb3 none none none p2 geb0/io189ndb3 geb0/io145ndb3 geb0/io136ndb3 none none none p3 vmv2 vmv2 vmv2 none none none p4 io179rsb2 io138rsb2 i o129rsb2 none none none p5 io171rsb2 io136rsb2 i o128rsb2 none none none p6 io165rsb2 io131rsb2 i o122rsb2 none none none p7 io159rsb2 io124rsb2 i o115rsb2 none none none p8 io151rsb2 io119rsb2 i o110rsb2 none none none p9 io137rsb2 io107rsb2 i o98rsb2 none none none p10 io134rsb2 io104rsb2 i o95rsb2 none none none p11 io128rsb2 io97rsb2 i o88rsb2 none none none p12 vmv1 vmv1 io84rsb2 none rule 7 rule 7 p13 tck tck tck none none none p14 v pump v pump v pump none none none p15 trst trst trst none none none p16 gda0/io113ndb1 gda0/io88ndb1 g da0/io79vdb1 none none none r1 gea1/io188pdb3 gea1/io144pdb3 gea1/io135pdb3 none none none r2 gea0/io188ndb3 gea0/io144ndb 3 gea0/io135ndb3 none none none r3 io184rsb2 io139rsb2 i o127rsb2 none none none r4 gec2/io185rsb2 gec2/io141rsb 2 gec2/io132rsb2 none none none r5 io168rsb2 io132rsb2 i o123rsb2 none none none table 12-6 ? pin compatibility and migration tabl e for the fg256 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-24 v1.1 r6 io163rsb2 io127rsb2 i o118rsb2 none none none r7 io157rsb2 io121rsb2 i o112rsb2 none none none r8 io149rsb2 io114rsb2 i o106rsb2 none none none r9 io143rsb2 io109rsb2 i o100rsb2 none none none r10 io138rsb2 io105rsb2 io96rsb2 none none none r11 io131rsb2 io98rsb2 io89rsb2 none none none r12 io125rsb2 io96rsb2 io85rsb2 none none none r13 gdb2/io115rsb2 gdb2/io90rsb2 gdb2/io81rsb2 none none none r14 tdi tdi tdi none none none r15 gndq gndq nc none rule 8 rule 8 r16 tdo tdo tdo none none none t1 gnd gnd gnd none none none t2 io183rsb2 io137rsb2 i o126rsb2 none none none t3 geb2/io186rsb2 geb2/io142rsb 2 geb2/io133rsb2 none none none t4 io172rsb2 io134rsb2 i o124rsb2 none none none t5 io170rsb2 io125rsb2 i o116rsb2 none none none t6 io164rsb2 io123rsb2 i o113rsb2 none none none t7 io158rsb2 io118rsb2 i o107rsb2 none none none t8 io153rsb2 io115rsb2 i o105rsb2 none none none t9 io142rsb2 io111rsb2 i o102rsb2 none none none t10 io135rsb2 io106rsb2 i o97rsb2 none none none t11 io130rsb2 io102rsb2 i o92rsb2 none none none t12 gdc2/io116rsb2 gdc2/io91rsb2 gdc2/io82rsb2 none none none t13 io120rsb2 io93rsb2 i o86rsb2 none none none t14 gda2/io114rsb2 gda2/io89rsb 2 gda2/io80rsb2 none none none t15 tms tms tms none none none t16 gnd gnd gnd none none none table 12-6 ? pin compatibility and migration tabl e for the fg256 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-25 fg484 package table 12-7 ? pin compatibility and migratio n table for the fg484 package pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 a1 gnd gnd gnd none none none a2 gnd gnd gnd none none none a3 v cci b0 v cci b0 v cci b0 none none none a4 io07rsb0 nc nc rule 1 rule 1 none a5 io09rsb0 nc nc rule 1 rule 1 none a6 io13rsb0 io09rsb0 io15rsb0 none none none a7 io18rsb0 io15rsb0 io18rsb0 none none none a8 io20rsb0 nc nc rule 1 rule 1 none a9 io26rsb0 nc nc rule 1 rule 1 none a10 io32rsb0 io22rsb0 i o23rsb0 none none none a11 io40rsb0 io23rsb0 i o29rsb0 none none none a12 io41rsb0 io29rsb0 i o35rsb0 none none none a13 io53rsb0 io35rsb0 i o36rsb0 none none none a14 io59rsb0 nc nc rule 1 rule 1 none a15 io64rsb0 nc nc rule 1 rule 1 none a16 io65rsb0 io46rsb0 i o50rsb0 none none none a17 io67rsb0 io48rsb0 i o51rsb0 none none none a18 io69rsb0 nc nc rule 1 rule 1 none a19 nc nc nc none none none a20 v cci b0 v cci b0 v cci b0 none none none a21 gnd gnd gnd none none none a22 gnd gnd gnd none none none aa1 gnd gnd gnd none none none aa2 v cci b3 v cci b3 v cci b3 none none none aa3 nc nc nc none none none aa4 io181rsb2 nc nc rule 1 rule 1 none aa5 io178rsb2 nc nc rule 1 rule 1 none aa6 io175rsb2 io135rsb2 n c none rule 1 rule 1 aa7 io169rsb2 io133rsb2 n c none rule 1 rule 1 aa8 io166rsb2 nc nc rule 1 rule 1 none aa9 io160rsb2 nc nc rule 1 rule 1 none migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-26 v1.1 aa10 io152rsb2 nc nc rule 1 rule 1 none aa11 io146rsb2 nc nc rule 1 rule 1 none aa12 io139rsb2 nc nc rule 1 rule 1 none aa13 io133rsb2 nc nc rule 1 rule 1 none aa14 nc nc nc none none none aa15 nc nc nc none none none aa16 io122rsb2 io101rsb2 n c none rule 1 rule 1 aa17 io119rsb2 nc nc rule 1 rule 1 none aa18 io117rsb2 nc nc rule 1 rule 1 none aa19 nc nc nc none none none aa20 nc nc nc none none none aa21 v cci b1 v cci b1 v cci b1 none none none aa22 gnd gnd gnd none none none ab1 gnd gnd gnd none none none ab2 gnd gnd gnd none none none ab3 v cci b2 v cci b2 v cci b2 none none none ab4 io180rsb2 nc nc rule 1 rule 1 none ab5 io176rsb2 nc nc rule 1 rule 1 none ab6 io173rsb2 io130rsb2 i o121rsb2 none none none ab7 io167rsb2 io128rsb2 i o119rsb2 none none none ab8 io162rsb2 io122rsb2 i o114rsb2 none none none ab9 io156rsb2 io116rsb2 i o109rsb2 none none none ab10 io150rsb2 nc nc rule 1 rule 1 none ab11 io145rsb2 nc nc rule 1 rule 1 none ab12 io144rsb2 io113rsb2 i o104rsb2 none none none ab13 io132rsb2 io112rsb2 i o103rsb2 none none none ab14 io127rsb2 nc nc rule 1 rule 1 none ab15 io126rsb2 nc nc rule 1 rule 1 none ab16 io123rsb2 io100rsb2 i o91rsb2 none none none ab17 io121rsb2 io95rsb2 io90rsb2 none none none ab18 io118rsb2 nc nc rule 1 rule 1 none ab19 nc nc nc none none none ab20 v cci b2 v cci b2 v cci b2 none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-27 ab21 gnd gnd gnd none none none ab22 gnd gnd gnd none none none b1 gnd gnd gnd none none none b2 v cci b3 v cci b3 v cci b3 none none none b3 nc nc nc none none none b4 io06rsb0 nc nc rule 1 rule 1 none b5 io08rsb0 nc nc rule 1 rule 1 none b6 io12rsb0 io08rsb0 nc none rule 1 rule 1 b7 io15rsb0 io12rsb0 nc none rule 1 rule 1 b8 io19rsb0 nc nc rule 1 rule 1 none b9 io24rsb0 nc nc rule 1 rule 1 none b10 io31rsb0 io17rsb0 nc none rule 1 rule 1 b11 io39rsb0 nc nc rule 1 rule 1 none b12 io48rsb0 nc nc rule 1 rule 1 none b13 io54rsb0 io36rsb0 nc none rule 1 rule 1 b14 io58rsb0 nc nc rule 1 rule 1 none b15 io63rsb0 nc nc rule 1 rule 1 none b16 io66rsb0 io47rsb0 nc none rule 1 rule 1 b17 io68rsb0 io49rsb0 nc none rule 1 rule 1 b18 io70rsb0 nc nc rule 1 rule 1 none b19 nc nc nc none none none b20 nc nc nc none none none b21 v cci b1 v cci b1 v cci b1 none none none b22 gnd gnd gnd none none none c1 v cci b3 v cci b3 v cci b3 none none none c2 io220pdb3 nc nc rule 1 rule 1 none c3 nc nc nc none none none c4 nc nc nc none none none c5 gnd gnd gnd none none none c6 io10rsb0 nc nc rule 1 rule 1 none c7 io14rsb0 nc nc rule 1 rule 1 none c8 v cc v cc v cc none none none c9 v cc v cc v cc none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-28 v1.1 c10 io30rsb0 nc nc rule 1 rule 1 none c11 io37rsb0 nc nc rule 1 rule 1 none c12 io43rsb0 nc nc rule 1 rule 1 none c13 nc nc nc none none none c14 v cc v cc v cc none none none c15 v cc v cc v cc none none none c16 nc nc nc none none none c17 nc nc nc none none none c18 gnd gnd gnd none none none c19 nc nc nc none none none c20 nc nc nc none none none c21 nc nc nc none none none c22 v cci b1 v cci b1 v cci b1 none none none d1 io219pdb3 nc nc rule 1 rule 1 none d2 io220ndb3 nc nc rule 1 rule 1 none d3 nc nc nc none none none d4 gnd gnd gnd none none none d5 gaa0/io00rsb0 gaa0/ io00rsb0 gaa0/io00r sb0 none none none d6 gaa1/io01rsb0 gaa1/ io01rsb0 gaa1/io01r sb0 none none none d7 gab0/io02rsb0 gab0/io02rsb0 gab0/io02rsb0 none none none d8 io16rsb0 io11rsb0 io16rsb0 none none none d9 io22rsb0 io16rsb0 io17rsb0 none none none d10 io28rsb0 io18rsb0 i o22rsb0 none none none d11 io35rsb0 io28rsb0 i o28rsb0 none none none d12 io45rsb0 io34rsb0 i o34rsb0 none none none d13 io50rsb0 io37rsb0 i o37rsb0 none none none d14 io55rsb0 io41rsb0 i o41rsb0 none none none d15 io61rsb0 io43rsb0 i o43rsb0 none none none d16 gbb1/io75rsb0 gbb1/io57rsb0 gbb1/io57rsb0 none none none d17 gba0/io76rsb0 gba0/io58rsb0 gba0/io58rsb0 none none none d18 gba1/io77rsb0 gba1/io59rsb0 gba1/io59rsb0 none none none d19 gnd gnd gnd none none none d20 nc nc nc none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-29 d21 nc nc nc none none none d22 nc nc nc none none none e1 io219ndb3 nc nc rule 1 rule 1 none e2 nc nc nc none none none e3 gnd gnd gnd none none none e4 gab2/io224pdb3 gab2/io173pdb3 gab2/io154udb3 n one none none e5 gaa2/io225pdb3 gaa2/io174pdb3 gaa2/io155udb3 none none none e6 gndq gndq io12rsb0 none rule 8 rule 8 e7 gab1/io03rsb0 gab1/io03rsb0 gab1/io03rsb0 none none none e8 io17rsb0 io13rsb0 io13rsb0 none none none e9 io21rsb0 io14rsb0 io14rsb0 none none none e10 io27rsb0 io21rsb0 io21rsb0 none none none e11 io34rsb0 io27rsb0 io27rsb0 none none none e12 io44rsb0 io32rsb0 io32rsb0 none none none e13 io51rsb0 io38rsb0 io38rsb0 none none none e14 io57rsb0 io42rsb0 io42rsb0 none none none e15 gbc1/io73rsb0 gbc1/io55rsb0 gbc1/io55rsb0 none none none e16 gbb0/io74rsb0 gbb0/io56rsb0 gbb0/io56rsb0 none none none e17 io71rsb0 io52rsb0 io44rsb0 none none none e18 gba2/io78pdb1 gba2/io60pdb 1 gba2/io60pdb1 none none none e19 io81pdb1 io60ndb1 io60ndb1 none none none e20 gnd gnd gnd none none none e21 nc nc nc none none none e22 io84pdb1 nc nc rule 1 rule 1 none f1 nc nc nc none none none f2 io215pdb3 nc nc rule 1 rule 1 none f3 io215ndb3 nc nc rule 1 rule 1 none f4 io224ndb3 io173ndb3 io154vdb3 none none none f5 io225ndb3 io174ndb3 io155vdb3 none none none f6 vmv3 vmv3 io11rsb0 none rule 7 rule 7 f7 io11rsb0 io07rsb0 io07rsb0 none none none f8 gac0/io04rsb0 gac0/io04rsb0 gac0/io04rsb0 none none none f9 gac1/io05rsb0 gac1/io05rsb0 gac1/io05rsb0 none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-30 v1.1 f10 io25rsb0 io20rsb0 i o20rsb0 none none none f11 io36rsb0 io24rsb0 i o24rsb0 none none none f12 io42rsb0 io33rsb0 i o33rsb0 none none none f13 io49rsb0 io39rsb0 i o39rsb0 none none none f14 io56rsb0 io44rsb0 i o45rsb0 none none none f15 gbc0/io72rsb0 gbc0/io54rsb0 gbc0/io54rsb0 none none none f16 io62rsb0 io51rsb0 i o48rsb0 none none none f17 vmv0 vmv0 vmv0 none none none f18 io78ndb1 io61npb1 io61npb1 none none none f19 io81ndb1 io63pdb1 io63pdb1 none none none f20 io82ppb1 nc nc rule 1 rule 1 none f21 nc nc nc none none none f22 io84ndb1 nc nc rule 1 rule 1 none g1 io214ndb3 io170ndb3 nc none rule 1 rule 1 g2 io214pdb3 io170pdb3 nc none rule 1 rule 1 g3 nc nc nc none none none g4 io222ndb3 io171ndb3 io151vdb3 none none none g5 io222pdb3 io171pdb3 io151udb3 none none none g6 gac2/io223pdb3 gac2/io172pdb3 gac2/io153udb3 n one none none g7 io223ndb3 io06rsb0 io06rsb0 none none none g8 gndq gndq gndq none none none g9 io23rsb0 io10rsb0 io10rsb0 none none none g10 io29rsb0 io19rsb0 i o19rsb0 none none none g11 io33rsb0 io26rsb0 i o26rsb0 none none none g12 io46rsb0 io30rsb0 i o30rsb0 none none none g13 io52rsb0 io40rsb0 i o40rsb0 none none none g14 io60rsb0 io45rsb0 i o46rsb0 none none none g15 gndq gndq gndq none none none g16 io80ndb1 io50rsb0 io47rsb0 none none none g17 gbb2/io79pdb1 gbb2/io61ppb 1 gbb2/io61ppb1 n one none none g18 io79ndb1 io53rsb0 io53rsb0 none none none g19 io82npb1 io63ndb1 io63ndb1 none none none g20 io85pdb1 nc nc rule 1 rule 1 none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-31 g21 io85ndb1 nc nc rule 1 rule 1 none g22 nc nc nc none none none h1 nc nc nc none none none h2 nc nc nc none none none h3 v cc v cc v cc none none none h4 io217pdb3 io166pdb3 io150pdb3 none none none h5 io218pdb3 io167npb3 io08rsb0 none none none h6 io221ndb3 io172ndb3 io153vdb3 none none none h7 io221pdb3 io169ndb3 io152vdb3 none none none h8 vmv0 vmv0 vmv0 none none none h9 v cci b0 v cci b0 v cci b0 none none none h10 v cci b0 v cci b0 v cci b0 none none none h11 io38rsb0 io25rsb0 i o25rsb0 none none none h12 io47rsb0 io31rsb0 i o31rsb0 none none none h13 v cci b0 v cci b0 v cci b0 none none none h14 v cci b0 v cci b0 v cci b0 none none none h15 vmv1 vmv1 vmv1 none none none h16 gbc2/io80pdb1 gbc2/io62pdb1 gbc2/io62pdb1 none none none h17 io83ppb1 io67ppb1 i o65rsb1 none none none h18 io86ppb1 io64ppb1 i o52rsb0 none none none h19 io87pdb1 io66pdb1 io66pdb1 none none none h20 v cc v cc v cc none none none h21 nc nc nc none none none h22 nc nc nc none none none j1 io212ndb3 nc nc rule 1 rule 1 none j2 io212pdb3 nc nc rule 1 rule 1 none j3 nc nc nc none none none j4 io217ndb3 io166ndb3 io150ndb3 none none none j5 io218ndb3 io168npb3 io149npb3 none none none j6 io216pdb3 io167ppb3 io09rsb0 none none none j7 io216ndb3 io169pdb3 io152udb3 none none none j8 v cci b3 v cci b3 v cci b3 none none none j9 gnd gnd gnd none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-32 v1.1 j10 v cc v cc v cc none none none j11 v cc v cc v cc none none none j12 v cc v cc v cc none none none j13 v cc v cc v cc none none none j14 gnd gnd gnd none none none j15 v cci b1 v cci b1 v cci b1 none none none j16 io83npb1 io62ndb1 io62ndb1 none none none j17 io86npb1 io64npb1 i o49rsb0 none none none j18 io90ppb1 io65ppb1 i o64ppb1 none none none j19 io87ndb1 io66ndb1 io66ndb1 none none none j20 nc nc nc none none none j21 io89pdb1 io68pdb1 nc none rule 1 rule 1 j22 io89ndb1 io68ndb1 nc none rule 1 rule 1 k1 io211pdb3 io157pdb3 nc none rule 1 rule 1 k2 io211ndb3 io157ndb3 nc none rule 1 rule 1 k3 nc nc nc none none none k4 io210ppb3 io165ndb3 io148ndb3 none none none k5 io213ndb3 io165pdb3 io148pdb3 none none none k6 io213pdb3 io168ppb3 io149ppb3 none none none k7 gfc1/io209ppb3 gfc1/io164ppb 3 gfc1/io147ppb3 n one none none k8 v cci b3 v cci b3 v cci b3 none none none k9 v cc v cc v cc none none none k10 gnd gnd gnd none none none k11 gnd gnd gnd none none none k12 gnd gnd gnd none none none k13 gnd gnd gnd none none none k14 v cc v cc v cc none none none k15 v cci b1 v cci b1 v cci b1 none none none k16 gcc1/io91ppb1 gcc 1/io69ppb1 gcc 1/io67ppb1 non e none none k17 io90npb1 io65npb1 i o64npb1 none none none k18 io88pdb1 io75pdb1 io73pdb1 none none none k19 io88ndb1 io75ndb1 io73ndb1 none none none k20 io94npb1 nc nc rule 1 rule 1 none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-33 k21 io98ndb1 io76ndb1 nc none rule 1 rule 1 k22 io98pdb1 io76pdb1 nc none rule 1 rule 1 l1 nc nc nc none none none l2 io200pdb3 io155pdb3 nc none rule 1 rule 1 l3 io210npb3 nc nc rule 1 rule 1 none l4 gfb0/io208npb3 gfb0/io163npb 3 gfb0/io146npb3 none none none l5 gfa0/io207ndb3 gfa0/io162ndb 3 gfa0/io145ndb3 none none none l6 gfb1/io208ppb3 gfb1/io163ppb 3 gfb1/io146ppb3 n one none none l7 v complf v complf v complf none none none l8 gfc0/io209npb3 gfc0/io164npb 3 gfc0/io147npb3 none none none l9 v cc v cc v cc none none none l10 gnd gnd gnd none none none l11 gnd gnd gnd none none none l12 gnd gnd gnd none none none l13 gnd gnd gnd none none none l14 v cc v cc v cc none none none l15 gcc0/io91npb1 gcc0/io69npb1 gcc0/io67npb1 none none none l16 gcb1/io92ppb1 gcb 1/io70ppb1 gcb 1/io68ppb1 non e none none l17 gca0/io93npb1 gca0/io71npb 1 gca0/io69npb1 none none none l18 io96npb1 io67npb1 n c none rule 1 rule 1 l19 gcb0/io92npb1 gcb0/io70npb1 gcb0/io68npb1 none none none l20 io97pdb1 io77pdb1 nc none rule 1 rule 1 l21 io97ndb1 io77ndb1 nc none rule 1 rule 1 l22 io99npb1 io78npb1 n c none rule 1 rule 1 m1 nc nc nc none none none m2 io200ndb3 io155ndb3 nc none rule 1 rule 1 m3 io206ndb3 io158npb3 nc none rule 1 rule 1 m4 gfa2/io206pdb3 gfa2/io161ppb 3 gfa2/io144ppb3 none none none m5 gfa1/io207pdb3 gfa1/io162pdb3 gfa1/io145pdb3 none none none m6 v ccplf v ccplf v ccplf none none none m7 io205ndb3 io160ndb3 io143ndb3 none none none m8 gfb2/io205pdb3 gfb2/io160pdb 3 gfb2/io143pdb3 none none none m9 v cc v cc v cc none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-34 v1.1 m10 gnd gnd gnd none none none m11 gnd gnd gnd none none none m12 gnd gnd gnd none none none m13 gnd gnd gnd none none none m14 v cc v cc v cc none none none m15 gcb2/io95ppb1 gcb 2/io73ppb1 gcb 2/io71ppb1 non e none none m16 gca1/io93ppb1 gca1/io71ppb 1 gca1/io69ppb1 none none none m17 gcc2/io96ppb1 gcc 2/io74ppb1 gcc 2/io72ppb1 non e none none m18 io100ppb1 io80ppb1 n c none rule 1 rule 1 m19 gca2/io94ppb1 gca2/io72pdb 1 gca2/io70pdb1 none none none m20 io101ppb1 io79ppb1 n c none rule 1 rule 1 m21 io99ppb1 io78ppb1 n c none rule 1 rule 1 m22 nc nc nc none none none n1 io201ndb3 io154ndb3 nc none rule 1 rule 1 n2 io201pdb3 io154pdb3 nc none rule 1 rule 1 n3 nc nc nc none none none n4 gfc2/io204pdb3 gfc2/io159pdb 3 gfc2/io142pdb3 none none none n5 io204ndb3 io161npb3 io144npb3 none none none n6 io203ndb3 io156ppb3 io141ppb3 none none none n7 io203pdb3 io129rsb2 i o120rsb2 none none none n8 v cci b3 v cci b3 v cci b3 none none none n9 v cc v cc v cc none none none n10 gnd gnd gnd none none none n11 gnd gnd gnd none none none n12 gnd gnd gnd none none none n13 gnd gnd gnd none none none n14 v cc v cc v cc none none none n15 v cci b1 v cci b1 v cci b1 none none none n16 io95npb1 io73npb1 i o71npb1 none none none n17 io100npb1 io80npb1 io74rsb1 none none none n18 io102ndb1 io74npb1 io72npb1 none none none n19 io102pdb1 io72ndb1 io70ndb1 none none none n20 nc nc nc none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-35 n21 io101npb1 io79npb1 nc none rule 1 rule 1 n22 io103pdb1 nc nc rule 1 rule 1 none p1 nc nc nc none none none p2 io199pdb3 io153pdb3 nc none rule 1 rule 1 p3 io199ndb3 io153ndb3 nc none rule 1 rule 1 p4 io202ndb3 io159ndb3 io142ndb3 none none none p5 io202pdb3 io156npb3 io141npb3 none none none p6 io196ppb3 io151ppb3 io125rsb2 none none none p7 io193ppb3 io158ppb3 io139rsb3 none none none p8 v cci b3 v cci b3 v cci b3 none none none p9 gnd gnd gnd none none none p10 v cc v cc v cc none none none p11 v cc v cc v cc none none none p12 v cc v cc v cc none none none p13 v cc v cc v cc none none none p14 gnd gnd gnd none none none p15 v cci b1 v cci b1 v cci b1 none none none p16 gdb0/io112npb1 gdb0/io87npb 1 gdb0/io78vpb1 none none none p17 io106ndb1 io85ndb1 io76vdb1 none none none p18 io106pdb1 io85pdb1 io76udb1 none none none p19 io107pdb1 io84pdb1 io75pdb1 none none none p20 nc nc nc none none none p21 io104pdb1 io81pdb1 nc none rule 1 rule 1 p22 io103ndb1 nc nc rule 1 rule 1 none r1 nc nc nc none none none r2 io197ppb3 nc nc rule 1 rule 1 none r3 v cc v cc v cc none none none r4 io197npb3 io150pdb3 io140pdb3 none none none r5 io196npb3 io151npb3 io 130rsb2 none none none r6 io193npb3 io147npb3 io138npb3 none none none r7 gec0/io190npb3 gec0/io146np b3 gec0/io137npb3 none none none r8 vmv3 vmv3 vmv3 none none none r9 v cci b2 v cci b2 v cci b2 none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-36 v1.1 r10 v cci b2 v cci b2 v cci b2 none none none r11 io147rsb2 io117rsb2 i o108rsb2 none none none r12 io136rsb2 io110rsb2 i o101rsb2 none none none r13 v cci b2 v cci b2 v cci b2 none none none r14 v cci b2 v cci b2 v cci b2 none none none r15 vmv2 vmv2 vmv2 none none none r16 io110ndb1 io94rsb2 io83rsb2 none none none r17 gdb1/io112ppb1 gdb1/io87ppb 1 gdb1/io78upb1 n one none none r18 gdc1/io111pdb1 gdc1/io86pdb 1 gdc1/io77udb1 none none none r19 io107ndb1 io84ndb1 io75ndb1 none none none r20 v cc v cc v cc none none none r21 io104ndb1 io81ndb1 nc none rule 1 rule 1 r22 io105pdb1 io82pdb1 nc none rule 1 rule 1 t1 io198pdb3 io152pdb3 nc none rule 1 rule 1 t2 io198ndb3 io152ndb3 nc none rule 1 rule 1 t3 nc nc nc none none none t4 io194ppb3 io150ndb3 io140ndb3 none none none t5 io192ppb3 io147ppb3 io138ppb3 none none none t6 gec1/io190ppb3 gec1/io146ppb3 gec1/io137ppb3 none none none t7 io192npb3 io140rsb2 i o131rsb2 none none none t8 gndq gndq gndq none none none t9 gea2/io187rsb2 gea2/io143rsb 2 gea2/io134rsb2 none none none t10 io161rsb2 io126rsb2 i o117rsb2 none none none t11 io155rsb2 io120rsb2 i o111rsb2 none none none t12 io141rsb2 io108rsb2 i o99rsb2 none none none t13 io129rsb2 io103rsb2 i o94rsb2 none none none t14 io124rsb2 io99rsb2 i o87rsb2 none none none t15 gndq gndq gndq none none none t16 io110pdb1 io92rsb2 io93rsb2 none none none t17 v jtag v jtag v jtag none none none t18 gdc0/io111ndb1 gdc0/io86ndb1 gdc0/io77vdb1 none none none t19 gda1/io113pdb1 gda1/io88pdb1 gda1/io79udb1 none none none t20 nc nc nc none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-37 t21 io108pdb1 io83pdb1 nc none rule 1 rule 1 t22 io105ndb1 io82ndb1 nc none rule 1 rule 1 u1 io195pdb3 io149pdb3 nc none rule 1 rule 1 u2 io195ndb3 io149ndb3 nc none rule 1 rule 1 u3 io194npb3 nc nc rule 1 rule 1 none u4 geb1/io189pdb3 geb1/io145pd b3 geb1/io136pdb3 none none none u5 geb0/io189ndb3 geb0/io145ndb3 geb0/io136ndb3 none none none u6 vmv2 vmv2 vmv2 none none none u7 io179rsb2 io138rsb2 i o129rsb2 none none none u8 io171rsb2 io136rsb2 i o128rsb2 none none none u9 io165rsb2 io131rsb2 i o122rsb2 none none none u10 io159rsb2 io124rsb2 i o115rsb2 none none none u11 io151rsb2 io119rsb2 i o110rsb2 none none none u12 io137rsb2 io107rsb2 i o98rsb2 none none none u13 io134rsb2 io104rsb2 i o95rsb2 none none none u14 io128rsb2 io97rsb2 i o88rsb2 none none none u15 vmv1 vmv1 io84rsb2 none rule 7 rule 7 u16 tck tck tck none none none u17 v pump v pump v pump none none none u18 trst trst trst none none none u19 gda0/io113ndb1 gda0/io88ndb 1 gda0/io79vdb1 none none none u20 nc nc nc none none none u21 io108ndb1 io83ndb1 nc none rule 1 rule 1 u22 io109pdb1 nc nc rule 1 rule 1 none v1 nc nc nc none none none v2 nc nc nc none none none v3 gnd gnd gnd none none none v4 gea1/io188pdb3 gea1/io144pdb3 gea1/io135pdb3 none none none v5 gea0/io188ndb3 gea0/io144ndb 3 gea0/io135ndb3 none none none v6 io184rsb2 io139rsb2 i o127rsb2 none none none v7 gec2/io185rsb2 gec2/io141rsb 2 gec2/io132rsb2 none none none v8 io168rsb2 io132rsb2 i o123rsb2 none none none v9 io163rsb2 io127rsb2 i o118rsb2 none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-38 v1.1 v10 io157rsb2 io121rsb2 i o112rsb2 none none none v11 io149rsb2 io114rsb2 i o106rsb2 none none none v12 io143rsb2 io109rsb2 i o100rsb2 none none none v13 io138rsb2 io105rsb2 i o96rsb2 none none none v14 io131rsb2 io98rsb2 i o89rsb2 none none none v15 io125rsb2 io96rsb2 i o85rsb2 none none none v16 gdb2/io115rsb2 gdb2/io90rsb2 gdb2/io81rsb2 none none none v17 tdi tdi tdi none none none v18 gndq gndq nc none rule 8 rule 8 v19 tdo tdo tdo none none none v20 gnd gnd gnd none none none v21 nc nc nc none none none v22 io109ndb1 nc nc rule 1 rule 1 none w1 nc nc nc none none none w2 io191pdb3 io148pdb3 nc none rule 1 rule 1 w3 nc nc nc none none none w4 gnd gnd gnd none none none w5 io183rsb2 io137rsb2 i o126rsb2 none none none w6 geb2/io186rsb2 geb2/io142rsb 2 geb2/io133rsb2 none none none w7 io172rsb2 io134rsb2 i o124rsb2 none none none w8 io170rsb2 io125rsb2 i o116rsb2 none none none w9 io164rsb2 io123rsb2 i o113rsb2 none none none w10 io158rsb2 io118rsb2 i o107rsb2 none none none w11 io153rsb2 io115rsb2 i o105rsb2 none none none w12 io142rsb2 io111rsb2 i o102rsb2 none none none w13 io135rsb2 io106rsb2 i o97rsb2 none none none w14 io130rsb2 io102rsb2 i o92rsb2 none none none w15 gdc2/io116rsb2 gdc2/io91rsb2 gdc2/io82rsb2 none none none w16 io120rsb2 io93rsb2 i o86rsb2 none none none w17 gda2/io114rsb2 gda2/io89rsb 2 gda2/io80rsb2 none none none w18 tms tms tms none none none w19 gnd gnd gnd none none none w20 nc nc nc none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices v1.1 12-39 w21 nc nc nc none none none w22 nc nc nc none none none y1 v cci b3 v cci b3 v cci b3 none none none y2 io191ndb3 io148ndb3 nc none rule 1 rule 1 y3 nc nc nc none none none y4 io182rsb2 nc nc rule 1 rule 1 none y5 gnd gnd gnd none none none y6 io177rsb2 nc nc rule 1 rule 1 none y7 io174rsb2 nc nc rule 1 rule 1 none y8 v cc v cc v cc none none none y9 v cc v cc v cc none none none y10 io154rsb2 nc nc rule 1 rule 1 none y11 io148rsb2 nc nc rule 1 rule 1 none y12 io140rsb2 nc nc rule 1 rule 1 none y13 nc nc nc none none none y14 v cc v cc v cc none none none y15 v cc v cc v cc none none none y16 nc nc nc none none none y17 nc nc nc none none none y18 gnd gnd gnd none none none y19 nc nc nc none none none y20 nc nc nc none none none y21 nc nc nc none none none y22 v cci b1 v cci b1 v cci b1 none none none table 12-7 ? pin compatibility and migration tabl e for the fg484 package (continued) pin number a3p1000 function a3p600 function a3p400 function migration rule between a3p1000 and a3p600 migration rule between a3p1000 and a3p400 migration rule between a3p600 and a3p400 migrating designs in proasic3 devices fro m higher-density to mid-density devices 12-40 v1.1 conclusion this application note describes design migration among proasic3 family devices with an emphasis on package pin compatibility. the proasic3 family of devices shares numerous common architectural features. during a system migration, care should be taken re garding the architectural features of each core. ad ditionally, a key requirem ent is running functional simulation before and after the migration, using actel to ols. actel will be updating this application note with additional packages in the future. related documents handbook documents i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-017-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the part number for this document was changed from 51700094-016-0 to 51700094-017-1. n/a 51900143-1/10.07 in table 12-4 pin compatibility and migr ation table for the pq208 package , pin 107 was updated to include rule 8. 12-5 51900143-0/7.06 the title of the document and the "introduction" section were updated to clarify the topics covered in the application note. 12-1 the "design migration" section was updated to match and cross-reference the sections of the document in sequence. 12-1 the title of table 12-1 device information was updated. 12-1 table 12-3 migration rules from higher -density to mid-density devices and table 4 were combined and a table not e was added to refer to the datasheet for i/o naming conventions. 12-3 in the "power supply and board-lev el considerations" section , the following bullet was removed: "since each bank independen tly supports 1.5 v to 3.3 v , i/os must be connected to the v cci bx of their own banks." 12-4 the "related documents" section was added. 12-40 v1.0 13-1 application note ac313 13 ? migrating designs from a3p250 to lower- logic-density devices introduction the purpose of this document is to assist you in migrating desi gns from a high-d ensity proasic ? 3 device (a3p250) to lower-density devices (a3p1 25, a3p060, and a3p030). since one of the key factors is pin compatibility for a given package among the devices within the family, the primary focus of this document will be to address the pin compatibility issue. design migration proasic3 family devices are architecturally comp atible with each other. however, customers must pay attention to a few key areas when migrating a design. the specific issues discussed throughout this application note are as follows: ? "design and device evaluation" ? "device and package compatibility" on page 13-2 ? "migration and implementation methodologies" on page 13-2 ? "i/o banks and standards" on page 13-3 ? "power supply consider ations" on page 13-4 ? "pin migration and compatibility" on page 13-5 design and device evaluation when migrating a design, the primary task should be to compare the available resources between two devices. you need to evaluate effective gate count, ra m size, i/o banks, and the number of i/os. in addition, when portin g designs to new proasic3 deri vatives, timing analysis and simulations should al so be validated. table 13-1 gives a summary of de vice resources for the a3p250 device and its smaller migration targets. table 13-1 ? device information a3p250 a3p125 a3p060 a3p030 system gates 250 k 125 k 60 k 30 k tiles (d-flip-flops) 6,144 3,072 1,536 768 ram (kbits) 36 36 18 ? ram blocks (4,608 bits) 8 8 4 ? i/o banks (+ jtag) 4222 user i/os per package: vq100 68/13 71 71 77 qn132 87/19 84 80 81 tq144 100 91 fg144 97/24 97 96 pq208 151/34 133 fg256 157/38 note: user i/o is given as x (single-ended) or x/y (single-ended/double-ended). migrating designs from a3p250 to lower-logic-density devices 13-2 v1.0 device and package compatibility proasic3 devices and packaging we re designed to allow considerab le footprint compatibility for smoother migration. common and convertible i/os among a3p030, a3 p060, a3p125, and a3p250 table 13-2 shows the number of i/os that are common between any two of th e above four devices. in addition, the table indicate s the number of i/os that re quire the necessary conversion (convertible i/os) using suggeste d design migration rules in the "migration and implementation methodologies" section . migration and implementation methodologies table 13-3 on page 13-3 lists some possible migration combinations and the recommended implementation rules for compat ible design conversions from higher-density to lower-density devices. the "pin migration and compatibility" section on page 13-5 contains tables that list the required rules for different pin co mbinations. if "rule x" is ment ioned for a pin combination, that combination requires the implem entation methodology given in table 13-3 on page 13-3 . note that many combinations of high-density/low-density pins require none of these rules; the pins have complete type compatibility. these pins ar e marked in the pin tables with "none." table 13-2 ? common and convertible i/os package a3p250 a3p125 a3p250 a3p060 a3p250 a3p030 a3p125 a3p060 a3p125 a3p030 a3p060 a3p030 common i/os convertible i/os common i/os convertible i/os common i/os convertible i/os common i/os convertible i/os common i/os convertible i/os common i/os convertible i/os vq100 68 7 67 5 69 46 69 4 72 46 71 46 qn132 84 13 80 25 64 72 80 14 66 70 61 75 fg144 97 ? 96 ? n/a n/a 96 ? n/a n/a n/a n/a pq208 134 18 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a tq144 n/a n/a n/a n/a n/a n/a 90 19 n/a n/a n/a n/a migrating designs from a3p250 to lower-logic-density devices v1.0 13-3 i/o banks and standards proasic3 i/os are partitioned into multiple i/o voltage banks. the number of banks is device- dependent. there are four i/o banks in the a3 p250 device and two i/o banks in the a3p030, a3p060, and a3p125 devices. package pins routed to banks 0 an d 1 in the a3p250 device are routed to bank 0 in the a3p030, a3p060, and a3p125 devices, and banks 2 and 3 in th e a3p250 device are routed to bank 1 in the a3p030, a3p060, and a3p125 devices. the banks have dedicated supplies ; therefore, only i/os with co mpatible voltage standards can be assigned to the same i/o voltage bank. note that the a3p250 device su pports double-ended i/os; however, the a3p030, a3p060, and a3p125 devices do not supp ort double-ended i/os. table 13-3 ? migration rules from higher-density device to lower-density device migration rule issue implementation methodology higher density lower density 1 i/o or global i/o nc leave this pin floati ng or program the i/o as unused (software cannot program nc to usable i/o). nc i/o or global i/o 2 i/o global i/o instantiate the global i/o as an i/o buffer (works as a single- ended i/o). 3 global i/o i/o use the pdc constraint to promote the single-ended i/o to a global pin. there will be some additional delay. 4v cc or v cci nc the pin can remain connected to the board's v cc , v cci , vmv, v complf , or gndq plane, as applicable. gndq nc vmv nc v complf nc 5v cci b(x) 1 v cci b(y) 2 make sure the two bank voltage levels are same. tie the pin to the board's corresponding v cci /vmv plane. vmv(x) 1 vmv(y) 2 6 vmv0 i/o or global i/o leave the pin connected to the board's v cc , v cci , vmv, v complf , or gndq plane, as applicable. instantiate the i/o as a tristate buffer with oe = 0 and no weak pull-ups/-downs. gndq i/o gndq global i/o i/o v cc v cc i/o v complf i/o v ccplf i/o notes: 1. "x" is a bank number desi gnator and can be 0?3 for pr oasic3 and 0?7 for proasic3e. 2. "y" is a bank number design ator and can be 0?3 for proasic3 and 0?7 for proasic3e. migrating designs from a3p250 to lower-logic-density devices 13-4 v1.0 power supply considerations i/o power supply requirements are very importan t for design migration. since the migration is within the proasic3 family, there is no issue with respect to the core voltage v cc . pins that must be appropriately connected are v cci bx (bank supply voltage to i/o output buffer and i/o logic), vmvx (quiet i/o supply voltage), gndq (quiet gnd), and gnd. gndq and vmvx are important to decouple simultaneous switching noise (sso) for i/os?enhancing signal integrity and improving noise immunity. the key rules of migration for the ab ove-mentioned pins are as follows: ?vmv and v cci values of the higher-densi ty device in a given bank must correspond to the same vmv and v cci values in the smaller device's migrating bank. ? since banks 0 and 1 are connected to bank 0 in the smaller device?and banks 2 and 3 are connected to bank 1 in the smaller device?this im plies that banks 0 and 1 in the a3p250 device must have identical vmv and identical v cci . similarly, the vmv and v cci voltages in banks 2 and 3 of the a3p250 device must be identical. ?v cci bx pins in unused banks and vmv pins in unused banks must be connected to gnd. ? unused i/os should be left alon e, since the software automatically configur es them as inputs with pull-ups. any inappropriate connection during the migration may affect overall dynamic or inrush power consumption and might even result in device malfunction. additionally, the i/o naming convention in proasic3 devices has significant embedded information (e.g., pin location, bank number, signal type, polarity, and clock conditioning). for a detailed explanation, refer to the "user i/ o naming convention" section of i/o structures in igloo and proasic3 devices . for additional information on power i ssues, refer to the relevant datasheet. migrating designs from a3p250 to lower-logic-density devices v1.0 13-5 pin migration and compatibility vq100 package table 13-4 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with vq100 packaging pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 migration rule between a3p060 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p250 and a3p030 1 gnd gnd gnd gnd none none none none none none 2 io03rsb1 gaa2/ io51rsb1 gaa2/ io67rsb1 gaa2/ io118udb3 none none none rule 3 rule 3 rule 3 3 io02rsb1 io52rsb1 io68rsb1 io118 vdb3 none none none none none none 4 io01rsb1 gab2/ io53rsb1 gab2/ io69rsb1 gab2/ io117udb3 none none none rule 3 rule 3 rule 3 5 io00rsb1 io95rsb1 io132rsb1 io117 vdb3 none none none none none none 6 io82rsb1 gac2/ io94rsb1 gac2/ io131rsb1 gac2/ io116udb3 none none none rule 3 rule 3 rule 3 7 io81rsb1 io93rsb1 io130rsb1 io116 vdb3 none none none none none none 8 io80rsb1 io92rsb1 io129rsb1 io11 2psb3 none none none none none none 9 gnd gnd gnd gnd none none none none none none 10 io79rsb1 gfb1/ io87rsb1 gfb1/ io124rsb1 gfb1/ io109pdb3 none none none rule 3 rule 3 rule 3 11 io78rsb1 gfb0/ io86rsb1 gfb0/ io123rsb1 gfb0/ io109ndb3 none none none rule 3 rule 3 rule 3 12 gec0/ io77rsb1 v complf v complf v complf none none none rule 6 rule 6 rule 6 13 gea0/ io76rsb1 gfa0/ io85rsb1 gfa0/ io122rsb1 gfa0/ io108npb3 none none none none none none 14 geb0/ io75rsb1 v ccplf v ccplf v ccplf none none none rule 6 rule 6 rule 6 15 io74rsb1 gfa1/ io84rsb1 gfa1/ io121rsb1 gfa1/ io108ppb3 none none none rule 3 rule 3 rule 3 16 io73rsb1 gfa2/ io83rsb1 gfa2/ io120rsb1 gfa2/ io107psb3 none none none rule 3 rule 3 rule 3 17 v cc v cc v cc v cc none none none none none none 18 v cci b1 v cci b1 v cci b1 v cci b3 none none none none none none 19 io72rsb1 gec1/ io77rsb1 gec0/ io111rsb1 gfc2/ io105psb3 none none none rule 3 rule 3 rule 3 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-6 v1.0 20 io71rsb1 geb1/ io75rsb1 geb1/ io110rsb1 gec1/ io100pdb3 none none none rule 3 rule 3 rule 3 21 io70rsb1 geb0/ io74rsb1 geb0/ io109rsb1 gec0/ io100ndb3 none none none rule 3 rule 3 rule 3 22 io69rsb1 gea1/ io73rsb1 gea1/ io108rsb1 gea1/ io98pdb3 none none none rule 3 rule 3 rule 3 23 io68rsb1 gea0/ io72rsb1 gea0/ io107rsb1 gea0/ io98ndb3 none none none rule 3 rule 3 rule 3 24 io67rsb1 vmv1 vmv1 vmv3 none no ne none rule 6 rule 6 rule 6 25 io66rsb1 gndq gndq gndq none none none rule 6 rule 6 rule 6 26 io65rsb1 gea2/ io71rsb1 gea2/ io106rsb1 gea2/ io97rsb2 none none none rule 3 rule 3 rule 3 27 io64rsb1 geb2/ io70rsb1 geb2/ io105rsb1 geb2/ io96rsb2 none none none rule 3 rule 3 rule 3 28 io63rsb1 gec2/ io69rsb1 gec2/ io104rsb1 gec2/ io95rsb2 none none none rule 3 rule 3 rule 3 29 io62rsb1 io68rsb1 io102rsb1 io93r sb2 none none none none none none 30 io61rsb1 io67rsb1 io100rsb1 io92r sb2 none none none none none none 31 io60rsb1 io66rsb1 io99rsb1 io91rsb2 none none none none none none 32 io59rsb1 io65rsb1 io97rsb1 io90rsb2 none none none none none none 33 io58rsb1 io64rsb1 io96rsb1 io88rsb2 none none none none none none 34 io57rsb1 io63rsb1 io95rsb1 io86rsb2 none none none none none none 35 io56rsb1 io62rsb1 io94rsb1 io85rsb2 none none none none none none 36 io55rsb1 io61rsb1 io93rsb1 io84rsb2 none none none none none none 37 v cc v cc v cc v cc none none none none none none 38 gnd gnd gnd gnd none none none none none none 39 v cci b1 v cci b1 v cci b1 v cci b2 none none none none none none 40 io53rsb1 io60rsb1 io87rsb1 io77rsb2 none none none none none none 41 io51rsb1 io59rsb1 io84rsb1 io74rsb2 none none none none none none 42 io50rsb1 io58rsb1 io81rsb1 io71rsb2 none none none none none none 43 io49rsb1 io57rsb1 io75rsb1 gdc2/ io63rsb2 none rule 2 rule 3 none none rule 3 table 13-4 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with vq100 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 migration rule between a3p060 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p250 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-7 44 io48rsb1 gdc2/ io56rsb1 gdc2/ io72rsb1 gdb2/ io62rsb2 none none none rule 3 rule 3 rule 3 45 io47rsb1 gdb2/ io55rsb1 gdb2/ io71rsb1 gda2/ io61rsb2 none none none rule 3 rule 3 rule 3 46 io46rsb1 gda2/ io54rsb1 gda2/ io70rsb1 gndq none rule 10 rule 10 rule 3 rule 3 rule 6 47 tck tck tck tck none none none none none none 48 tdi tdi tdi tdi none none none none none none 49 tms tms tms tms none no ne none none none none 50 nc vmv1 vmv1 vmv2 none none none rule 4 rule 4 rule 4 51 gnd gnd gnd gnd none none none none none none 52 v pump v pump v pump v pump none none none none none none 53 nc nc nc nc none none none none none none 54 tdo tdo tdo tdo none none none none none none 55 trst trst trst trst none none none none none none 56 v jtag v jtag v jtag v jtag none none none none none none 57 io45rsb0 gda1/ io49rsb0 gda1/ io65rsb0 gda1/ io60usb1 none none none rule 3 rule 3 rule 3 58 io44rsb0 gdc0/ io46rsb0 gdc0/ io62rsb0 gdc0/ io58vdb1 none none none rule 3 rule 3 rule 3 59 io43rsb0 gdc1/ io45rsb0 gdc1/ io61rsb0 gdc1/ io58udb1 none none none rule 3 rule 3 rule 3 60 io42rsb0 gcc2/ io43rsb0 gcc2/ io59rsb0 io52ndb1 none rule 2 rule 2 rule 3 rule 3 none 61 io41rsb0 gcb2/ io42rsb0 gcb2/ io58rsb0 gcb2/ io52pdb1 none none none rule 3 rule 3 rule 3 62 io40rsb0 gca0/ io40rsb0 gca0/ io56rsb0 gca1/ io50pdb1 none none none rule 3 rule 3 rule 3 63 gdb0/ io38rsb0 gca1/ io39rsb0 gca1/ io55rsb0 gca0/ io50ndb1 none none none none none none 64 gda0/ io37rsb0 gcc0/ io36rsb0 gcc0/ io52rsb0 gcc0/ io48ndb1 none none none none none none 65 gdc0/ io36rsb0 gcc1/ io35rsb0 gcc1/ io51rsb0 gcc1/ io48pdb1 none none none none none none table 13-4 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with vq100 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 migration rule between a3p060 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p250 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-8 v1.0 66 v cci b0 v cci b0 v cci b0 v cci b1 none none none none none none 67 gnd gnd gnd gnd none none none none none none 68 v cc v cc v cc v cc none none none none none none 69 io35rsb0 io31rsb0 io47rsb0 io43ndb1 none none none none none none 70 io34rsb0 gbc2/ io29rsb0 gbc2/ io45rsb0 gbc2/ io43pdb1 none none none rule 3 rule 3 rule 3 71 io33rsb0 gbb2/ io27rsb0 gbb2/ io43rsb0 gbb2/ io42psb1 none none none rule 3 rule 3 rule 3 72 io32rsb0 io26rsb0 io42rsb0 io41ndb1 none none none none none none 73 io31rsb0 gba2/ io25rsb0 gba2/ io41rsb0 gba2/ io41pdb1 none none none rule 3 rule 3 rule 3 74 io30rsb0 vmv0 vmv0 vmv1 none no ne none rule 6 rule 6 rule 6 75 io29rsb0 gndq gndq gndq none none none rule 6 rule 6 rule 6 76 io28rsb0 gba1/ io24rsb0 gba1/ io40rsb0 gba1/ io40rsb0 none none none rule 3 rule 3 rule 3 77 io27rsb0 gba0/ io23rsb0 gba0/ io39rsb0 gba0/ io39rsb0 none none none rule 3 rule 3 rule 3 78 io26rsb0 gbb1/ io22rsb0 gbb1/ io38rsb0 gbb1/ io38rsb0 none none none rule 3 rule 3 rule 3 79 io25rsb0 gbb0/ io21rsb0 gbb0/ io37rsb0 gbb0/ io37rsb0 none none none rule 3 rule 3 rule 3 80 io24rsb0 gbc1/ io20rsb0 gbc1/ io36rsb0 gbc1/ io36rsb0 none none none rule 3 rule 3 rule 3 81 io23rsb0 gbc0/ io19rsb0 gbc0/ io35rsb0 gbc0/ io35rsb0 none none none rule 3 rule 3 rule 3 82 io22rsb0 io18rsb0 io32rsb0 io29rsb0 none none none none none none 83 io21rsb0 io17rsb0 io28rsb0 io27rsb0 none none none none none none 84 io20rsb0 io15rsb0 io25rsb0 io25rsb0 none none none none none none 85 io19rsb0 io13rsb0 io22rsb0 io23rsb0 none none none none none none 86 io18rsb0 io11rsb0 io19rsb0 io21rsb0 none none none none none none 87 v cci b0 v cci b0 v cci b0 v cci b0 none none none none none none 88 gnd gnd gnd gnd none none none none none none 89 v cc v cc v cc v cc none none none none none none table 13-4 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with vq100 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 migration rule between a3p060 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p250 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-9 90 io16rsb0 io10rsb0 io15rsb0 io15rsb0 none none none none none none 91 io14rsb0 io09rsb0 io13rsb0 io13rsb0 none none none none none none 92 io12rsb0 io08rsb0 io11rsb0 io11rsb0 none none none none none none 93 io11rsb0 gac1/ io07rsb0 io09rsb0 gac1/ io05rsb0 rule 2nonerule 3rule 3nonerule 3 94 io10rsb0 gac0/ io06rsb0 io07rsb0 gac0/ io04rsb0 rule 2nonerule 3rule 3nonerule 3 95 io09rsb0 gab1/ io05rsb0 gac1/ io05rsb0 gab1/ io03rsb0 none none none rule 3 rule 3 rule 3 96 io08rsb0 gab0/ io04rsb0 gac0/ io04rsb0 gab0/ io02rsb0 none none none rule 3 rule 3 rule 3 97 io07rsb0 gaa1/ io03rsb0 gab1/ io03rsb0 gaa1/ io01rsb0 none none none rule 3 rule 3 rule 3 98 io06rsb0 gaa0/ io02rsb0 gab0/ io02rsb0 gaa0/ io00rsb0 none none none rule 3 rule 3 rule 3 99 io05rsb0 io01rsb0 gaa1/ io01rsb0 gndq rule 3 rule 9 rule 10 none rule 3 rule 6 100 io04rsb0 io00rsb0 gaa0/ io00rsb0 vmv0 rule 3 rule 8 rule 8 none rule 3 rule 6 table 13-4 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with vq100 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 migration rule between a3p060 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p250 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-10 v1.0 qfn132 package table 13-5 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with qfn132 packaging pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p250 and a3p125 migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p060 and a3p030 a1 io01rsb1 gab2/ io00rsb1 gab2/ io69rsb1 gab2/ io117upb3 none none none rule 3 rule 3 rule 3 a2 io81rsb1 io93rsb1 io130rsb1 io117vpb3 none none none none none none a3 nc v cci b1 v cci b1 v cci b3 rule 5 none rule 5 rule 4 rule 4 rule 4 a4 io80rsb1 gfc1/ io89rsb1 gfc1/ io126rsb1 gfc1/ io110pdb3 none none none rule 3 rule 3 rule 3 a5 gec0/ io77rsb1 gfb0/ io86rsb1 gfb0/ io123rsb1 gfb0/ io109npb3 none none none none none none a6 nc v ccplf v ccplf v ccplf none none none rule 4 rule 4 rule 4 a7 geb0/ io75rsb1 gfa1/ io84rsb1 gfa1/ io121rsb1 gfa1/ io108ppb3 none none none none none none a8 io73rsb1 gfc2/ io81rsb1 gfc2/ io118rsb1 gfc2/ io105ppb3 none none none rule 3 rule 3 rule 3 a9 nc io78rsb1 io115rsb1 io103ndb3 n one none none rule 1 rule 1 rule 1 a10 v cc v cc v cc v cc none none none none none none a11 io71rsb1 geb1/ io75rsb1 geb1/ io110rsb1 gea1/ io98ppb3 none none none rule 3 rule 3 rule 3 a12 io68rsb1 gea0/ io72rsb1 gea0/ io107rsb1 gea0/ io98npb3 none none none rule 3 rule 3 rule 3 a13 io63rsb1 gec2/ io69rsb1 gec2/ io104rsb1 gec2/ io95rsb2 none none none rule 3 rule 3 rule 3 a14 io60rsb1 io65rsb1 io100rsb1 io91rsb2 none none none none none none a15 nc v cc v cc v cc none none none none none none a16 io59rsb1 io64rsb1 io99rsb1 io90rsb2 none none none none none none a17 io57rsb1 io63rsb1 io96rsb1 io87rsb2 none none none none none none a18 v cc io62rsb1 io94rsb1 io85rsb2 none n one none rule 6 rule 6 rule 6 a19 io54rsb1 io61rsb1 io91rsb1 io82rsb2 none none none none none none a20 io52rsb1 io58rsb1 io85rsb1 io76rsb2 none none none none none none a21 io49rsb1 gdb2/ io55rsb1 io79rsb1 io70rsb2 none rule 2 rule 2 none none rule 3 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. d pins are corner pins pe r the package specification. 3. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-11 a22 io48rsb1 nc v cc v cc none rule 4rule 4rule 6rule 6rule 1 a23 io47rsb1 gda2/ io54rsb1 gdb2/ io71rsb1 gdb2/ io62rsb2 none none none rule 3 rule 3 rule 3 a24 tdi tdi tdi tdi none none none none none none a25 trst trst trst trst none none none none none none a26 io44rsb0 gdc1/ io48rsb0 gdc1/ io61rsb0 gdc1/ io58udb1 none none none rule 3 rule 3 rule 3 a27 nc v cc v cc v cc none none none rule 4 rule 4 rule 4 a28 io43rsb0 io47rsb0 io60rsb0 io54ndb1 none none none none none none a29 io42rsb0 gcc2/ io46rsb0 gcc2/ io59rsb0 io52ndb1 none none rule 2 none rule 3 rule 3 a30 io40rsb0 gca2/ io44rsb0 gca2/ io57rsb0 gca2/ io51ppb1 none none none rule 3 rule 3 rule 3 a31 io39rsb0 gca0/ io43rsb0 gca0/ io56rsb0 gca0/ io50npb1 none none none rule 3 rule 3 rule 3 a32 gdc0/ io36rsb0 gcb1/ io40rsb0 gcb1/ io53rsb0 gcb1/ io49pdb1 none none none none none none a33 nc io36rsb0 io49rsb0 io47nsb1 n one none none rule 1 rule 1 rule 1 a34 v cc v cc v cc v cc none none none none none none a35 io34rsb0 io31rsb0 io44rsb0 io41npb1 none none none none none none a36 io31rsb0 gba2/ io28rsb0 gba2/ io41rsb0 gba2/ io41ppb1 none none none rule 3 rule 3 rule 3 a37 io26rsb0 gbb1/ io25rsb0 gbb1/ io38rsb0 gbb1/ io38rsb0 none none none rule 3 rule 3 rule 3 a38 io23rsb0 gbc0/ io22rsb0 gbc0/ io35rsb0 gbc0/ io35rsb0 none none none rule 3 rule 3 rule 3 a39 nc v cci b0 v cci b0 v cci b0 none none none rule 4 rule 4 rule 4 a40 io22rsb0 io21rsb0 io28rsb0 io28rsb0 none none none none none none a41 io20rsb0 io18rsb0 io22rsb0 io22rsb0 none none none none none none a42 io18rsb0 io15rsb0 io18rsb0 io18rsb0 none none none none none none a43 v cc io14rsb0 io14rsb0 io14rsb0 none n one none rule 6 rule 6 rule 6 a44 io15rsb0 io11rsb0 io11rsb0 io11rsb0 none none none none none none table 13-5 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with qfn132 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p250 and a3p125 migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p060 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. d pins are corner pins pe r the package specification. 3. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-12 v1.0 a45 io12rsb0 gab1/ io08rsb0 io07rsb0 io07rsb0 none rule 2 rule 2 none none rule 3 a46 io10rsb0 nc v cc v cc none rule 4rule 4rule 6rule 6rule 1 a47 io09rsb0 gab0/ io07rsb0 gac1/ io05rsb0 gac1/ io05rsb0 none none none rule 3 rule 3 rule 3 a48 io06rsb0 i o04rsb0 gab0/ io02rsb0 gab0/ io02rsb0 none rule 3 rule 3 rule 3 rule 3 none b1 io02rsb1 io01rsb1 io68rsb1 io118vdb3 none none none none none none b2 io82rsb1 gac2/ io94rsb1 gac2/ io131rsb1 gac2/ io116udb3 none none none rule 3 rule 3 rule 3 b3 gnd gnd gnd gnd none none none none none none b4 io79rsb1 gfc0/ io88rsb1 gfc0/ io125rsb1 gfc0/ io110ndb3 none none none rule 3 rule 3 rule 3 b5 nc v complf v complf v complf none none none rule 4 rule 4 rule 4 b6 gnd gnd gnd gnd none none none none none none b7 io74rsb1 gfb2/ io82rsb1 gfb2/ io119rsb1 gfb2/ io106psb3 none none none rule 3 rule 3 rule 3 b8 nc io79rsb1 io116rsb1 io103pdb3 none none none rule 1 rule 1 rule 1 b9 gnd gnd gnd gnd none none none none none none b10 io70rsb1 geb0/ io74rsb1 geb0/ io109rsb1 geb0/ io99ndb3 none none none rule 3 rule 3 rule 3 b11 io67rsb1 vmv1 vmv1 vmv3 rule 6 n one rule 5rule 6rule 6rule 6 b12 io64rsb1 geb2/ io70rsb1 geb2/ io105rsb1 geb2/ io96rsb2 none none none rule 3 rule 3 rule 3 b13 io61rsb1 io67rsb1 io101rsb1 io92rsb2 none none none none none none b14 gnd gnd gnd gnd none none none none none none b15 io58rsb1 nc io98rsb1 io89rsb2 n one rule 1 rule 1 none none rule 1 b16 io56rsb1 nc io95rsb1 io86rsb2 n one rule 1 rule 1 none none rule 1 b17 gnd gnd gnd gnd none none none none none none b18 io53rsb1 io59rsb1 io87rsb1 io78rsb2 none none none none none none b19 io50rsb1 gdc2/ io56rsb1 io81rsb1 io72rsb2 none rule 2 rule 2 none none rule 3 table 13-5 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with qfn132 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p250 and a3p125 migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p060 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. d pins are corner pins pe r the package specification. 3. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-13 b20 gnd gnd gnd gnd none none none none none none b21 io46rsb1 gndq gndq gndq none no ne none rule 6 rule 6 rule 8 b22 tms tms tms tms none none none none none none b23 tdo tdo tdo tdo none none none none none none b24 io45rsb0 gdc0/ io49rsb0 gdc0/ io62rsb0 gdc0/ io58vdb1 none none none rule 3 rule 3 rule 3 b25 gnd gnd gnd gnd none none none none none none b26 nc nc nc io54pdb1 rule 1 none rule 1 rule 1 none none b27 io41rsb0 gcb2/ io45rsb0 gcb2/ io58rsb0 gcb2/ io52pdb1 none none none rule 3 rule 3 rule 3 b28 gnd gnd gnd gnd none none none none none none b29 gda0/ io37rsb0 gcb0/ io41rsb0 gcb0/ io54rsb0 gcb0/ io49ndb1 none none none none none none b30 nc gcc1/ io38rsb0 gcc1/ io51rsb0 gcc1/ io48pdb1 none none none rule 1 rule 1 rule 1 b31 gnd gnd gnd gnd none none none none none none b32 io33rsb0 gbb2/ io30rsb0 gbb2/ io43rsb0 gbb2/ io42pdb1 none none none rule 3 rule 3 rule 3 b33 io30rsb0 vmv0 vmv0 vmv1 rule 5 n one rule 5rule 6rule 6rule 7 b34 io27rsb0 gba0/ io26rsb0 gba0/ io39rsb0 gba0/ io39rsb0 none none none rule 3 rule 3 rule 3 b35 io24rsb0 gbc1/ io23rsb0 gbc1/ io36rsb0 gbc1/ io36rsb0 none none none rule 3 rule 3 rule 3 b36 gnd gnd gnd gnd none none none none none none b37 io21rsb0 io20rsb0 io26rsb0 io26rsb0 none none none none none none b38 io19rsb0 io17rsb0 io21rsb0 io21rsb0 none none none none none none b39 gnd gnd gnd gnd none none none none none none b40 io16rsb0 io12rsb0 io13rsb0 io13rsb0 none none none none none none b41 io13rsb0 gac0/ io09rsb0 io08rsb0 io08rsb0 none rule 2 rule 2 none none rule 3 b42 gnd gnd gnd gnd none none none none none none table 13-5 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with qfn132 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p250 and a3p125 migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p060 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. d pins are corner pins pe r the package specification. 3. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-14 v1.0 b43 io08rsb0 gaa1/ io06rsb0 gac0/ io04rsb0 gac0/ io04rsb0 none none none rule 3 rule 3 rule 3 b44 io05rsb0 gndq gndq gndq none no ne none rule 6 rule 6 rule 6 c1 io03rsb1 gaa2/ io02rsb1 gaa2/ io67rsb1 gaa2/ io118udb3 none none none rule 3 rule 3 rule 3 c2 io00rsb1 io95rsb1 io132rsb1 io116vdb3 none none none none none none c3 nc v cc v cc v cc none none none rule 4 rule 4 rule 4 c4 io78rsb1 gfb1/ io87rsb1 gfb1/ io124rsb1 gfb1/ io109ppb3 none none none rule 3 rule 3 rule 3 c5 gea0/ io76rsb1 gfa0/ io85rsb1 gfa0/ io122rsb1 gfa0/ io108npb3 none none none none none none c6 nc gfa2/ io83rsb1 gfa2/ io120rsb1 gfa2/ io107psb3 none none none rule 1 rule 1 rule 1 c7 nc io80rsb1 io117rsb1 io105npb3 none none none rule 1 rule 1 rule 1 c8 v cci b1 v cci b1 v cci b1 v cci b3 rule 5 none rule 5 rule 5 rule 5 rule 5 c9 io69rsb1 gea1/ io73rsb1 gea1/ io108rsb1 geb1/ io99pdb3 none none none rule 3 rule 3 rule 3 c10 io66rsb1 gndq gndq gndq none no ne none rule 6 rule 6 rule 6 c11 io65rsb1 gea2/ io71rsb1 gea2/ io106rsb1 gea2/ io97rsb2 none none none rule 3 rule 3 rule 3 c12 io62rsb1 io68rsb1 io103rsb1 io94rsb2 none none none none none none c13 nc v cci b1 v cci b1 v cci b2 rule 5 none rule 5 rule 4 rule 4 rule 4 c14 nc nc io97rsb1 io88rsb2 none r ule 1rule 1rule 1rule 1 none c15 io55rsb1 nc io93rsb1 io84rsb2 n one rule 1 rule 1 none none rule 1 c16 v cci b1 io60rsb1 io89rsb1 io80rsb2 non e none none rule 6 rule 6 rule 6 c17 io51rsb1 io57rsb1 io83rsb1 io74rsb2 none none none none none none c18 nc nc v cci b1 v cci b2 rule 5rule 4rule 4rule 4rule 4rule 4 c19 tck tck tck tck none none none none none none c20 nc vmv1 vmv1 vmv2 none none none rule 4 rule 4 rule 4 c21 v pump v pump v pump v pump none none none none none none c22 v jtag v jtag v jtag v jtag none none none none none none table 13-5 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with qfn132 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p250 and a3p125 migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p060 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. d pins are corner pins pe r the package specification. 3. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-15 c23 nc v cci b0 v cci b0 v cci b1 rule 5 none rule 5 rule 4 rule 4 rule 4 c24 nc nc nc io53nsb1 rule 1 none rule 1 rule 1 none none c25 nc nc nc io51npb1 rule 1 none rule 1 rule 1 none none c26 gdb0/ io38rsb0 gca1/ io42rsb0 gca1/ io55rsb0 gca1/ io50ppb1 none none none none none none c27 nc gcc0/ io39rsb0 gcc0/ io52rsb0 gcc0/ io48ndb1 none none none rule 1 rule 1 rule 1 c28 v cci b0 v cci b0 v cci b0 v cci b1 rule 5 none rule 5 rule 5 rule 5 none c29 io32rsb0 io29rsb0 io42rsb0 io42ndb1 none none none none none none c30 io29rsb0 gndq gndq gndq none no ne none rule 6 rule 6 rule 6 c31 io28rsb0 gba1/ io27rsb0 gba1/ io40rsb0 gba1/ io40rsb0 none none none rule 3 rule 3 rule 3 c32 io25rsb0 gbb0/ io24rsb0 gbb0/ io37rsb0 gbb0/ io37rsb0 none none none rule 3 rule 3 rule 3 c33 nc v cc v cc v cc none none none rule 4 rule 4 rule 4 c34 nc io19rsb0 io24rsb0 io24rsb0 n one none none rule 3 rule 3 rule 3 c35 v cci b0 io16rsb0 io19rsb0 io19rsb0 non e none none rule 1 rule 1 rule 1 c36 io17rsb0 io13rsb0 io16rsb0 io16rsb0 none none none none none none c37 io14rsb0 gac1/ io10rsb0 io10rsb0 io10rsb0 none rule 2 rule 2 none none rule 3 c38 io11rsb0 nc v cci b0 v cci b0 rule 5rule 4rule 4rule 6rule 6rule 1 c39 io07rsb0 gaa0/ io05rsb0 gab1/ io03rsb0 gab1/ io03rsb0 none none none rule 3 rule 3 rule 3 c40 io04rsb0 vmv0 vmv0 vmv0 none none none rule 6 rule 6 rule 6 d1 gnd gnd gnd gnd none none none none none none d2 gnd gnd gnd gnd none none none none none none d3 gnd gnd gnd gnd none none none none none none d4 gnd gnd gnd gnd none none none none none none table 13-5 ? pin compatibility and migration table for a 3p030, a3p060, a3p125, and a3p250 with qfn132 packaging (continued) pin no. a3p030 function a3p060 function a3p125 function a3p250 function migration rule between a3p250 and a3p125 migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p030 migration rule between a3p125 and a3p030 migration rule between a3p060 and a3p030 notes: 1. see table 13-3 on page 13-3 for the high-density /low-density pin comb ination guidelines. 2. d pins are corner pins pe r the package specification. 3. "none" implies that the pins ca n be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-16 v1.0 tq144 package table 13-6 ? pin compatibility and migration table fo r proasic3 a3p060 and a3p125 with tq144 packaging pin number a3p060 function a3p125 function migration rule between a3p125 and a3p060 1 gaa2/io51rsb1 gaa2/io67rsb1 none 2 io52rsb1 io68rsb1 none 3 gab2/io53rsb1 gab2/io69rsb1 none 4 io95rsb1 io132rsb1 none 5 gac2/io94rsb1 gac2/io131rsb1 none 6 io93rsb1 io130rsb1 none 7 io92rsb1 io129rsb1 none 8 io91rsb1 io128rsb1 none 9v cc v cc none 10 gnd gnd none 11 v cci b1 v cci b1 none 12 io90rsb1 io127rsb1 none 13 gfc1/io89rsb1 gfc1/io126rsb1 none 14 gfc0/io88rsb1 gfc0/io125rsb1 none 15 gfb1/io87rsb1 gfb1/io124rsb1 none 16 gfb0/io86rsb1 gfb0/io123rsb1 none 17 v complf v complf none 18 gfa0/io85rsb1 gfa0/io122rsb1 none 19 v ccplf v ccplf none 20 gfa1/io84rsb1 gfa1/io121rsb1 none 21 gfa2/io83rsb1 gfa2/io120rsb1 none 22 gfb2/io82rsb1 gfb2/io119rsb1 none 23 gfc2/io81rsb1 gfc2/io118rsb1 none 24 io80rsb1 io117rsb1 none 25 io79rsb1 io116rsb1 none 26 io78rsb1 io115rsb1 none 27 gnd gnd none 28 v cci b1 v cci b1 none 29 gec1/io77rsb1 gec1/io112rsb1 none 30 gec0/io76rsb1 gec0/io111rsb1 none 31 geb1/io75rsb1 geb1/io110rsb1 none 32 geb0/io74rsb1 geb0/io109rsb1 none 33 gea1/io73rsb1 gea1/io108rsb1 none 34 gea0/io72rsb1 gea0/io107rsb1 none 35 vmv1 vmv1 none notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-17 36 gndq gndq none 37 nc nc none 38 gea2/io71rsb1 gea2/io106rsb1 none 39 geb2/io70rsb1 geb2/io105rsb1 none 40 gec2/io69rsb1 gec2/io104rsb1 none 41 io68rsb1 io103rsb1 none 42 io67rsb1 io102rsb1 none 43 io66rsb1 io101rsb1 none 44 io65rsb1 io100rsb1 none 45 v cc v cc none 46 gnd gnd none 47 v cci b1 v cci b1 none 48 nc io99rsb1 rule 1 49 io64rsb1 io9 7rsb1 none 50 nc io95rsb1 rule 1 51 io63rsb1 io9 3rsb1 none 52 nc io92rsb1 rule 1 53 io62rsb1 io9 0rsb1 none 54 nc io88rsb1 rule 1 55 io61rsb1 io8 6rsb1 none 56 nc io84rsb1 rule 1 57 nc io83rsb1 rule 1 58 io60rsb1 io8 2rsb1 none 59 io59rsb1 io8 1rsb1 none 60 io58rsb1 io8 0rsb1 none 61 io57rsb1 io7 9rsb1 none 62 nc v cc rule 4 63 gnd gnd none 64 nc v cci b1 rule 4 65 gdc2/io56rsb1 gdc2/io72rsb1 none 66 gdb2/io55rsb1 gdb2/io71rsb1 none 67 gda2/io54rsb1 gda2/io70rsb1 none 68 gndq gndq none 69 tck tck none 70 tdi tdi none 71 tms tms none 72 vmv1 vmv1 none table 13-6 ? pin compatibility and migration table fo r proasic3 a3p060 and a3p125 with tq144 packaging (continued) pin number a3p060 function a3p125 function migration rule between a3p125 and a3p060 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-18 v1.0 73 v pump v pump none 74 nc nc none 75 tdo tdo none 76 trst trst none 77 v jtag v jtag none 78 gda0/io50rsb0 gda0/io66rsb0 none 79 gdb0/io48rsb0 gdb0/io64rsb0 none 80 gdb1/io47rsb0 gdb1/io63rsb0 none 81 v cci b0 v cci b0 none 82 gnd gnd none 83 io44rsb0 io6 0rsb0 none 84 gcc2/io43rsb0 gcc2/io59rsb0 none 85 gcb2/io42rsb0 gcb2/io58rsb0 none 86 gca2/io41rsb0 gca2/io57rsb0 none 87 gca0/io40rsb0 gca0/io56rsb0 none 88 gca1/io39rsb0 gca1/io55rsb0 none 89 gcb0/io38rsb0 gcb0/io54rsb0 none 90 gcb1/io37rsb0 gcb1/io53rsb0 none 91 gcc0/io36rsb0 gcc0/io52rsb0 none 92 gcc1/io35rsb0 gcc1/io51rsb0 none 93 io34rsb0 io5 0rsb0 none 94 io33rsb0 io4 9rsb0 none 95 nc nc none 96 nc nc none 97 nc nc none 98 v cci b0 v cci b0 none 99 gnd gnd none 100 v cc v cc none 101 io30rsb0 io4 7rsb0 none 102 gbc2/io29rsb0 gbc2/io45rsb0 none 103 io28rsb0 io4 4rsb0 none 104 gbb2/io27rsb0 gbb2/io43rsb0 none 105 io26rsb0 io4 2rsb0 none 106 gba2/io25rsb0 gba2/io41rsb0 none 107 vmv0 vmv0 none 108 gndq gndq none 109 nc gba1/io40rsb0 rule 1 table 13-6 ? pin compatibility and migration table fo r proasic3 a3p060 and a3p125 with tq144 packaging (continued) pin number a3p060 function a3p125 function migration rule between a3p125 and a3p060 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-19 110 nc gba0/io39rsb0 rule 1 111 gba1/io24rsb0 gbb1/io38rsb0 none 112 gba0/io23rsb0 gbb0/io37rsb0 none 113 gbb1/io22rsb0 gbc1/io36rsb0 none 114 gbb0/io21rsb0 gbc0/io35rsb0 none 115 gbc1/io20rsb0 io34rsb0 rule 2 116 gbc0/io19rsb0 io33rsb0 rule 2 117 v cci b0 v cci b0 none 118 gnd gnd none 119 v cc v cc none 120 io18rsb0 io2 9rsb0 none 121 io17rsb0 io2 8rsb0 none 122 io16rsb0 io2 7rsb0 none 123 io15rsb0 io2 5rsb0 none 124 io14rsb0 io2 3rsb0 none 125 io13rsb0 io2 1rsb0 none 126 io12rsb0 io1 9rsb0 none 127 io11rsb0 io1 7rsb0 none 128 nc io16rsb0 rule 1 129 io10rsb0 io1 4rsb0 none 130 io09rsb0 io1 2rsb0 none 131 io08rsb0 io1 0rsb0 none 132 gac1/io07rsb0 io08rsb0 rule 2 133 gac0/io06rsb0 io06rsb0 rule 2 134 nc v cci b0 rule 4 135 gnd gnd none 136 nc v cc rule 4 137 gab1/io05rsb0 gac1/io05rsb0 none 138 gab0/io04rsb0 gac0/io04rsb0 none 139 gaa1/io03rsb0 gab 1/io03rsb0 none 140 gaa0/io02rsb0 gab 0/io02rsb0 none 141 io01rsb0 gaa1/io01rsb0 rule 3 142 io00rsb0 gaa0/io00rsb0 rule 3 143 gndq gndq none 144 vmv0 vmv0 none table 13-6 ? pin compatibility and migration table fo r proasic3 a3p060 and a3p125 with tq144 packaging (continued) pin number a3p060 function a3p125 function migration rule between a3p125 and a3p060 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-20 v1.0 pq208 package table 13-7 ? pin compatibility and migration table fo r proasic3 a3p125 and a3p250 with pq208 packaging pin number a3p125 function a3p250 function migration rule between a3p250 and a3p125 1 gnd gnd none 2 gaa2/io67rsb1 gaa2/io118udb3 none 3 io68rsb1 io118vdb3 none 4 gab2/io69rsb1 gab2/io117udb3 none 5 io132rsb1 io117vdb3 none 6 gac2/io131rsb1 gac 2/io116udb3 none 7 nc io116vdb3 rule 1 8 nc io115udb3 rule 1 9 io130rsb1 io115vdb3 none 10 io129rsb1 io114udb3 none 11 nc io114vdb3 rule 1 12 io128rsb1 io113pdb3 none 13 nc io113ndb3 rule 1 14 nc io112pdb3 rule 1 15 nc io112ndb3 rule 1 16 v cc v cc none 17 gnd gnd none 18 v cci b1 v cci b3 rule 5 19 io127rsb1 io111pdb3 none 20 nc io111ndb3 rule 1 21 gfc1/io126rsb1 gfc1/io110pdb3 none 22 gfc0/io125rsb1 gfc0/io110ndb3 none 23 gfb1/io124rsb1 gfb1/io109pdb3 none 24 gfb0/io123rsb1 gfb0/io109ndb3 none 25 v complf v complf none 26 gfa0/io122rsb1 gfa0/io108npb3 none 27 v ccplf v ccplf none 28 gfa1/io121rsb1 gfa1/io108ppb3 none 29 gnd gnd none 30 gfa2/io120rsb1 gfa2/io107pdb3 none 31 nc io107ndb3 rule 1 32 gfb2/io119rsb1 gfb2/io106pdb3 none 33 nc io106ndb3 rule 1 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-21 34 gfc2/io118rsb1 gfc2/io105pdb3 none 35 io117rsb1 io105ndb3 none 36 nc nc none 37 io116rsb1 io104pdb3 none 38 io115rsb1 io104ndb3 none 39 nc io103psb3 rule 1 40 v cci b1 v cci b3 rule 5 41 gnd gnd none 42 io114rsb1 io101pdb3 none 43 io113rsb1 io101ndb3 none 44 gec1/io112rsb1 gec1/io100pdb3 none 45 gec0/io111rsb1 gec0/io100ndb3 none 46 geb1/io110rsb1 geb1/io99pdb3 none 47 geb0/io109rsb1 geb0/io99ndb3 none 48 gea1/io108rsb1 g ea1/io98pdb3 none 49 gea0/io107rsb1 gea0/io98ndb3 none 50 vmv1 vmv3 rule 5 51 gndq gndq none 52 gnd gnd none 53 nc nc none 54 nc nc none 55 gea2/io106rsb1 gea2/io97rsb2 none 56 geb2/io105rsb1 geb2/io96rsb2 none 57 gec2/io104rsb1 gec2/io95rsb2 none 58 io103rsb1 io94rsb2 none 59 io102rsb1 io93rsb2 none 60 io101rsb1 io92rsb2 none 61 io100rsb1 io91rsb2 none 62 v cci b1 v cci b2 rule 5 63 io99rsb1 io90rsb2 none 64 io98rsb1 io89rsb2 none 65 gnd gnd none 66 io97rsb1 io88rsb2 none 67 io96rsb1 io87rsb2 none table 13-7 ? pin compatibility and migration table fo r proasic3 a3p125 and a3p250 with pq208 packaging (continued) pin number a3p125 function a3p250 function migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-22 v1.0 68 io95rsb1 io86rsb2 none 69 io94rsb1 io85rsb2 none 70 io93rsb1 io84rsb2 none 71 v cc v cc none 72 v cci b1 v cci b2 rule 5 73 io92rsb1 io83rsb2 none 74 io91rsb1 io82rsb2 none 75 io90rsb1 io81rsb2 none 76 io89rsb1 io80rsb2 none 77 io88rsb1 io79rsb2 none 78 io87rsb1 io78rsb2 none 79 io86rsb1 io77rsb2 none 80 io85rsb1 io76rsb2 none 81 gnd gnd none 82 io84rsb1 io75rsb2 none 83 io83rsb1 io74rsb2 none 84 io82rsb1 io73rsb2 none 85 io81rsb1 io72rsb2 none 86 io80rsb1 io71rsb2 none 87 io79rsb1 io70rsb2 none 88 v cc v cc none 89 v cci b1 v cci b2 rule 5 90 io78rsb1 io69rsb2 none 91 io77rsb1 io68rsb2 none 92 io76rsb1 io67rsb2 none 93 io75rsb1 io66rsb2 none 94 io74rsb1 io65rsb2 none 95 io73rsb1 io64rsb2 none 96 gdc2/io72rsb1 gdc2/io63rsb2 none 97 gnd gnd none 98 gdb2/io71rsb1 gdb2/io62rsb2 none 99 gda2/io70rsb1 gda 2/io61rsb2 none 100 gndq gndq none 101 tck tck none table 13-7 ? pin compatibility and migration table fo r proasic3 a3p125 and a3p250 with pq208 packaging (continued) pin number a3p125 function a3p250 function migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-23 102 tdi tdi none 103 tms tms none 104 vmv1 vmv2 rule 5 105 gnd gnd none 106 v pump v pump none 107 nc nc none 108 tdo tdo none 109 trst trst none 110 v jtag v jtag none 111 gda0/io66rsb0 gda 0/io60vdb1 none 112 gda1/io65rsb0 gda 1/io60udb1 none 113 gdb0/io64rsb0 gdb0/io59vdb1 none 114 gdb1/io63rsb0 gdb1/io59udb1 none 115 gdc0/io62rsb0 gdc0/io58vdb1 none 116 gdc1/io61rsb0 gdc1/io58udb1 none 117 nc io57vdb1 rule 1 118 nc io57udb1 rule 1 119 nc io56ndb1 rule 1 120 nc io56pdb1 rule 1 121 nc io55rsb1 rule 1 122 gnd gnd none 123 v cci b0 v cci b1 rule 5 124 nc nc none 125 nc nc none 126 v cc v cc none 127 io60rsb0 io53ndb1 none 128 gcc2/io59rsb0 gcc2/io53pdb1 none 129 gcb2/io58rsb0 gcb2/io52psb1 none 130 gnd gnd none 131 gca2/io57rsb0 gca2/io51psb1 none 132 gca0/io56rsb0 gca1/io50pdb1 none 133 gca1/io55rsb0 gca0/io50ndb1 none 134 gcb0/io54rsb0 gcb0/io49ndb1 none 135 gcb1/io53rsb0 gcb1/io49pdb1 none table 13-7 ? pin compatibility and migration table fo r proasic3 a3p125 and a3p250 with pq208 packaging (continued) pin number a3p125 function a3p250 function migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-24 v1.0 136 gcc0/io52rsb0 gcc0/io48ndb1 none 137 gcc1/io51rsb0 gcc1/io48pdb1 none 138 io50rsb0 io47ndb1 none 139 io49rsb0 io47pdb1 none 140 v cci b0 v cci b1 rule 5 141 gnd gnd none 142 v cc v cc none 143 io48rsb0 io46rsb1 none 144 io47rsb0 io45ndb1 none 145 io46rsb0 io45pdb1 none 146 nc io44ndb1 rule 1 147 nc io44pdb1 rule 1 148 nc io43ndb1 rule 1 149 gbc2/io45rsb0 gbc2/io43pdb1 none 150 io44rsb0 io42ndb1 none 151 gbb2/io43rsb0 gbb2/io42pdb1 none 152 io42rsb0 io41ndb1 none 153 gba2/io41rsb0 gba2/io41pdb1 none 154 vmv0 vmv1 rule 5 155 gndq gndq none 156 gnd gnd none 157 nc nc none 158 gba1/io40rsb0 gba1/io40rsb0 none 159 gba0/io39rsb0 gba0/io39rsb0 none 160 gbb1/io38rsb0 gbb1/io38rsb0 none 161 gbb0/io37rsb0 gbb0/io37rsb0 none 162 gnd gnd none 163 gbc1/io36rsb0 gbc1/io36rsb0 none 164 gbc0/io35rsb0 gbc0/io35rsb0 none 165 io34rsb0 io34rsb0 none 166 io33rsb0 io33rsb0 none 167 io32rsb0 io32rsb0 none 168 io31rsb0 io31rsb0 none 169 io30rsb0 io30rsb0 none table 13-7 ? pin compatibility and migration table fo r proasic3 a3p125 and a3p250 with pq208 packaging (continued) pin number a3p125 function a3p250 function migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-25 170 v cci b0 v cci b0 none 171 v cc v cc none 172 io29rsb0 io29rsb0 none 173 io28rsb0 io28rsb0 none 174 io27rsb0 io27rsb0 none 175 io26rsb0 io26rsb0 none 176 io25rsb0 io25rsb0 none 177 io24rsb0 io24rsb0 none 178 gnd gnd none 179 io23rsb0 io23rsb0 none 180 io22rsb0 io22rsb0 none 181 io21rsb0 io21rsb0 none 182 io20rsb0 io20rsb0 none 183 io19rsb0 io19rsb0 none 184 io18rsb0 io18rsb0 none 185 io17rsb0 io17rsb0 none 186 v cci b0 v cci b0 none 187 v cc v cc none 188 io16rsb0 io16rsb0 none 189 io15rsb0 io15rsb0 none 190 io14rsb0 io14rsb0 none 191 io13rsb0 io13rsb0 none 192 io12rsb0 io12rsb0 none 193 io11rsb0 io11rsb0 none 194 io10rsb0 io10rsb0 none 195 gnd gnd none 196 io09rsb0 io09rsb0 none 197 io08rsb0 io08rsb0 none 198 io07rsb0 io07rsb0 none 199 io06rsb0 io06rsb0 none 200 v cci b0 v cci b0 none 201 gac1/io05rsb0 gac1/io05rsb0 none 202 gac0/io04rsb0 gac0/io04rsb0 none 203 gab1/io03rsb0 gab1/io03rsb0 none table 13-7 ? pin compatibility and migration table fo r proasic3 a3p125 and a3p250 with pq208 packaging (continued) pin number a3p125 function a3p250 function migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-26 v1.0 204 gab0/io02rsb0 gab0/io02rsb0 none 205 gaa1/io01rsb0 gaa 1/io01rsb0 none 206 gaa0/io00rsb0 gaa 0/io00rsb0 none 207 gndq gndq none 208 vmv0 vmv0 none table 13-7 ? pin compatibility and migration table fo r proasic3 a3p125 and a3p250 with pq208 packaging (continued) pin number a3p125 function a3p250 function migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-27 fg144 package table 13-8 ? pin compatibility and migratio n table for proasic3 a3p060, a3p125, and a3p250 with fg144 packaging pin no. a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 a1 gndq gndq gndq none none none a2 vmv0 vmv0 vmv0 none none none a3 gab0/io04rsb0 gab0/io02rsb0 gab0/io02rsb0 none none none a4 gab1/io05rsb0 gab1/io03rsb0 gab1/io03rsb0 none none none a5 io08rsb0 io11rsb0 io16rsb0 none none none a6 gnd gnd gnd none none none a7 io11rsb0 io18rsb0 io29rsb0 none none none a8 v cc v cc v cc none none none a9 io16rsb0 io25rsb0 io33rsb0 none none none a10 gba0/io23rsb0 gba0/io39rsb0 gba0/io39rsb0 none none none a11 gba1/io24rsb0 gba1/io40rsb0 gba1/io40rsb0 none none none a12 gndq gndq gndq none none none b1 gab2/io53rsb1 gab2/io69rsb1 gab2/io117udb3 none none none b2 gnd gnd gnd none none none b3 gaa0/io02rsb0 gaa0/io00rsb0 gaa0/io00rsb0 none none none b4 gaa1/io03rsb0 gaa1/io01rsb0 gaa1 /io01rsb0 none rule 6 rule 6 b5 io00rsb0 io08rsb0 io14rsb0 none none none b6 io10rsb0 io14rsb0 io19rsb0 none none none b7 io12rsb0 io19rsb0 io22rsb0 none none none b8 io14rsb0 io22rsb0 io30rsb0 none none none b9 gbb0/io21rsb0 gbb0/io37rsb0 gbb0/io37rsb0 none none none b10 gbb1/io22rsb0 gbb1/io38rsb0 gbb1/io38rsb0 none none none b11 gnd gnd gnd none none none b12 vmv0 vmv0 vmv1 none none none c1 io95rsb1 io132rsb1 i o117vdb3nonenonenone c2 gfa2/io83rsb1 gfa2/io120rsb1 gfa2/io107ppb3 none none none c3 gac2/io94rsb1 gac 2/io131rsb1 gac2/io116udb3 none none none c4 v cc v cc v cc none none none c5 io01rsb0 io10rsb0 io12rsb0 none none none notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-28 v1.0 c6 io09rsb0 io12rsb0 io17rsb0 none none none c7 io13rsb0 io21rsb0 io24rsb0 none none none c8 io15rsb0 io24rsb0 io31rsb0 none none none c9 io17rsb0 io27rsb0 io34rsb0 none none none c10 gba2/io25rsb0 gba2/io41rsb0 gba2/io41pdb1 none none none c11 io26rsb0 io42rsb0 io41ndb1 none none none c12 gbc2/io29rsb0 gbc2/io45rsb0 gbc2/io43ppb1 none none none d1 io91rsb1 io128rsb1 io112ndb3 none none none d2 io92rsb1 io129rsb1 io112pdb3 none none none d3 io93rsb1 io130rsb1 i o116vdb3nonenonenone d4 gaa2/io51rsb1 gaa2/io67rsb1 gaa2/io118upb3 none none none d5 gac0/io06rsb0 gac0/io04rsb0 gac0/io04rsb0 none none none d6 gac1/io07rsb0 gac1/io05rsb0 gac1/io05rsb0 none none none d7 gbc0/io19rsb0 gbc0/io35rsb0 gbc0/io35rsb0 none none none d8 gbc1/io20rsb0 gbc1/io36rsb0 gbc1/io36rsb0 none none none d9 gbb2/io27rsb0 gbb2/io43rsb0 gbb2/io42pdb1 none none none d10 io18rsb0 io28rsb0 io42ndb1 none none none d11 io28rsb0 io44rsb0 io43npb1 none none none d12 gcb1/io37rsb0 gcb1/io53rsb 0 gcb1/io49ppb1 none none none e1 v cc v cc v cc none none none e2 gfc0/io88rsb1 gfc0/io125rsb 1 gfc0/io110ndb3 none none none e3 gfc1/io89rsb1 gfc1/io126rsb 1 gfc1/io110pdb3 none none none e4 v cci b1 v cci b1 v cci b3 none rule 5 rule 5 e5 io52rsb1 io68rsb1 io118vpb3 none none none e6 v cci b0 v cci b0 v cci b0 none none none e7 v cci b0 v cci b0 v cci b0 none none none e8 gcc1/io35rsb0 gcc1/io51rsb0 gcc1/io48pdb1 none none none e9 v cci b0 v cci b0 v cci b1 none rule 5 rule 5 e10 v cc v cc v cc none none none e11 gca0/io40rsb0 gca0/io56rs b0 gca0/io50ndb1 none none none e12 io30rsb0 io46rsb0 io 51ndb1nonenonenone table 13-8 ? pin compatibility and migratio n table for proasic3 a3p060, a3p125, and a3p250 with fg144 packaging (continued) pin no. a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-29 f1 gfb0/io86rsb1 gfb0/io123rsb 1 gfb0/io109npb3 none none none f2 v complf v complf v complf none none none f3 gfb1/io87rsb1 gfb1/io124rsb 1 gfb1/io109ppb3 none none none f4 io90rsb1 io127rsb1 io107npb3 none none none f5 gnd gnd gnd none none none f6 gnd gnd gnd none none none f7 gnd gnd gnd none none none f8 gcc0/io36rsb0 gcc0/io52rsb0 gcc0/io48ndb1 none none none f9 gcb0/io38rsb0 gcb0/io54rsb 0 gcb0/io49npb1 none none none f10 gnd gnd gnd none none none f11 gca1/io39rsb0 gca1/io55rsb0 gca1/io50pdb1 none none none f12 gca2/io41rsb0 gca2/io57rsb0 gca2/io51pdb1 none none none g1 gfa1/io84rsb1 gfa1/io121rsb1 gfa1/io108ppb3 none none none g2 gnd gnd gnd none none none g3 v ccplf v ccplf v ccplf none none none g4 gfa0/io85rsb1 gfa0/io122rsb1 gfa0/io108npb3 none none none g5 gnd gnd gnd none none none g6 gnd gnd gnd none none none g7 gnd gnd gnd none none none g8 gdc1/io45rsb0 gdc1/io61rsb0 gdc1/io58upb1 none none none g9 io32rsb0 io48rsb0 io53ndb1 none none none g10 gcc2/io43rsb0 gcc2/io59rsb 0 gcc2/io53pdb1 none none none g11 io31rsb0 io47rsb0 io52ndb1 none none none g12 gcb2/io42rsb0 gcb2/io58rsb 0 gcb2/io52pdb1 none none none h1 v cc v cc v cc none none none h2 gfb2/io82rsb1 gfb2/io119rsb 1 gfb2/io106pdb3 none none none h3 gfc2/io81rsb1 gfc2/io118rsb 1 gfc2/io105psb3 none none none h4 gec1/io77rsb1 gec1/io112rsb1 gec1/io100pdb3 none none none h5 v cc v cc v cc none none none h6 io34rsb0 io50rsb0 io79rsb2 none none none h7 io44rsb0 io60rsb0 io65rsb2 none none none table 13-8 ? pin compatibility and migratio n table for proasic3 a3p060, a3p125, and a3p250 with fg144 packaging (continued) pin no. a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-30 v1.0 h8 gdb2/io55rsb1 gdb2/io71rsb1 gdb2/io62rsb2 none none none h9 gdc0/io46rsb0 gdc0/io62rs b0 gdc0/io58vpb1 none none none h10 v cci b0 v cci b0 v cci b1 none rule 5 rule 5 h11 io33rsb0 io49rsb0 i o54psb1nonenonenone h12 v cc v cc v cc none none none j1 geb1/io75rsb1 geb1/io110rsb 1 geb1/io99pdb3 none none none j2 io78rsb1 io115rsb1 io106ndb3 none none none j3 v cci b1 v cci b1 v cci b3 none rule 5 rule 5 j4 gec0/io76rsb1 gec0/io111rsb1 gec0/io100ndb3 none none none j5 io79rsb1 io116rsb1 i o88rsb2nonenonenone j6 io80rsb1 io117rsb1 i o81rsb2nonenonenone j7 v cc v cc v cc none none none j8 tck tck tck none none none j9 gda2/io54rsb1 gda2/io70rsb1 gda2/io61rsb2 none none none j10 tdo tdo tdo none none none j11 gda1/io49rsb0 gda1/io65rsb 0 gda1/io60udb1 none none none j12 gdb1/io47rsb0 gdb1/io63rsb 0 gdb1/io59udb1 none none none k1 geb0/io74rsb1 geb0/io109rsb 1 geb0/io99ndb3 none none none k2 gea1/io73rsb1 gea1/io108rsb 1 gea1/io98pdb3 none none none k3 gea0/io72rsb1 gea0/io107rsb 1 gea0/io98ndb3 none none none k4 gea2/io71rsb1 gea2/io106rsb1 gea2/io97rsb2 none none none k5 io65rsb1 io100rsb1 i o90rsb2nonenonenone k6 io64rsb1 io98rsb1 io84rsb2 none none none k7 gnd gnd gnd none none none k8 io57rsb1 io73rsb1 io66rsb2 none none none k9 gdc2/io56rsb1 gdc2/io72rsb1 gdc2/io63rsb2 none none none k10 gnd gnd gnd none none none k11 gda0/io50rsb0 gda0/io66rsb 0 gda0/io60vdb1 none none none k12 gdb0/io48rsb0 gdb0/io64rsb0 gdb0/io59vdb1 none none none l1 gnd gnd gnd none none none l2 vmv1 vmv1 vmv3 none rule 5 rule 5 table 13-8 ? pin compatibility and migratio n table for proasic3 a3p060, a3p125, and a3p250 with fg144 packaging (continued) pin no. a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices v1.0 13-31 l3 geb2/io70rsb1 geb2/io105rsb 1 geb2/io96rsb2 none none none l4 io67rsb1 io102rsb1 i o91rsb2nonenonenone l5 v cci b1 v cci b1 v cci b2 none rule 5 rule 5 l6 io62rsb1 io95rsb1 io82rsb2 none none none l7 io59rsb1 io85rsb1 io80rsb2 none none none l8 io58rsb1 io74rsb1 io72rsb2 none none none l9 tms tms tms none none none l10 v jtag v jtag v jtag none none none l11 vmv1 vmv1 vmv2 none rule 5 rule 5 l12 trst trst trst none none none m1 gndq gndq gndq none none none m2 gec2/io69rsb1 gec2/io104rsb 1 gec2/io95rsb2 none none none m3 io68rsb1 io103rsb1 i o92rsb2nonenonenone m4 io66rsb1 io101rsb1 i o89rsb2nonenonenone m5 io63rsb1 io97rsb1 io87rsb2 none none none m6 io61rsb1 io94rsb1 io85rsb2 none none none m7 io60rsb1 io86rsb1 io78rsb2 none none none m8 nc io75rsb1 io76rsb2 rule 1 rule 1 none m9tdi tdi tdi nonenonenone m10 v cci b1 v cci b1 v cci b2 none rule 5 rule 5 m11 v pump v pump v pump none none none m12 gndq gndq gndq none none none table 13-8 ? pin compatibility and migratio n table for proasic3 a3p060, a3p125, and a3p250 with fg144 packaging (continued) pin no. a3p060 function a3p125 function a3p250 function migration rule between a3p125 and a3p060 migration rule between a3p250 and a3p060 migration rule between a3p250 and a3p125 notes: 1. see table 13-3 on page 13-3 for the high-density/low-densi ty pin combination guidelines. 2. "none" implies that the pins can be connected without any change. migrating designs from a3p250 to lower-logic-density devices 13-32 v1.0 conclusion this application note describes the design migr ation among proasic3 family devices with an emphasis on package pin compatib ility. devices in the proasic3 family share numerous common architectural features. however, no t all architectural features of fa mily members are identical; use the datasheet to identi fy differences. additi onally, a key requiremen t is running functional simulation before and after the migration using actel tools. actel will continue to update this application note with additional packages. related documents handbook documents i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-018-0 revised january 2008 migrating designs from a3p250 to lower-logic-density devices v1.0 13-33 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.0) page 51900135-2/12.06 in table 13-1 device information , a3p250 device information was updated. 13-1 in table 13-2 common and convertible i/os , i/o counts for the vq100 package were updated. 13-2 in table 13-4 pin compatibility and migration table for a3p030, a3p060, a3p125, and a3p250 wi th vq100 packaging , the a3p030 pin function information was updated. several ru les changed throughout the table. 13-5 51900135-1/12.06 table13-1device information was updated to include a3p030 device information. 13-1 table 13-2 common and convertible i/os was updated. 13-2 the "migration and implementati on methodologies" section was updated. 13-2 table 13-3 migration rules from higher -density device to lower-density device was updated. 13-3 in table 13-4 pin compatibility and migration table for a3p030, a3p060, a3p125, and a3p250 with vq100 packaging , the a3p030 pin information was updated. several rules changed throughout the table. 13-5 in table 13-5 pin compatibility and migration table for a3p030, a3p060, a3p125, and a3p250 with qfn132 packaging , all pin data was updated. several rules changed throughout the table. 13-10 in table 13-7 pin compatibility and migrat ion table for proasic3 a3p125 and a3p250 with pq208 packaging , the rules were updated for the following pins: 50, 104, and 154. 13-20 in table 13-8 pin compatibility and mi gration table for proasic3 a3p060, a3p125, and a3p250 with fg144 packaging , the rules were updated for the following pins: l2 and l11. 13-27 51900135-0/5.06 qn132 info rmation was added to table 13-1 device information . 13-1 qn132 information was added to table 13-2 common and convertible i/os . 13-2 table 13-6 pin compatibility and migr ation table for proasic3 a3p060 and a3p125 with tq144 packaging is new. 13-16 migrating designs from a3p250 to lower-logic-density devices v1.0 13-35 migrating designs from a3p250 to lower-logic-density devices 13-36 v1.0 programming and security v1.1 14-1 application note ac315 14 ? programming flash devices introduction this document provides an over view of the various programming options available for the actel flash families. the electr onic version of this document includes active links to all programming resources, which are available at http://www.actel.com/produc ts/hardware/default.aspx . for actel antifuse devices, refer to the programming anti fuse devices document. summary of programming support flashpro3 is a high-performance in-system prog ramming (isp) tool ta rgeted at the latest generation of low-power flash devices offered by actel: igloo, ? fusion, and proasic ? 3, including arm ? -enabled devices. flashpro3 of fers extremely high performanc e through the use of usb 2.0 and is high-speed compli ant for full use of the 480 mbps bandwidth. this newest programmer can program proasic3e devices in under 30 seconds; even the largest proasic3e devices take under two minutes to program. powered exclus ively via usb, flashpro3 provides a v pump voltage of 3.3 v for programming these devices. silicon sculptor 3 is an easy-to-u se, single-site programming tool for actel fpgas that delivers high data throughput and promotes ease of use whil e lowering the overall cost of ownership. silicon sculptor 3 includes a high-speed usb 2.0 interface that allows a customer to connect as many as 12 programmers to a single pc. furthe rmore, silicon sculptor 3 is co mpatible with adapter modules from silicon sculptor ii , thereby preserving a customer's investment and enabling a seamless upgrade to this latest ge neration of the tool. for details of programmer suppo rt for each device, refer to table 14-5 on page 14-8 . general flash programming information programming basics when choosing a programming solu tion, there are a number of op tions available. this section provides a brief overview of those options. the next sections provide more detail on those options as they apply to actel fpgas. reprogrammable or one-time-programmable (otp) depending on the technology chosen, devi ces may be reprogrammable or one-time- programmable. as the name impl ies, a reprogrammable device can be programmed many times. generally, the contents of such a device will be completely overwritten wh en it is reprogrammed. all actel flash devices are reprogrammable. an otp device is programmable one time only. once programmed, no more changes can be made to the contents. actel flash devi ces provide the option of disa bling the reprogrammability for security purposes. this combines the convenience of reprogrammabi lity during design verification with the security of an otp techno logy for highly sensitive designs. device programmer or in-system programming there are two fundamental ways to program an fpga: using a device programmer or, if the technology permits, using in-system programming. a device programmer is a piece of equipment in a lab or on the production floor that is used fo r programming devices. th e devices are placed into a socket mounted in a programming adapter modu le, and the appropriate electrical interface is applied. the device can then be placed on the board. a typical programmer, used during programming flash devices 14-2 v1.1 development, programs a single device at a time and is referred to as a single-site engineering programmer. with isp, the device is alread y mounted onto the board when pr ogramming occurs, most typically via the jtag pins. the jtag pins can be controlled either by an on-board resource, such as a microprocessor, or by an off-board programmer through a header connection. once mounted, it can be programmed repeatedly. if the applicatio n requires it, the syst em can be designed to reprogram itself using a microprocessor, wi thout the use of any external programmer. for production, high-volume multi-site production programmers handle designs that require device programmers. in addition, actel can preprogram devices for production, negating the need for further programming. this service is re ferred to as in-hou se programming (ihp). live at power-up (l apu) or boot prom utilizing the technology of the fpga significan tly impacts board-level po wer-up considerations. some technologies are nonvolatile and are consid ered functional, or "live," as soon as power reaches the operational level. all actel fpga tech nologies are live at power-up. by contrast, sram technology is volatile, and devices built using sr am cells lose their cont ents when power cycling occurs. these devices must be reprogrammed ever y time power is applied. such a design must include nonvolatile storage for the contents as we ll as the means to reprogram. there is a delay before sram devices are functional; other parts of the board mu st come alive first to reprogram these types of fpgas. therefore, such devices ca n never be part of critical boot circuits. design security design security is a growin g concern for systems designer s. the choice of programming methodology and technology affects system security . use of actel programmi ng technology is the most secure option available, pr oviding much better protection than sram-based devices and asics. actel provides a number of ways to ensu re designs are protected. general information on design security can be fo und on the actel website: http://www.actel.com/products/so lutions/security /default.aspx programming features for actel devices actel provides two types of fpgas: flash and antifuse ( table 14-1 ). some progra mming methods are common to both and some are exclusive to flash. this document describes only the programming soluti ons supported for flash devices. flash devices the flash devices su pplied by actel are reprog rammable by either a generic device programmer or isp. actel supports isp using jtag, which is supporte d by the flashpro3, flas hpro, flashpro lite, and sculptor programmers. levels of isp support vary de pending on the device chosen: ? fusion, proasic3, and proasic3e devices support isp. ? proasic3l devices operate using a 1.2 v core voltage and support isp at 1.5 v only. voltage switching is required in-system to switch from a 1.2 v core to 1.5 v core for programming. table 14-1 ? programming features for actel devices feature flash antifuse reprogrammable yes no in-system programmable yes no one-time programmable yes (option) yes live at power-up yes yes secure yes yes single-site programmer support yes yes multi-site programmer support yes yes in-house programming support yes yes programming flash devices v1.1 14-3 ? igloo, igloo plus, and iglooe v5 devices can be programmed in-system when the device is using a 1.5 v supply voltage to the fpga core. ? igloo, igloo plus, and iglooe v2 devices ca n operate using either 1.2 v core voltage or 1.5 v core voltage. alth ough the device can operate at 1. 2 v core voltage, the device can only be reprogrammed when the core voltage is 1.5 v. voltage switching is required in- system to switch from a 1.2 v supply (v cc , v cci , and v jtag ) to 1.5 v for programming. since flash devices are nonvolatile, they are live at power-up. this is different from an sram-based device, which loads its programming information wh en it is powered up. sram devices require a time on the order of hundreds of mil liseconds before the system is active. there are multiple levels of securi ty available in flash devices. us e of a security key will lock the device. the device can then only be reprogra mmed by first unlocking the device with the appropriate security key. it can also be locked permanently, whic h means there is no key that can access the device. the command to secure the device is embedded within the programming file, optionally enabled by the programming software. this is also referred to as the otp version of flash, allowing for only a single programming insta nce. this is discussed in more detail in the implementation of security in actel's proasic and proasic plus flash-based fpgas application note. for proasic3/e devices, refer to security in low-power flash devices flash devices can also be progra mmed using single-sit e or multi-site programmers as well as volume-programming services from actel or other vendors. types of programming for flash devices the number of devices to be programmed will influence the optimal programming methodology. those available are listed below: ? in-system programming ? using a programmer ? using a microprocesso r or microcontroller ? device programmers ? single-site programmers ? multi-site programmers, batch prog rammers, or gang programmers ? automated production (robotic) programmers ? volume programming services ? actel in-house programming ? programming centers in-system programming device type supported: flash isp refers to programming the fpga after it has been mounted on the syste m board. the fpga may be preprogrammed and later reprogrammed using isp. the advantage of using isp is the ability to update the fpga design many times without any changes to the board. th is eliminates the require ment of using a socket for the fpga, saving cost and improving reliability. it also reduces progra mming hardware expenses, as the isp methodology is die-/packag e-independent. there are two methods of in-system programming: external and internal. ? programmer isp?refer to in-system programming (isp) of actel?s low-power flash devices using flashpro3 for more information. using an external programmer and a cable, the device can be programmed through a header on the system boar d. in actel documentation, this is referred to as external isp. actel provides flashpro3, flashpro lite, flashpro, or silicon sculptor 3 to perform external isp. note that silicon sculptor 3 can only provide isp for proasic and proasic plus ? families, not for proasic3 or proasic3e. programming flash devices 14-4 v1.1 ? advantages: allows local control of progra mming and data files for maximum security. the programming algorithms and hardware ar e available from actel. the only hardware required on the board is a programming header. ? limitations: a negligible board space re quirement for the prog ramming header and jtag signal routing ? microprocessor isp?refer to microprocessor programming of actel?s low-power flash devices for more information. using a microprocessor and an external or internal memory, you can store the program in memory and use the microprocessor to perfo rm the programming. in actel documentation, this is referred to as internal isp. both the code for the progra mming algorithm and the fpga programming file must be stored in me mory on the board. programming voltages must also be generated on the board. ? advantages: the programming code is st ored in the system memory. an external programmer is not required during programming. ? limitations: this is the approach that requ ires the most design work, since some way of getting and/or storing the data is needed; a system interface to the device must be designed; and the low-level api to the pr ogramming firmware must be written and linked into the code provided by actel. wh ile there are benefits to this methodology, serious thought and planning should go into the decision. device programmers device type supported: flash and antifuse device programmers are used to program a device before it is mounted on the system board. the advantage of using device pr ogrammers is that no programming hardware is required on the system board. therefore, no additional components or board space are required. if devices are to be reprogrammed multiple times, or if the quantity of devices to be programmed is relatively low, a single-site device programmer is the simplest so lution. for applications in which design security is paramount (often the case in military or space desi gns), the use of on-site programing maintains design security at all times. adapter modules are purc hased with the programmers to supp ort the fpga packages used. the fpga is placed in the adapter module and the programming software is run from a pc. actel supplies the programm ing software for all of the actel prog rammers. the softwa re allows for the selection of the correct die/pack age and programming files. it wi ll then program and verify the device. ? single-site programmers a single-site programmer programs one device at a time. actel offers silicon sculptor 3 as a single-site programmer. ? advantages: lower cost than multi-site programmers. no additional overhead for programming on the system board. allows lo cal control of programming and data files for maximum security. allows on-demand programming on-site. ? limitations: only programs one device at a time. ? multi-site programmers often referred to as batch or gang prog rammers, multi-site programmers can program multiple devices at the same time using the sa me programming file. this is often used for large volume programming and by programming houses. the sites of ten have independent processors and memory enabling the sites to operat e concurrently, meaning each site may start programming the same file independently. this enables the operator to change one device while the other sites continue programming, which increases throughput. multiple adapter modules for the same package are required when us ing a multi-site programmer. silicon sculptor i, ii, and 3 pr ogrammers can be cascaded to program multiple devices in a chain. multi-site programmers can also be purchased from bp microsystems. ? advantages: provides the capability of prog ramming multiple devices at the same time. no additional overhead for programming on the system board. allows local control of programming and data files for maximum security. programming flash devices v1.1 14-5 ? limitations: more expensive than a single-site programmer ? automated production (robotic) programmers automated production programmers are based on multi-site programmers. they consist of a large input tray holding multiple parts and a robotic arm to select and place parts into appropriate programming socke ts automatically. when the programming of the parts is complete, the parts are remove d and placed in a finished tray. the automated programmers are often used in volume programming houses to program parts for which the programming time is small. volume programming services device type supported: flash and antifuse once the design is stable for ap plications with large production volumes, preprogrammed devices can be purchased. table 14-2 describes the volume programming services. advantages: as programming is outs ourced, this solution is easier to implement th an creating a substantial in-house programming capability. as programming hous es specialize in large-volume programming, this is often th e most cost-effective solution. limitations: there are some logistical issues with the use of a programming service provider, such as the transfer of programming files and the approval of first articl es. by definition, the programming file must be released to a third-party progra mming house. nondisclos ure agreements (ndas) can be signed to help ensure data protection; however, for extremel y security-conscious designs, this may not be an option. ? actel in-house programming when purchasing actel devices in volume, ihp can be requested as part of the purchase. if this option is chosen, there is a small cost adder for each device programmed. each device is marked with a special mark to distinguish it from blank parts. prog ramming files for the design will be sent to actel. sample parts wi th the design programmed , first articles, will be returned for customer approval. once approval of first articles has been received, actel will proceed with programming the remainder of th e order. to request actel ihp, contact your local actel representative. ? distributor programming centers if purchases are made through a distributor, many distributors will provide programming for their customers. cons ult with your preferred dis tributor about this option. ? independent programming centers there are many programming centers that sp ecialize only in programming but are not directly affiliated with actel or our distributo rs. these programming centers must follow the guidelines for programming ac tel devices and use certified programmers to program actel devices. actel does not have recommendat ions for external programming centers. table 14-2 ? volume programming services programmer vendor availability in-house programming actel contact actel sales distributor programming centers me mec unique contact distribution independent programming centers various contact vendor programming flash devices 14-6 v1.1 programming solutions details for the available programmers can be found in the programmer user's guides listed in the "related documents" section on page 14-12 . refer to table 14-3 on page 14-6 for more information concerning programming solutions. all of the programmers except the flashpro3, flas hpro lite, and flashpro require adapter modules, which are designed to support device packages. the modules are all listed on the actel website at http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . they are not listed in this document, sinc e this list is updated frequently with new package options and any upgrades required to improve programming yield or support new families. programmer ordering codes the products shown in table 14-4 can be ordered through actel sales and will be shipped directly from actel. products can also be or dered from actel distributors, bu t will still be shipped directly from actel. table 14-4 includes ordering codes for the full kit, as well as codes for replacement items and any related hardware. some additi onal products can be purchased from external suppliers for use with the prog rammers. ordering codes for ad apter modules used with silicon sculptor are available on the actel website at http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . table 14-3 ? programming solutions programmer vendor isp single device multi-device availability flashpro3 actel only yes yes 1 available flashpro lite actel only yes yes 1 available flashpro actel only yes yes 1 available silicon sculptor 3 actel yes yes cascade option (up to two) available silicon sculptor ii actel yes yes 2 cascade option (up to two) available silicon sculptor actel yes yes cascade option (up to four) discontinued sculptor 6x actel no yes yes discontinued bp microprogrammers bp microsystems no yes yes contact bp microsystems at www.bpmicro.com notes: 1. multiple devices can be connected in the same jtag chain for programming. 2. silicon sculptor ii can only provide isp for proasic and proasic plus families, not for proasic3/e. table 14-4 ? programming ordering codes description vendor ordering code comment flashpro3 isp programmer actel flashpro 3 uses a 2x5, ra male header connector flashpro lite isp programmer actel flashpro lite supports small pr ogramming header or large header through header converter (not included) flashpro isp programmer actel flash pro supports small prog ramming header or large header through header converter (not included) silicon sculptor 3 actel silicon-sculptor 3 usb 2.0 high-speed production programmer silicon sculptor ii actel silicon-sculptor ii requires add-on adapter modules to support devices silicon sculptor isp module actel smpa-isp-actel-3-kit ships with both large and small header support * a maximum of two silicon sculptor ii programmers can be chained together using a standard ieee 1284 parallel port cable. programming flash devices v1.1 14-7 concurrent programming cable actel ss-expander used to cascad e silicon sculptor i programmers together* software for silicon sculptor actel sculptor-software-cd http://www.actel.com/download/program_debug/ss/ isp cable for small header actel isp-cable-s supplied with smpa-isp-actel-3-kit isp cable for large header actel pa-isp-cable supplied with smpa-isp-actel-3-kit header converter actel header-converter converts from small to large header small programming header samtec ftsh-113-01-l-d-k supported by flashpro, flashpro lite, and silicon sculptor in migrating to proasic3 /e devices, an fp3-26pin- adapter is required. 10-pin 0.1" pitch cable header (right- angle pcb mount angle) amp 103310-1 supported by flashpro3 10-pin 0.1" pitch cable header (straight pcb mount angle) 3m 2510-6002ub supported by flashpro3 compact programming header (10-pin 0.05" pitch, 2 rows of 5 pins) samtec ftsh-105-01-l-d-k supported by flashpro3, fp3-26pin-adapter required. used for boards where space is at a premium. migration and compact header adapter actel fp3-26pin-adapter required with the use of ftsh-105-01-l-d-k large programming header 0.062" board thickness 3m 3429-6502 supported by silicon sc ulptor by default, flashpro, and flashpro lite, with header converter large programming header 0.094" to 0.125" board thickness 3m 3429-6503 supported by silicon sc ulptor by default, flashpro, and flashpro lite, with header converter plug-in header small actel smpa-isp-header-s requi red for small header fo r proasic only; not used for proasic plus plug-in header actel smpa-isp-header required for large header for proasic only; not used for proasic plus vacuum pens for pq, tq, vq; <208 pins actel penvac vacuum pens for pq, tq, vq; 208 pins actel penvac-hd heavy-duty, provides stronger vacuum table 14-4 ? programming ordering codes (continued) description vendor ordering code comment * a maximum of two silicon sculptor ii programmers can be chained together using a standard ieee 1284 parallel port cable. programming flash devices 14-8 v1.1 programmer device support refer to table 14-5 to determine which general-purpose flash devices have programmer device support. to learn more about the different actel families, refer to the actel website: http://www.actel.com/products/devices.aspx. data in table 14-5 also applies to arm-enabled m7 device versions of fusion, igloo, and proasic3 devices. refer to the appropriate family data sheets for information on die/package combinations available as arm- enabled versions. table 14-5 ? programmer device support actel family device arm- enabled silicon sculptor silicon sculptor 6x silicon sculptor ii silicon sculptor 3flashpro flashpro lite flashpro3 fusion afs090 no no yes. no isp support. yes. no isp support. no no yes. isp support afs250 afs600 ? afs1500 ? igloo agl015 no no yes. no isp support. yes. no isp support. no no yes. isp support. agl030 agl060 agl125 agl250 ? agl600 ? agl1000 ? igloo plus aglp030 no no yes. no isp support yes. no isp support. no no yes. isp support aglp060 aglp125 iglooe agle600 ? no no yes. no isp support. yes. no isp support. no no yes. isp support agle3000 ? proasic3l a3p250l ? no no yes. no isp support. yes. no isp support. no no yes. isp support. a3p600l ? a3p1000l ? a3pe3000l ? proasic3 a3p015 no no yes. no isp support. yes. no isp support. no no yes. isp support. a3p030 a3p060 a3p125 a3p250 ? a3p400 ? a3p600 ? a3p1000 ? proasic3e a3pe600 ? no no yes. no isp support. yes. no isp support. no no yes. isp support. a3pe1500 ? a3pe3000 ? * refer to the "certified programming solu tions" section on page 14-9 for more information on programmer support. programming flash devices v1.1 14-9 certified programming solutions the actel-certified programmers fo r flash devices are flashpro3, flashpro lite, flashpro, silicon sculptor i and ii, and any programmer that is buil t by bp microsystems. all other programmers are considered noncertified programmers. ? flashpro3, flashpro lite, flashpro the actel family of flashpro device progra mmers provides in-system programming in an easy-to-use, compact system that supports a ll proasic families. whether programming a board containing a single device or multiple devices connected in a chain, the actel line of flashpro programmers enable s fast programming and repr ogramming. programming with the flashpro series of programmers saves boar d space and money as it eliminates the need for sockets on the board. there are no built-i n algorithms, so there is no delay between product release and programming support. ? silicon sculptor ii silicon sculptor ii is a robu st, compact, single-d evice programmer with standalone software for the pc. it is designed to enable concurrent programming of multiple units from the same pc with speeds equivalent to or faster than previous actel programmer s. it replaces silicon sculptor i as the actel programmer of choice. ? silicon sculptor i and silicon sculptor 6x actel no longer offers silicon sculptor i or silicon sculptor 6x for sale. both items have been discontinued. actel does support silicon sculptor i and silicon sculptor 6x by continuing to release new software that enables improved programming of previously covered actel devices; new actel devices are only supported on silicon sculptor ii. all software support for silicon sculptor i and silicon sculptor 6x pr ogrammers will be disconnected by the end of 2005; no support for these older programmers will be offered in 2006. actel recommends that all customers upgrade to silicon scul ptor ii or a bp multi-site programmer. ? noncertified programmers actel does not test programmi ng solutions from other vendors, and cannot guarantee programming yield. also, actel will not perform any failure analysis on devices programmed by hardware from other vendors. ? programming centers actel programming hardware policy also applie s to programming centers. actel expects all programming centers to use certified prog rammers to program actel devices. if a programming center uses noncertified pr ogrammers to program actel devices, the " noncertified programmers " policy applies. proasic plus apa075 yes. isp support. yes. isp support. yes. isp support. yes. isp support. yes. isp support. yes. isp support. no apa150 apa300 apa450 apa600 apa750 apa1000 proasic a500k50 yes yes yes yes yes no no a500k130 a500k180 a500k270 table 14-5 ? programmer device su pport (continued) actel family device arm- enabled silicon sculptor silicon sculptor 6x silicon sculptor ii silicon sculptor 3flashpro flashpro lite flashpro3 * refer to the "certified programming solu tions" section on page 14-9 for more information on programmer support. programming flash devices 14-10 v1.1 flash programming guidelines preprogramming setup before programming, several steps are requir ed to ensure an optimal programming yield. use proper handling and electrosta tic discharge (esd) precautions actel fpgas are sensitive electronic devices that are susceptible to damage from esd and other types of mishandling. for more in formation about esd, refer to the actel quality and reliability guide, beginning with page 41. use the latest version of the de signer software to generate your programming file (recommended) the files used to program actel fl ash devices (*.bit, *.stp) contai n important information about the switches that will be programme d in the fpga. find the latest ve rsion and corresponding release notes at http://www.actel.com/download/software/designer/ . also, programming files must always be zipped during file transfer to av oid the possibility of file corruption. use the latest version of the programming software the programming software is frequently updated to accommodate yield enhancements in fpga manufacturing. these updates ensure maximu m programming yield and minimum programming times. before progra mming, always check the ve rsion of software being used to ensure it is the most recent. depending on the programming software, refer to one of the following: ?flashpro: http://www.actel.com/download/program_debug/flashpro/ ? silicon sculptor: http://www.actel.com/download/program_debug/ss/ use the most recent adapter m odule with silicon sculptor occasionally, actel make s modifications to the adapter modules to impr ove programming yields and programming times. to identi fy the latest version of each mo dule before programming, visit http://www.actel.com/products/hardwa re/program_debug/ss/modules.aspx . perform routine hardware self-diagnostic test ?flashpro the self-test is only appl icable when programming wi th flashpro and flashpro3 programmers. it is not supported with flashpro lite. to run the self-diagn ostic test, follow the instructions given in the "performing a self-test" section of http://www.actel.com/documents/flashpro_ug.pdf . ? silicon sculptor the self-diagnostic test verifi es correct operation of the pin drivers, power supply, cpu, memory, and adapter module. this test shou ld be performed before every programming session. at minimum, the te st must be executed every week . to perform self-diagnostic testing using the silicon sculptor software, perform the following steps, depending on the operating system: ? dos: from anywhere in the software, type alt + d . ? windows: click device > choose actel diagnostic > select the te s t tab > click ok . programming flash fpgas programming a flash device is a one-step proces s, whether programming is conducted with a socket adapter module or via isp. the execute func tion will automatically erase the device, program the flash cells, and verify that it is programmed correctly. actel recommend s confirming the security status is correct before programming. the following steps ar e required to program actel flash fpgas. programming flash devices v1.1 14-11 programming with flashpro setup properly connect the flashpro ribbon cable with the programming header an d turn on the switch. actel recommends running the self-test be fore programming any devices; see the "perform routine hardware self-diagno stic test" section on page 14-10 . in the programming software, from the file menu, choose connect . in the flashpro connect to programmer dialog box that appears, select the port to which the fl ashpro programmer is connected, and select the device family. disable voltages from the programmer if they are available on the board. click connect . a successful connect or any erro rs appear in the log window. analyze chain and device selection from the file menu, choose analyze chain . chain details appear in the log window. if any failures appear, refer to the error and troubleshooting section of the flashpro user's guide . select the device to be programmed from the device list. if only one device is present in the chain, performing analyze chain sele cts that device automati cally from the device list. loading the stapl file flashpro3, flashpro lite , and flashpro programmers use a stapl (*.stp) file to program the device. to load the stapl file, fro m the file menu, choose open stapl file , or click the open file button in the toolbar. selecting an action after loading the stapl file, sele ct an action from the action list. see the "programming file actions" section in the flashpro user's guide for a definition of each action. programming the device to program the device, in the action li st, select program . make the required selections and click execute to start programming. the progress of th e programming action displays in the log window. the message "exit 0" indicates that the device has successfully been programmed. note: do not interrupt the programming sequence; it may damage the device or programmer. verify correct programming to verify the device is programmed with the corre ct stapl file, load the stapl file and in the action list and click verify . click execute to start the verification proc ess. a successful verification results in "exit 0." note: verification is also performed in the previous "programming the device" step; clicking verify is an additional standalone option. programming failure allowances flash fpgas are reprogrammable, so actel tests the programmability for 100% of the devices shipped. return material authorization (rma) policies actel consistently strives to exceed customer expe ctations by continuing to improve the quality of our products and our quality management system. actel has rma procedures in place to address programming fallout. customers should be mindful of the following rma policies. all devices submitted for an rma, must be within the actel warranty period of one year from date of shipment. actel will reject rmas for devices that are no longer under warranty. rmas will only be authorized fo r current actel devices. devices th at have been discontinued will not receive rmas. all functional failure analysis requests must be initiated by opening a case with actel technical support. devices returned for fail ure analysis against an rma should be in their original packaging and must have an rma number issued by actel. programming flash devices 14-12 v1.1 contacting the cust omer support group highly skilled engineers staff the cu stomer applications center from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. you can contact the center by one of the following methods: electronic mail you can communicate your technical questions to our email address and receive answers back by email, fax, or phone. also, if you have design pr oblems, you can email your design files to receive assistance. actel monitors the emai l account throughout the day. when sending your request to us, please be sure to incl ude your full name, company name, an d contact information for efficient processing of your request. the technical support email address is tech@actel.com . telephone our technical support hotline answ ers all calls. the center retriev es information, such as your name, company name, telephone nu mber, and question. once this is done, a case number is assigned. then the center forwards the info rmation to a queue wh ere the first available applications engineer receives the data and returns your call. the phone hours are from 7:00 a . m . to 6:00 p . m ., pacific time, monday through friday. the customer applications cent er number is (800) 262-1060. european customers can call +44 (0) 1256 305 600. related documents below is a list of related documents, their loca tion on the actel website, and a brief summary of each document. application notes programming antifuse devices http://www.actel.com/documen ts/antifuseprogram_an.pdf implementation of security in actel's proasic and proasic plus flash-based fpgas http://www.actel.com/documents/flash_security_an.pdf handbook documents security in low-pow er flash devices http://www.actel.com/docum ents/lpd_secu rity_hbs.pdf in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 http://www.actel.com/documents/lpd_isp_hbs.pdf microprocessor programming of actel?s low-power flash devices http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf user?s guides flashpro programmers flashpro3, flashpro lite, and flashpro http://www.actel.com/products/hardware /program_debug/flashpro/default.aspx flashpro user's guide http://www.actel.com/documents/flashpro_ug.pdf the flashpro user?s guide incl udes hardware and software setup, self-test instructions, use instructions, and a troubleshooting / error message guide. programming flash devices v1.1 14-13 silicon sculptor 3 and silicon sculptor ii http://www.actel.com/products/hardwa re/program_debug/ss/default.aspx other documents http://www.actel.com/products/solution s/security/default.aspx#flashlock the security resource center descri bes security in actel flash fpgas. actel quality and reliability guide http://www.actel.com/documents/relguide.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-013-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the "flash devices" section was updated to include the igloo plus family. the text, "voltage switching is required in-system to switch from a 1.2 v core to 1.5 v core for programming" was revised to state, "although the device can operate at 1.2 v core voltage, the devi ce can only be reprogrammed when the core voltage is 1.5 v. voltage switching is required in-system to switch from a 1.2 v supply (v cc , v cci , and v jtag ) to 1.5 v for programming." 14-2 the proasic3l family was added to table 14-5 programmer device support as a separate set of rows rather than combined with proasic3 and proasic3e devices. the igloo plus family wa s included, and agl015 and a3p015 were added. 14-8 v1.1 15-1 security in low-pow er flash devices 15 ? security in low-power flash devices security in programmable logic the need for security on fpga programmable lo gic devices (plds) has never been greater than today. if the contents of the fpga can be read by an external source, the in tellectual property (ip) of the system is vulnerable to unauthorized copying. actel igloo, ? fusion, and proasic ? 3 devices contain state-of-the-art circuitr y to make the flash-based devi ces secure during and after programming. low-power flash devices have a built-in 128-bit advanced encryption standard (aes) decryption core (except for 15 k and 30 k gate devi ces). the decryption core facilitates secure in- system programming (isp) of the fpga core ar ray fabric, the flashrom , and the flash memory blocks (fbs) in fusion devices. the flashr om, flash blocks, and fp ga core fabric can be programmed independently of each other, allowi ng the flashrom or flash blocks to be updated without the need for change to the fpga core fabric. actel has incorporated the aes decryption core into the low- power flash devices and has also included the actel flash-based lock technology, flashlock. ? together, they provide leading-edge security in a programmable logic device. configurat ion data loaded into a device can be decrypted prior to being written to the fpga core using the aes 128-bit block cipher standard. the aes encryption key is stored in on-chip, nonvolatile flash memory. this document outlines th e security features offered in low-pow er flash devices, some applications and uses, as well as the different so ftware settings for each application. figure 15-1 ? overview on security security in low-pow er flash devices 15-2 v1.1 security support in low-power devices the low-power flash families listed in table 15-1 support the security f eature and th e functions described in this document. the family name links to the datasheet for each family. any required timing details are linked from the timing numbers column to the relevant datasheet sections. actel's low-power flash devices (listed in table 15-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 15-1 . where the information applies to only one fa mily or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 15-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 15-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1.2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher density, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fp gas qualified for automotive applications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. security in low-pow er flash devices v1.1 15-3 security architecture igloo, fusion, and proasic3 devices have b een designed with the most comprehensive programming logic design se curity in the industry. in the architec ture of these devices, security has been designed into the very fabric. the flash cells are located beneath seven metal layers, and the use of many device design and layout techniques makes invasive attacks difficult. since device layers cannot be removed withou t disturbing the char ge on the programmed (or erased) flash gates, devices cannot be easily deconstructed to decode the design. low-power flash devices are unique in being reprogrammable and having inhere nt resistance to both in vasive and noninvasive attacks on valuable ip. secure, remote isp is now possible with aes encryp tion capability for the programming file during electronic transfer. figure 15-2 shows a view of th e aes decryption core inside an igloo device; figure 15-3 on page 15-4 shows the aes decryption core inside a fusion device. the aes core is used to decrypt the encrypted programming f ile when programming. note: isp aes decryption is not supported by 15 k and 30 k gate devices. for details of other architecture features by device, refer to the appropriate family datasheet. figure 15-2 ? block representation of th e aes decryption core in igloo and proasic3 devices flash*freeze technology charge pumps user nonvolatile flashrom isp aes decryption* ram block 4,608-bit dual-port sram or fifo block ram block 4,608-bit dual-port sram or fifo block versatile ccc i/os bank 0 bank 3 bank 3 bank 1 bank 1 bank 2 security in low-pow er flash devices 15-4 v1.1 security features igloo and proasic3 devices have two entities in side: flashrom and the fpga core fabric. fusion devices contain three entities: flashrom, fb s, and the fpga core fabric. the parts can be programmed or updated independently with a stapl programming file. the programming files can be aes-encrypted or plaintext. this allows maximum flexibilit y in providing security to the entire device. refer to flashrom in actel?s lo w-power flash devices for information on the flashrom structure. unlike sram-based fpga devices, which require a separate bo ot prom to store programming data, low-power flash devices are nonvolatile, and the secured configuration data is stored in on- chip flash cells that are part of the fpga fabric. once programmed, th is data is an inherent part of the fpga array and does not need to be loaded at system power- up. sram-based fpgas load the configuration bitstream upon power-up; therefore, the configuration is exposed and can be read easily. the built-in fpga core, fb, and flashrom support programming f iles encrypted with the 128-bit aes (fips-192) block ciphers. the aes key is stored in dedicated, on-chip flash memory and can be programmed before the device is shipped to other parties (allowin g secure remote field updates). security in arm-enabled low-power flash devices there are slight differences between the regular flash devices and the arm ? -enabled flash devices, which have the m1 and m7 prefix. the aes key is used by actel and preprogrammed into the device to protect the arm ip. as a result, the design is encrypted along with the arm ip, according to the details below. figure 15-3 ? block representation of the aes decr yption core in a fusion afs600 fpga versatile ccc ccc i/os osc ccc/pll bank 0 bank 4 bank 2 bank 1 bank 3 sram block 4,608-bit dual-port sram or fifo block sram block 4,608-bit dual-port sram or fifo block flash memory blocks flash memory blocks adc analog quad isp aes decryption user nonvolatile flashrom charge pumps analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad analog quad security in low-pow er flash devices v1.1 15-5 coremp7 device security arm7 (m7-enabled) devices are shipped with the following security features: ? fpga array enabled for aes-encryp ted programming and verification ? flashrom enabled for plaintext read and write cortex-m1 device security cortex-m1?enabled devices are shipped wi th the following security features: ? fpga array enabled for aes-encryp ted programming and verification ? flashrom enabled for aes-encrypted write and verify ? fusion embedded flash memory enabled for aes- encrypted write aes encryption of programming files low-power flash devices employ aes as part of th e security mechanism that prevents invasive and noninvasive attacks. the mechanism entails encrypting the pr ogramming file with aes encryption and then passing the programming file through the aes de cryption core, which is embedded in the device. the file is decrypted there, and the devi ce is successfully programmed. the aes master key is stored in on-chip nonvolatile memory (flash). the aes master key can be preloaded into parts in a secure programming environment (such as the actel in-house programming center), and then "blank" parts can be shipped to an untrusted pr ogramming or manufactur ing center for final personalization with an aes-encrypted bitstream. late-stage product changes or personalization can be implemented easily and securely by simply sending a stapl file wi th aes-encrypted data. secure remote field updates over public networks (such as the inte rnet) are possible by sending and programming a stapl file with aes-encrypted data. the aes key protects the programming data for f ile transfer into the device, with 128-bit aes encryption. if aes encryption is used, the aes key is stored or preprogrammed into the device. to program, you must use an aes-en crypted file, and the encryption used on the file must match the encryption key alr eady in the device. the aes key is protected by a flashlock security pas s key that is also impl emented in each device. the aes key is always protected by the flashlock key, and the aes-encrypted file does not contain the flashlock key. this flashlock pass key techno logy is exclusive to the actel flash-based device families. flashlock pass key technology can al so be implemented with out the aes encryption option, providing a choice of different security levels. in essence, security featur es can be categorized into the following three options: ? aes encryption with fl ashlock pass key protection ? flashlock protection only (no aes encryption) ? no protection each of the above options is explained in more detail in the following sections with application examples and software im plementation options. advanced encr yption standard the 128-bit aes standard (fips-192) block cipher is the nist (national insti tute of standards and technology) replacement for des (data encryption standard fips46-2). aes has been designed to protect sensitive government info rmation well into the 21st centur y. it replaces the aging des, which nist adopted in 1977 as a federal information processing standard used by federal agencies to protect sensitive, unclassified inform ation. the 128-bit ae s standard has 3.4 10 38 possible 128-bit key variants, and it has been estimated th at it would take 1,000 trillion years to crack 128-bit aes cipher text using exha ustive techniques. keys are store d (securely) in low-power flash devices in nonvolatile flash memory . all programming files sent to the device can be authenticated by the part prior to programming to ensure that bad programming data is not loaded into the part that may possibly damage it. all programming verifi cation is performed on-chi p, ensuring that the contents of low-power flash devices remain secure. actel has implemented the 128-bit aes (rijndael) algorithm in low-p ower flash devices. with this key size, there are approximately 3.4 10 38 possible 128-bit keys. des has a 56-bit key size, which provides approximately 7.2 10 16 possible keys. in their aes fact sheet, the nati onal institute of security in low-pow er flash devices 15-6 v1.1 standards and technology uses the following hypo thetical example to illustrate the theoretical security provided by aes. if one were to assume that a computing system ex isted that could recover a des key in a second, it would take that same ma chine approximately 149 trillion years to crack a 128-bit aes key. nist continues to make their point by stating the universe is believed to be less than 20 billion years old. 1 the aes key is securely stored on-chip in dedi cated low-power flash device flash memory and cannot be read out. in the first step, the aes key is generated and programmed into the device (for example, at a secure or trusted programming site). the actel designer soft ware tool provides aes key generation capability. after the key has been programmed into the device, the device will only correctly decrypt programming files that have been encrypted with the same key. if the individual programming file content is incorrect, a messag e authentication contro l (mac) mechanism inside the device will fail in authenti cating the programming file. in other words, when an encrypted programming file is being loaded into a device that has a different programmed aes key, the mac will prevent this incorrect data from being lo aded, preventing possible device damage. see figure 15-3 on page 15-4 and figure 15-4 on page 15-7 for graphical repr esentations of this process. it is important to note that the user decides what level of protec tion will be implemented for the device. when aes protection is desired, the fl ashlock pass key must be set. the aes key is a content protection mechanism, whereas the flashl ock pass key is a device protection mechanism. when the aes key is programmed into the device, th e device still needs the pass key to protect the fpga and flashrom contents and the security setti ngs, including the aes key. using the flashlock pass key prevents modification of the design contents by means of simply programming the device with a different aes key. aes decryption and mac authentication low-power flash devices have a built-in 128-bit aes decryption core, whic h decrypts the encrypted programming file and performs a mac check that authenticates the file prior to programming. mac authenticates the entire pr ogramming data stream. after aes decryption, the mac checks the data to make sure it is valid programming data for the device. this can be done while the device is still operating. if th e mac validates the file, the device will be erased and programmed. if the mac fails to validate, th en the device will continue to operate uninterrupted. this will ensure the following: ? correct decryption of th e encrypted programming file ? prevention of erroneous or corrupted data being programmed during the programming file transfer ? correct bitstream passed to the device for decryption 1. national institute of standards and technology, ?advanced encryption standard (aes) questions and answers,? 28 january 2002, < http://csrc.nist.gov/cryptotoolkit/aes/aesfact.html > (10 january 2005). security in low-pow er flash devices v1.1 15-7 flashlock additional options for iglo o and proasic3 devices the user also has the option of prohibiting write operations to the fpga array but allowing verify operations on the fpga array and/or read oper ations on the flashrom without the use of the flashlock pass key. this option provides the user the freedom of verifying the fpga array and/or reading the flashrom contents after the device is programmed, without having to provide the flashlock pass key. the user can incorporate aes encryption on the prog ramming files to better enhance the level of security used. figure 15-4 ? example application scen ario using aes in igloo and proasic3 devices figure 15-5 ? example application scenario using aes in fusion devices actel designer software programming file generation with aes encryption igloo and proasic3 decrypted bitstream mac validation aes decryptioncore transmit medium / public network encrypted bistream flashrom aes key fpga core actel designer software programming file generation with aes encryption fusion decrypted bitstream mac validation aes decryptioncore transmit medium / public network encrypted bistream flashrom aes key fpga core fbs security in low-pow er flash devices 15-8 v1.1 permanent security setting options in applications where a permanent lock is not desired, yet the security settings should not be modifiable, igloo and proasic3 device s can accommodate th is requirement. this application is partic ularly useful in cases where a device is located at a remote location and must be reprogrammed with a design or data update. refer to the "application 3: nontrusted environment?field updates/upgrades" section on page 15-10 for further discus sion and examples of how this can be achieved. the user must be careful when considering the permanent flashlock or permanent security settings option. once the design is programmed wi th the permanent settings, it is not possible to reconfigure the security settings already employed on the device . therefore, exercise careful consideration before prog ramming permanent settings. permanent flashlock the purpose of the permanent lock feature is to provide the benefits of the highest level of security to igloo and proasic3 devices. if sele cted, the permanent flashlock feature will create a permanent barrier, preventing an y access to the contents of th e device. this is achieved by permanently disabling write and ve rify access to the array, and write and read access to the flashrom. after permanently lock ing the device, it has been ef fectively rendered one-time- programmable. this feature is usef ul if the intended applications do not require design or system updates to the device. security in low-pow er flash devices v1.1 15-9 security in action this section illustrates some applications of the security advantages of actel?s devices ( figure 15-6 ). application 1: trusted environment as illustrated in figure 15-7 on page 15-10 , this application allows th e programming of devices at design locations where research and developmen t take place. therefore, encryption is not necessary and is optional to the user. this is of ten a secure way to prot ect the design, since the design program files are not sent elsewhere. in situations where production programming is not available at the design location, programming centers (suc h as actel in-house programming) provide a way of programming designs at an al ternative, secure, and trusted location. in this scenario, the user generates a st apl programming file from the de signer software in plaintext format, containing information on the entire design or the portion of the design to be programmed. the user can choose to employ the flashlock pass key feature with the design. once the design is programmed to unprogrammed devices, the design is protected by this flashlock pass key. if no future programming is needed, the us er can consider permanen tly securing the igloo and proasic3 device, as discussed in the "permanent flashlock" section on page 15-8 . application 2: nontrusted en vironment?unsecured location often, programming of devices is not performe d in the same location as actual design implementation, to redu ce manufacturing cost. overseas programming centers and contract manufacturers are examples of this scenario. to achieve security in this case, the aes key and the flashlock pass key can be initially programmed in-house (trusted environment). this is done by generating a programming file with only the security settings and no design contents. the de sign fpga core, flashrom, and (for fusion) fb contents are generated in a separate programming file. this programming fi le must be set with the same aes key that was used to prog ram to the device previously so the device will correctly decrypt this encrypted programming file. as a result, th e encrypted design content programming file can note: flash blocks are only used in fusion devices. figure 15-6 ? security options plaintext source file aes encryption cipher text source file public domain aes decryption core flashrom flash blocks flash device application 3 application 2 application 1 fpga core security in low-pow er flash devices 15-10 v1.1 be safely sent off-site to nontrusted pr ogramming locations for design programming. figure 15-7 shows a more detailed fl ow for this application. application 3: nontrusted environment?field updates/upgrades programming or reprogramming of devices may occur at remote locations. reconfiguration of devices in consumer products/equipment through public networks is one example. typically, the remote system is already programmed with particul ar design contents. when design update (fpga array contents update) and/or data upgrade (fla shrom and/or fb contents upgrade) is necessary, an updated programming file with aes encryption can be generated, sent across public networks, and transmitted to the remote system. reprogramm ing can then be done using this aes-encrypted programming file, providing easy and secure field upgrades. low-power flash devices support this secure isp using aes. the detailed flow for this application is shown in figure 15-8 on page 15-11 . refer to microprocessor programming of actel?s low-power flash devices for more information. to prepare devices for this scenar io, the user can initially genera te a programming file with the available security setting options. this programming file is programmed into the devices before shipment. during the prog ramming file generation step, the user has the option of making the security settings permanent or not. in situatio ns where no changes to the security settings are necessary, the user can select this feature in the software to generate the programming file with permanent security settings. actel recommends th at the programming file use encryption with an aes key, especially when isp is done via public domain. for example, if the designer wants to use an aes key for the fpga array and the flashrom, permanent needs to be chosen for this setting. at fi rst, the user would do this by choosing the options to use an aes key for the fpga array and the fl ashrom, and then choosing permanently lock the security settings . a unique aes key would be chosen. once this programming file is notes: 1. programmed portion indi cated with dark gray. 2. programming of fbs applies to fusion only figure 15-7 ? application 2: device programmin g in a nontrusted environment trusted environment nontrusted manufacturing environment flash device aes and/or pass key protected programming file fpga/flashrom/fbs contents security settings generates design contents encrypted with aes generates and programs security settings only (programming of the security keys) programs design contents to devices ships devices to manufacturer sends file(s) to manufacturer oem customers returns programmed devices to vendor ships programmed devices to end customer flash device flash device oem fpga/flashrom/fbs security settings* fpga/flashrom/fbs security settings security in low-pow er flash devices v1.1 15-11 generated and programmed to the devices, the aes key is permanently stored in the on-chip memory, where it is secured safely. the devices wo uld be sent to distant locations for the intended application. wh en an update is needed, a new progra mming file must be generated. the programming file must use the same aes key for encryption; othe rwise, the authenti cation will fail and the file will not get programmed in the device. flashrom security use models each of the subsequent sections describes in detail the available selections in actel designer as an aid to understanding security ap plications and generating appropriate programming files for those applications. before proceeding, it is helpful to review figure 15-7 on page 15-10 , which gives a general overview of the programming file generati on flow within the desi gner software as well as what occurs during the device programming stage. specific settings are discussed in the following sections. in figure 15-7 on page 15-10 , the flow consists of two sub- flows. sub-flow 1 describes programming security settings to the device only, and sub-flow 2 describes programming the design contents only. in application 1, described in the "application 1: trusted environment" section on page 15-9 , the user does not need to generate separate files but can generate one programming file containing both security settings and design contents. then programming of the secu rity settings and design contents is done in one step. both sub-flow 1 and sub-flow 2 are used. in application 2, described in the "application 2: nontrusted envi ronment?unsecured location" section on page 15-9 , the trusted site should follow sub-fl ows 1 and 2 separately to generate two separate programming files. the programming file from sub-flow 1 will be used at the trusted site to program the device(s) first. the programming fi le from sub-flow 2 will be sent off-site for production programming. figure 15-8 ? application 3: nontrust ed environment?field updates/upgrades remote environment / system trusted environment generates updated design contents encrypted with aes original design contents aes encrypted and flashlock pass key protected oem aes encrypted programming file transmits to remote system update/upgrade flash device security in low-pow er flash devices 15-12 v1.1 in application 3, described in the "application 3: nontrusted environment?field updates/upgrades" section on page 15-10 , typically only sub-flow 2 will be used because only updates to the design content portion are needed and no security settings need to be changed. in the event that update of the se curity settings is necessary, see the "reprogramming devices" section on page 15-21 for details. for more information on programming low-power flash devices, refer to in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 note: if programming the security header only, just perform sub-flow 1. if programming design content on ly, just perform sub-flow 2. figure 15-9 ? security programming flows software generates programming file with desired security settings: ? encrypted with aes and protected with flashlock pass key ? protected with flashlock pass key only program design contents program security settings user 1 2 designer software programming software programming previously secured device(s)? yes no no software generates programming file with desired design contents (fpga array, flashrom, fb, or all) yes no device previously programmed? software performs comparison of flashlock pass key between programming file and device software performs comparison of flashlock pass key between programming file and device encrypted design content passes through mac for authentication software programs selected security settings into device no does flashlock pass key match? does flashlock pass key match? yes no returns error returns error yes correct? yes no aes key used previously? yes user assigns desired security settings to fpga/flashrom/fb/all: ? aes key and flashlock pass key ? flashlock pass key only user must reassign exact flashlock pass key previously programmed into the device user must reassign exact aes key previously programmed into the device software generates programming file with flashlock pass key and design contents design content programmed into device software generates programming file with encrypted design contents design content decrypted and programmed into device security in low-pow er flash devices v1.1 15-13 generating programming files generation of the programming file in a trusted environment? application 1 as discussed in the "application 1: trusted environment" section on page 15-9 , in a trusted environment, the user can choose to program the device with pl aintext bitstream content. it is possible to use plaintext for programming even when the flashlock pass key option has been selected. in this application, it is not necessary to employ ae s encryption prot ection. for aes encryption settin gs, refer to the next sections. the generated programming file w ill include the security setting (if selected) and the plaintext programming file content for the fpga array, flas hrom, and/or fb. these options are indicated in table 15-2 and table 15-3 . for this scenario, generate th e programming file as follows: 1. select the silicon features to be programmed (security settings, fpga array, flashrom, flash memory block), as shown in figure 15-10 on page 15-14 and figure 15-11 on page 15-14 . click next . if security settings is selected (i.e., the flashlock secu rity pass key feature), an additional dialog will be displayed to prompt you to se lect the security level setting. if no security setting is selected, you wi ll be directed to step 3. table 15-2 ? igloo and proasic3 plaintext security options, no aes security protection flashrom only fpga core only both flashrom and fpga no aes / no flashlock ??? flashlock only ??? aes and flashlock ? ? ? table 15-3 ? fusion plaintext security options security protection flashrom only fpga core only fb core only all no aes / no flashlock ???? flashlock ???? aes and flashlock ? ? ? ? note: for all instructions, the programming of flash blocks refers to fusion only. security in low-pow er flash devices 15-14 v1.1 figure 15-10 ? all silicon features checked fo r igloo and proasic3 devices figure 15-11 ? all silicon features checked for fusion security in low-pow er flash devices v1.1 15-15 2. choose the appropriate security level setting and enter a flas hlock pass key. the default is the medium security level ( figure 15-12 ). click next . if you want to select different options for the fpga and/or flashrom, this can be set by clicking custom level . refer to the "advanced options" section on page 15-22 for different custom security level options and descriptions of each. figure 15-12 ? medium security level selected for low-power flash devices security in low-pow er flash devices 15-16 v1.1 3. choose the desired settings for the flashrom configurations to be programmed ( figure 15-13 ). click finish to generate the stapl prog ramming file fo r the design. generation of security head er programming file only? application 2 as mentioned in the "application 2: nontrusted environm ent?unsecured location" section on page 15-9 , the designer may employ flashlock pass key protection or flashl ock pass key with aes encryption on the device before sending it to a nontrusted or unsecured location for device programming. to achieve this, th e user needs to generate a programming file containing only the security settings desired (secur ity header programming file). note: if aes encryption is configured, flashlock pa ss key protection must also be configured. the available security op tions are indicated in table 15-4 and table 15-5 on page 15-17 . figure 15-13 ? flashrom configuration setting s for low-power flash devices table 15-4 ? flashlock security option s for igloo and proasic3 security option flashrom only fpga core only both flashrom and fpga no aes / no flashlock ? ? ? flashlock only ??? aes and flashlock ??? security in low-pow er flash devices v1.1 15-17 for this scenario, generate th e programming file as follows: 1. select only the security settings option, as indicated in figure 15-14 and figure 15-15 on page 15-18 . click next . table 15-5 ? flashlock security options for fusion security option flashrom only fpga core only fb core only all no aes / no flashlock ? ? ? ? flashlock ???? aes and flashlock ???? figure 15-14 ? programming igloo and proasi c3 security settings only security in low-pow er flash devices 15-18 v1.1 2. choose the desired se curity level se tting and enter the key(s). ?the high security level employs flashlock pass key with aes key protection. ?the medium security level employs flashl ock pass key protection only. figure 15-15 ? programming fusion se curity settings only figure 15-16 ? high security level to implement flas hlock pass key and aes key protection security in low-pow er flash devices v1.1 15-19 table 15-6 and table 15-7 show all available options. if you want to implement custom levels, refer to the "advanced options" section on page 15-22 for information on each option and how to set it. 3. when done, click finish to generate the security header programming file. generation of programming f iles with aes encryption? application 3 this section discusses how to ge nerate design content programming files needed specifically at unsecured or remote locations to program devices with a security header (flashlock pass key and aes key) already programmed ( "application 2: nontrusted en vironment?unsecured location" section on page 15-9 and "application 3: nontrusted envi ronment?field updates/upgrades" section on page 15-10 ). in this case, the encrypted programm ing file must correspond to the aes key already programmed into the device. if aes encr yption was previously se lected to encrypt the flashrom, fb, and fpga array, aes encryption mu st be set when generati ng the programming file for them. aes encryption can be applied to the flashrom only, the fb only, the fpga array only, or all. the user must ensure both the flashloc k pass key and the aes key match those already programmed to the device(s), and all securi ty settings must matc h what was previously programmed. otherwise, the encryption and/or device unlocking will not be recognized when attempting to program the devi ce with the programming file. the generated programming fi le will be aes-encrypted. in this scenario, generate th e programming file as follows: 1. deselect the security settings and select the portion of the device to be programmed ( figure 15-17 on page 15-20 ). select programming previously secured device(s ). click next . table 15-6 ? all igloo and proasic3 head er file security options security option flashrom only fpga core only both flashrom and fpga no aes / no flashlock ??? flashlock only ??? aes and flashlock ??? note: ? = options that may be used table 15-7 ? all fusion header fi le security options security option flashrom only fpga core only fb core only all no aes / no flashlock ???? flashlock ???? aes and flashlock ???? security in low-pow er flash devices 15-20 v1.1 choose the high security level to reprogram devices usin g both the flashlock pass key and aes key protection ( figure 15-18 on page 15-21 ). enter the aes key and click next . a device that has already been secured with fl ashlock and has an aes key loaded must recognize the aes key to program the device and generate a valid bitstream in authen tication. the flashlock key is only required to unlock the device and change the security settings. this is what makes it possible to program in an untrusted environm ent. the aes key is protected inside the device by the flashlock key, so you ca n only program if you have the correct aes key. in fact, the aes key is not in the programming file eith er. it is the key used to encrypt the data in the file. the same key previously programmed with the flashlock key matche s to decrypt the file. if you had an aes-encrypted file programmed to a device without flashlock, this would not be secure, since without flashlock to protect the aes key, you could simply reprogram the aes key first, then program with any aes key you wanted or no aes key at all. this option is therefore not available in the software. note: the settings in this figure are used to show the ge neration of an aes-encrypted programming file for the fpga array, flashrom, and fb contents. one or all locations may be selected for encryption. figure 15-17 ? settings to program a device secured wi th flashlock and using aes encryption security in low-pow er flash devices v1.1 15-21 programming with this file is intended for an unsecured enviro nment. the aes key encrypts the programming file with the same aes key already us ed in the device and utilizes it to program the device. reprogramming devices previously programmed devices can be reprogrammed using the steps in the "generation of the programming file in a trusted environm ent?application 1" section on page 15-13 and "generation of security header programming file only?application 2" section on page 15-16 . in the case where a flashlock pass key has been pr ogrammed previously, the user must generate the new programming file with a flashlock pass key that matches the one previously programmed into the device. the software will ch eck the flashlock pass key in th e programming file against the flashlock pass key in the device. the keys must match before the device can be unlocked to perform further progra mming with the new programming file. figure 15-10 on page 15-14 and figure 15-11 on page 15-14 show the option programming previously secured device(s) , which the user should select befo re proceeding. upon going to the next step, the user will be notifi ed that the same flashlock pass key needs to be entered, as shown in figure 15-19 on page 15-22 . figure 15-18 ? security level set high to re program device with aes key security in low-pow er flash devices 15-22 v1.1 it is important to note that when the security se ttings need to be update d, the user also needs to select the security settings check box in step 1, as shown in figure 15-10 on page 15-14 and figure 15-11 on page 15-14 , to modify the security settings. the user must consid er the following: ? if only a new aes key is necessary, the user must re-enter the same pass key previously programmed into the device in designer and then generate a programming file with the same pass key and a different aes key. this en sures the programming file can be used to access and program the device and the new aes key. ? if a new pass key is necessary, the user can generate a new programming file with a new pass key (with the same or a new aes key if desired). however, for programming, the user must first load the orig inal programming file with the pass key that was previously used to unlock the device. then the ne w programming file can be used to program the new security settings. advanced options as mentioned, there may be app lications where more complicated security setting s are required. the ?custom security levels? section in the flashpoint user's guide describes different advanced options available to aid the user in obta ining the best availabl e security settings. figure 15-19 ? flashlock pass key, previously programmed devices security in low-pow er flash devices v1.1 15-23 programming file header definition in each stapl programming file generated, ther e will be information ab out how the aes key and flashlock pass key are configured. table 15-8 shows the header definitions in stapl programming files for different security levels. example file headers stapl files generated with flashlock key and aes key contain key information ? flashlock key / aes ke y indicated in stapl file header definition ? intended only for secu red/trusted environment programming applications ============================================= note "creator" "designer version: 6.1.1.108"; note "device" "a3pe600"; note "package" "208 pqfp"; note "date" "2005/04/08"; note "stapl_version" "jesd71"; note "idcode" "$123261cf"; note "design" "counter32"; note "checksum" "$edb9"; note "save_data" "fromstream"; note "security" "keyed encrypt "; note "alg_version" "1"; note "max_freq" "20000000"; note "silsig" "$00000000"; note "pass_key" "$00123456789012345678901234567890"; note "aes_key" "$abcdefabcdefabcdefabcdefabcdefab"; ============================================== table 15-8 ? stapl programming fi le header definitions by security level security level stapl f ile header definition no security (no flashlock pass key or aes key) note "security" "disable"; flashlock pass key with no aes key note "security" "keyed "; flashlock pass ke y with aes key note "security" "keyed encrypt "; permanent security settings option enabled note "security" "permlock encrypt "; aes-encrypted fpga array (f or programming updates) note "security" "encrypt core "; aes-encrypted flashrom (for programming updates) note "security" "encrypt from "; aes-encrypted fpga array and flashrom (for programming updates) note "security" "encrypt from core "; security in low-pow er flash devices 15-24 v1.1 stapl file with aes encryption ? does not contain aes key / flashlock key information ? intended for transmission through web or serv ice to unsecured locations for programming ============================================= note "creator" "designer version: 6.1.1.108"; note "device" "a3pe600"; note "package" "208 pqfp"; note "date" "2005/04/08"; note "stapl_version" "jesd71"; note "idcode" "$123261cf"; note "design" "counter32"; note "checksum" "$ef57"; note "save_data" "fromstream"; note "security" "encrypt from core "; note "alg_version" "1"; note "max_freq" "20000000"; note "silsig" "$00000000"; conclusion the new and enhanced security features offered in actel igloo, fusion, and proasic3 devices provide state-of-the-art security to designs programmed into thes e flash-based devices. actel low- power flash devices employ the encryption standard used by nist and the u.s. government?aes using the 128-bit rijndael algorithm. the combination of an on-chip ae s decryption engine and actel fl ashlock technology provides the highest level of security against invasive attack s and design theft, impl ementing the most robust and secure isp solution. these security features protect ip within the fp ga and protect the system from cloning, wholesale ?black box? copying of a de sign, invasive attacks, and explicit ip or data theft. glossary term explanation security header programming file programming file used to program the flashlock pass ke y and/or aes key into the device to secure the fpga , flashrom, and/or fbs. aes (encryption) key 128-bit key defined by the user wh en the aes encryption option is set in the actel designer software when genera ting the programming file. flashlock pass key 128-bit key defined by the user when the flashlock option is set in the actel designer software when generating the programming file. the flashlock key protects the security se ttings programmed to the device. once a device is programmed with flashlock, whatever settings were chosen at that time are secure. flashlock the combined security features that protect the device content from attacks. these features are the following: ? flash technology that does not require an external bitstream to program the device ? flashlock pass key that secures device co ntent by locking the security settings and preventing access to the device as defined by the user ? aes key that allows secure, encrypted device reprogrammability security in low-pow er flash devices v1.1 15-25 references national institute of standards and techno logy. ?advanced encryption standard (aes) questions and answers.? 28 january 2002. < http://csrc.nist.go v/cryptotoolkit/aes/aesfact.html > (10 january 2005). related documents handbook documents flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf programming proasic3/e using a microprocessor http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 http://www.actel.com/documents/lpd_isp_hbs.pdf user?s guides flashpoint user's guide\ http://www.actel.com/documents/flashpoint_ug.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information. part number 51700094-014-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 15-2 v1.1 16-1 in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 16 ? in-system programming (isp) of actel?s low- power flash devices using flashpro3 introduction actel's low-power flash devices are all in-syste m programmable. this do cument describes the general requirements for programming a device and specific requirem ents for the flashpro3 programmer. igloo, ? fusion, and proasic ? 3 devices offer a low-power, single -chip, live-at-power-up solution with the asic advantages of security and low unit cost through nonvolatile flash technology. each device contains 1 kbit of on-chip, user-accessible, nonvolatile flashrom. the flashrom can be used in diverse system applications such as internet protocol (ip) addressing, user system preference storage, device serialization, or subscription-based business mo dels. fusion, igloo, and proasic3 devices offer the best in-system prog ramming (isp) solu tion, flashlock ? security features, and aes- decryption-based isp. isp architecture low-power flash devices support is p via jtag and require a single v pump voltage of 3.3 v during programming. in addition, programming via a microc ontroller in a target sy stem is also supported. refer to microprocessor programming of actel?s low-power flash devices . family-specific support: ? fusion, proasic3, and proasic3e devices support isp. ? proasic3l devices operate using a 1.2 v core voltage and support isp at 1.5 v only. voltage switching is required in-system to switch from a 1.2 v core to 1.5 v core for programming. ? igloo and iglooe v5 devices can be progra mmed in-system when the device is using a 1.5 v supply voltage to the fpga core. igloo, igloo plus, and iglooe v2 devices can oper ate using either a 1.2 v core voltage or a 1.5 v core voltage. although the devi ce can operate at 1.2 v core vo ltage, the device can only be reprogrammed when all supplies (v cc , v cci , and v jtag ) are at 1.5 v. voltage switching is required in-system to switch from a 1.2 v co re to 1.5 v core for programming. igloo devices cannot be programmed in-system when the device is in flash*freeze mode. the device should exit flash*freeze mode and be in normal operation for programming to start. programming operations in igloo devices can be ac hieved when the device is in normal operating mode and a 1.5 v core voltage is used. jtag 1532 igloo and proasic3 devices support the jtag-based ieee 1532 standard for isp. to start jtag operations, the igloo device shou ld exit flash*freeze? mode an d be in normal operation before starting to send jtag commands to the device. as part of this support, when a device is in an unprogrammed state, all user i/o pins are disabled . this is achieved by keeping the global io_en signal deactivated, which also has the effect of disabling the input buffers. th e sample/preload instruction captures the status of pads in parallel and shifts them ou t as new data is shifted in for loading into the boundary scan register (bsr). wh en the device is in an unprogrammed state, the sample/preload instruction has no effect on i/o st atus; however, it will co ntinue to shift in new data to be loaded into the bsr. therefore, when sample/preload is used on an unprogrammed device, the bsr will be loaded with undefined da ta. for jtag timing inform ation on setup, hold, and fall times, refer to the flashpro user?s guide . in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 16-2 v1.1 isp support in low-power devices the low-power flash families listed in table 16-1 support the isp feat ure and the functions described in this document. actel's low-power flash devices (listed in table 16-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 16-1 . where the information applies to only one fa mily or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 16-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 16-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1.2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher density, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fp gas qualified for automotive applications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.1 16-3 programming voltage (v pump ) and v jtag low-power flash devices support on-chip charge pu mps, and therefore require only a single 3.3 v programming voltage for the v pump pin during programming. when the device is not being programmed, the v pump pin can be left floating or can be ti ed (pulled up) to any voltage between 0 v and 3.6 v. during programming, the target board or the flashpro3 programmer can provide v pump . flashpro3 is capable of supplying v pump to a single device. if more than one device is to be programmed using flashpro3 on a given board, flashpro3 should not be relied on to supply the v pump voltage. low-power flash device i/os support a bank-based, voltage-supply ar chitecture that simultaneously supports multiple i/o voltage standards ( table 16-2 on page 16-3 ). by isolating the jtag power supply in a separate bank from the user i/os, lo w-power flash devices prov ide greater flexibility with supply selection and simpli fy power supply and printed circuit board (pcb) design. the jtag pins can be run at any voltage fro m 1.5 v to 3.3 v (nominal). acte l recommends that tck be tied to gnd or v jtag when not used. this preven ts a possible totemp ole current on the input buffer stage. for tdi, tms, and trst pins, the devi ces provide an internal nominal 10 k pull-up resistor. during programming, all i/o pins, except for jtag inte rface pins, are tristated and weakly pulled up to v cci . this isolates the part and prevents the sign als from floating. the jtag interface pins are driven by the flashpro3 during programming, including the trst pin, which is driven high. ieee 1532 (jtag) interface the supported industry-standard ieee 1532 prog ramming interface buil ds on the ieee 1149.1 (jtag) standard. ieee 1532 defines the standardized process and methodology for isp. both silicon and software issues are addre ssed in ieee 1532 to create a si mplified isp environment. any ieee 1532?compliant programmer can be used to program low-power flash devices. however, only limited security and flashrom fe atures are supported when usin g the ieee 1532 standard. the actel flashpro3 programmer was de veloped exclusively for these de vices and will support all the security and device serialization features. refer to the standard for detail ed information about ieee 1532. security unlike sram-based fpgas that require loading at power-up from an extern al source such as a microcontroller or boot prom, actel nonvolatile devices are live at power-up, and there is no bitstream required to load the device when power is applied. the unique flash-based architecture prevents reverse engineer ing of the programmed code on the device, because the programmed data is stored in nonvolatile memory cells. each nonvolatile memory cell is made up of small capacitors and any physical deconstruction of th e device will disrupt sto red electrical charges. each low-power flash device has a built-in 128-bit advanced encryption st andard (aes) decryption core, except for the 15 k and 30 k gate devices. any fpga core or flashr om content loaded into the device can optionally be sent as encrypted bitstream and decrypted as it is loaded. this is table 16-2 ? power supplies power supply programming mode current during programming v cc 1.5 v < 70 ma v cci 1.5 v / 1.8 v / 2.5 v / 3.3 v (bank-selectable) i/os are weakly pulled up. v jtag 1.5 v / 1.8 v / 2.5 v / 3.3 v < 20 ma v pump 3.0 v to 3.6 v < 80 ma note: all supply voltages should be at 1.5 v or hi gher, regardless of the setting during normal operation. in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 16-4 v1.1 particularly suitable for applicatio ns where device updates must be transmitted over an unsecured network such as the internet. th e embedded aes decryption core can prevent sensitive data from being intercepted ( figure 16-1 on page 16-4 ). a single 128-bit aes key (32 hex characters) is used to encrypt fpga core programming data and/or flashr om programming data in the actel tools. the low-power flash devices also decrypt with a single 128-bit aes key. in addition, low-power flash devices support a message authentication code (mac) for authentication of the encrypted bitstream on-chip. this allows the encrypted bitstream to be au thenticated and pr events erroneous data from being programmed into the device. the fpga core, flas hrom, and flash memory blocks (fbs), in fusion only, can be updated independentl y using a programming file that is aes-encrypted (cipher text) or uses plain text. security in arm-enabled low-power flash devices there are slight differences between the regular flash device and the arm ? -enabled flash devices, which have the m1 and m7 prefix. the aes key is used by actel and pre-programmed into the device to protect the arm ip. as a result, the design will be encrypted along with the arm ip, according to the details below. coremp7 device security arm7? (m7-enabled) devices are shipped with the following security features: ? fpga array enabled for aes encryp ted programming and verification ? flashrom enabled for plaintext read and write cortex-m1 device security cortex-m1?enabled devices are shipped wi th the following security features: ? fpga array enabled for aes-encryp ted programming and verification ? flashrom enabled for aes-encrypted write and verify fusion embedded flash memory en abled for aes encrypted write. figure 16-2 on page 16-5 shows different applicat ions for isp programming. figure 16-1 ? aes-128 security features actel designer software programming file generation with aes encryption flash device decrypted bitstream mac validation aes decryption fpga core, flashrom, fbs transmit medium / public network encrypted bistream user encryption aes key in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.1 16-5 1. in a trusted programming environment, you can program the device using the unencrypted (plaintext) programming file. 2. you can program the aes key in a trusted pr ogramming environment and finish the final programming in an untrusted environment using the aes-encrypted (cipher text) programming file. 3. for the remote isp updating/reprogramming, th e aes key stored in the device enables the encrypted programming bitstream to be tra nsmitted through the untrusted network connection. actel low-power flash devices also provide the uniq ue actel flashlock feature, which protects the pass key and aes key. unless the original flashloc k pass key is used to unlock the device, security settings cannot be modified. low-power flash devices do not su pport read-back of fpga core- programmed data; however, the flashrom contents can selectively be read back (or disabled) via the jtag port based on th e security settings established by the actel designer software. refer to security in low-pow er flash devices for more information. flashrom and programming files each low-power flash device has 1 kbit of on-chip, nonvolatile flash memory that can be accessed from the fpga core. this nonvolatile flashrom is arranged in eight pages of 128 bits ( figure 16-3 ). each page can be programmed independently, wi th or without the 128-bi t aes encryption. the flashrom can only be programmed via the ieee 1532 jtag port and cannot be programmed from the fpga core. in addition, during programming of the flashrom, the fpga core is powered down automatically by the on-chi p programming control logic. using flashrom combined with aes, many subscription-based applic ations or device serialization applications are po ssible. smartgen supports easy manage ment of the flashrom contents even over large numbers of devices. smartgen ca n support flashrom cont ents that contain the following: ?static values figure 16-2 ? different isp use models source plain text aes encryption source encrypted bitstream tcp/ip flashrom aes decryption fpga core igloo or proasic3 device option 1 option 2 option 3 in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 16-6 v1.1 ? random numbers ? values read from a file ? independent updates of each page in addition, auto-incrementing of fields is poss ible. in applications where the flashrom content is different for each device, you have the option to generate a single stapl file for all the devices or individual serializatio n files for each device. for more in formation on how to generate the flashrom content for device serialization, refer to flashrom in actel?s lo w-power flas h devices . actel libero ? integrated designed envi ronment (ide) includes a un ique tool to support the generation and management of flashrom and fpga programming files. this tool is called flashpoint. depending on the applications, designers can use th e flashpoint software to generate a stapl file with different contents. in each ca se, optional aes encryption and/or different security settings can be set. in designer, when you click the programming file icon, flashpoint launches, and you can generate stapl file(s) with four different cases ( figure 16-4 on page 16-7 ). when the serial ization feature is used during the configuration of flashrom in smartgen, you can generate a single stapl file that will program all the devices or an individual stapl file for each device. the following cases present the fp ga core and flashrom programming file combinations that can be used for different applications. in each case, yo u can set the optional se curity settings (flashlock pass key and/or aes key) depending on the application. 1. a single stapl file or multiple stapl file s with multiple flashr om contents and the fpga core content. a single stapl file will be gene rated if the device seri alization feature is not used. you can program the whole flashrom or selectively program individual pages. 2. a single stapl file for the fpga core content 3. a single stapl file or multiple stapl files wi th multiple flashrom contents. a single stapl file will be generated if the device serializ ation feature is not used. you can program the whole flashrom or selectivel y program individual pages. 4. a single stapl file to config ure the security settings for th e device, such as the aes key and/or pass key. figure 16-3 ? flashrom architecture 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 byte number in page page number in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.1 16-7 programming solution for device programming, any ieee 1532?complian t programmer can be used; however, the flashpro3 programmer must be used to control the low-power flash device's rich security features and flashrom programming options. the flas hpro3 programmer is a low-cost portable programmer for the actel flash families. it can al so be used with a powered usb hub for parallel programming. general specif ications for the flashpro3 programmer are as follows: ? programming clock ? tck is used with a ma ximum frequency of 20 mhz, and the default frequency is 4 mhz. ? programming file ? stapl ? daisy chain ? supported. you can use the chainbuilder software to build the programming file for the chain. ? parallel programming ? supported. multiple flashpro3 programmers can be connected together using a powered usb hub or through the multiple usb ports on the pc. ? power supply ? the target board must provide v cc , v cci , v pump , and v jtag during programming. however, if there is only on e device on the target board, the flashpro3 programmer can generate the required v pump voltage from the usb port. figure 16-4 ? flexible programming file genera tion for different applications actel's designer software suite fpga core content single/multiple flashrom content(s) flashrom configuration file (*.ufc) smartgen fpga core content security settings single/multiple flashrom content(s) programming file (flashpoint) netlist security settings security settings security settings 1234 in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 16-8 v1.1 isp programming header information the flashpro3 programming cabl e connector can be connected with a 10-pin, 0.1"-pitch programming header. the recommended programming headers are manufactured by amp (103310-1) and 3m (2510-6002ub). if you have limited board space, you can use a compact programming header manufactured by samtec (ftsh-105-01-l-d-k). using this compact programming header, you are required to order an additional header adapter manufactured by actel (fp3-26pin-adapter). existing proasic plus family customers who are using the sa mtec small programming header (ftsh- 113-01-l-d-k) and are planning to migrate to igloo or proasic3 devices can order a separate adapter kit from actel (fp3-10pin -adapter-kit), which contains a compact 10-pin adapter kit as well as 26-pin migration capability . table 16-3 ? programming header ordering code manufacturer part nu mber description amp 103310-1 10-pin, 0.1"-pitch cabl e header (right-angle pcb mount angle) 3m 2510-6002ub 10-pin, 0.1"-pitch ca ble header (straight pcb mount angle) samtec ftsh-113-01-l-d-k small programming header supported by flashpro and silicon sculptor samtec ftsh-105-01-l-d-k com pact programming header samtec ffsd-05-d-06.00-01-n 10-pin cable with 50 mil pitch sockets; included in fp3- 10pin-adapter-kit. actel fp3-10pin-adapter-kit compac t header and migration kit figure 16-5 ? programming header (top view) table 16-4 ? programming header pin numbers and description pin signal source description 1 tck programmer jtag clock 2 gnd 1 ? signal reference 3 tdo target board test data output 4 nc ? no connect 5 tms programmer test mode select 6v jtag target board jtag supply voltage 7v pump 2 programmer/target board programming supply voltage 8 ntrst programmer jtag test reset (hi-z with 10 k pull-down, high, low, or toggling) 9 tdi programmer test data input 10 gnd 1 ? signal reference notes: 1. both gnd pins must be connected. 2. flashpro3 can provide v pump if there is only one device on the target board. 12 34 56 78 9 tck tdo tms v tdi gnd nc trst gnd 10 pump v jtag in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.1 16-9 board-level considerations a bypass capacitor is required from v pump to gnd for all low-po wer flash devices during programming. this bypass capacitor protects the de vices from voltage spikes that may occur on the v pump supplies during th e erase and programming cycles. refer to pin descriptions for specific recommendations. for proper programming, 0.01 f and 0.33 f capaci tors (both rated at 16 v) are to be connected in parallel across v pump and gnd, and positioned as close to the fpga pins as possible. the bypass ca pacitor must be placed within 2.5 cm of the device pins. troubleshooting signal integrity symptoms of a signal integrity problem a signal integrity problem can ma nifest itself in many ways. the problem may show up as extra or dropped bits during serial communication, changing the meaning of the communication. there is a normal variation of threshold voltage and freque ncy response between pa rts even from the same lot. because of this, the effects of signal integrity may not always affect different devices on the same board in the same way. so metimes, replacing a device ap pears to make signal integrity problems go away, but this is just masking the pr oblem. different parts on identical boards will exhibit the same problem sooner or later. it is important to fix signal integrity problems early. unless the signal integrity problems are severe enough to completely block all communication between the device and the programmer, they ma y show up as subtle problems. some of the flashpro3 exit codes that are caus ed by signal integrity problems ar e listed below. signal integrity problems are not the only possible cause of these errors, but this list is intended to show where problems can occur. flashpro3 allows tck to be lowered from 24 mhz down to 1 mhz to allow you to address some signal integrit y problems that may oc cur with impedance mismatching at higher frequencies. chain integrity test error or analyze chain failure normally, the flashpro3 analyze chain command expects to see 0x2 on the tdo pin. if the command reports reading 0x0 or 0x3, it is seeing the tdo pin stuck at 0 or 1. the only time the tdo pin comes out of tristate is when the jtag tap state machine is in th e shift-ir or shift-dr state. if figure 16-6 ? board layout and progra mming header top view v cc v cci v jtag gnd tck tdo tms v pump tdi trst 1 tck 2 gnd 3 tdo 4 nc 5 tms 6 v jtag 7 v pump 8 trst 9 tdi 10 gnd low-power flash device v cc from the target board v jtag from the target board v cci from the target board polarizing notch in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 16-10 v1.1 noise or reflections on the tck or tms lines ha ve disrupted the correct state transitions, the device's tap state controller migh t not be in one of these two sta tes when the programmer tries to read the device. when this happens, the output is floating when it is read and does not match the expected data value. this can also be caused by a broken tdo net. only a small amount of data is read from the device during the analyze chai n command, so marginal problems may not always show up during this command. exit 11 this error occurs during the verify stage of pr ogramming a device. after programming the design into the proasic3/e devi ce, the device is verified to ensu re it is programmed correctly. the verification is done by shifting the programming data into the de vice. an internal comparison is performed within the device to verify that all switches are programmed correctly. noise induced by poor signal integrity can disrupt the writes and reads or the verification process and produce a verification error. while technically a verificati on error, the root cause is often related to signal integrity. refer to the flashpro user's guide for other error messages and solu tions. for the most up-to-date known issues and so lutions, refer to http://www.actel.com/support . conclusion igloo, fusion, and proasic3 devices offer a low-cost, single-chip solution that is live at power-up through nonvolatile flash technology. the flashloc k pass key and 128-bit aes key security features enable secure isp in an untrusted environmen t. on-chip flashrom enables a host of new applications, including device serialization, subscription-based applications, and ip addressing. additionally, as the flashrom is nonvolatile, all of these services can be provided without battery backup. related documents handbook documents microprocessor programming of actel?s low-power flash devices http://www.actel.com/documents/ lpd_microprocessor_hbs.pdf security in low-pow er flash devices http://www.actel.com/l pd_security_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf user?s guides flashpro user's guide http://www.actel.com/documents/flashpro_ug.pdf in-system programming (isp) of actel?s low-power flash devi ces using flashpro3 v1.1 16-11 part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-015-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the "isp architecture" section was updated to included the igloo plus family in the discussion of family-specific supp ort. the text, "when 1.2 v is used, the device can be reprogrammed in-system at 1.5 v only" was revised to state, "although the device can operate at 1.2 v core voltage, the device can only be reprogrammed when all supplies (v cc , v cci , and v jtag ) are at 1.5 v." 16-1 the "isp support in low-pow er devices" section and table 16-1 low-power flash families were updated to include the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 16-2 the "security" section was updated to mention that 15 k gate devices do not have a built-in 128-bit decryption core. 16-3 table16-2power supplies was revised to remove the normal operation column and add a table note stating, "all supply voltages should be at 1.5 v or higher, regardless of the setting during normal operation." 16-3 the "isp programming header information" section was revised to change fp3-26pin-adapter to fp3-10pin-adapter-kit. table 16-3 programming header ordering code was updated with the same change, as well as adding the part number ffsd-05-d-06.00-01-n, a 10-pin cable with 50-mil-pitch sockets. 16-8 the "board-level consid erations" section was updated to describe connecting two capacitors in parallel across v pump and gnd for proper programming. 16-9 51900055-2/7.06 informatio n was added to the "programming voltage (vpump) and vjtag" section about the jtag interface pin. 16-3 51900055-1/1.05 actgen was changed to smartgen. n/a in figure 16-6 board layout and programming header top view , the order of the text was changed to: v jtag from the target board v cci from the target board v cc from the target board 16-9 v1.1 17-1 microprocessor programming of actel?s low-power flash devices 17 ? microprocessor programming of actel?s low- power flash devices introduction the igloo, ? fusion, and proasic ? 3 families of flash fpgas supp ort in-system programming (isp) with the use of a microprocessor. flash-based fp gas store their configuration information in the actual cells within the fpga fabric. sram-based devices need an external configuration memory, and hybrid nonvolatile devices store the configurat ion in a flash memory inside the same package as the sram fpga. since the prog ramming of a true flash fpga is si mpler, requiring only one stage, it makes sense that programming with a micropro cessor in-system should be simpler than with other sram fpgas. this reduces bill-of-materials costs and printed circuit board (pcb) area, and increases system reliability. nonvolatile flash technology also gives the low-pow er flash devices the advantage of a secure, low- power, live-at-power-up, and single-chip solution. low-power flash devices are reprogrammable and offer time-to-market benefits at an asic-lev el unit cost. these features enable engineers to create high-density systems using existing asic or fpga design flows and tools. this document is an introduction to microprocessor programming only. to explain the difference between the options avai lable, user's guides for directc and stapl provide more detail on implementing each style. figure 17-1 ? isp using microprocessor mi c ropro c essor internal ram i/o fun c tions j ta g bus flash devi c e internal/external memory running directc on board memory device .dat file microprocessor programming of actel?s low-power flash devices 17-2 v1.1 microprocessor programming su pport in low-power devices the low-power flash families listed in table 17-1 support programming with a microprocessor and the functions describe d in this document. actel's low-power flash devices (listed in table 17-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 17-1 . where the information applies to only one fa mily or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 17-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 17-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s iglooe igloo devices enhanced with hi gher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1. 2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher density, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fp gas qualified for automotive applications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. microprocessor programming of actel?s low-power flash devices v1.1 17-3 programming algorithm jtag interface the low-power flash families ar e fully compliant with the ieee 1149.1 (jtag) standard. they support all the mandatory bounda ry scan instructions (extest, sample/preload, and bypass) as well as six optional public instructions (usercode, idcode, highz, and clamp). ieee 1532 the low-power flash families ar e also fully compliant with th e ieee 1532 programming standard. the ieee 1532 standard adds progra mming instructions and associat ed data registers to devices that comply with the ieee 1149.1 standard (jtag). these in structions and regi sters extend the capabilities of the ieee 1149.1 standard such th at the test access port (tap) can be used for configuration activities. the ieee 1532 standar d greatly simplifies the programming algorithm, reducing the amount of time needed to implement microprocessor isp. implementation overview to implement device programming with a microprocess or, the user should first download the c- based stapl player or directc code from the actel website . (see the actel website for future updates regarding the stapl player and directc code). using the easy-to-follow actel user's guide, create the low-level application programming interface (api) to provide the necessary basic functions. these api fu nctions act as the interface betwee n the programming software and the actual hardware ( figure 17-2 ). the api is then linked with the stapl player or directc and compiled us ing the microprocessor's compiler. once the en tire code is compiled, the user must do wnload the resulting binary into the mcu system's program memory (s uch as rom, eeprom, or flash). the system is now ready for programming. to program a design into the fpga, the user cr eates a bitstream or stapl file using the actel designer software, downloads it into the mcu system's volatile memory, and activates the stored programming binary file ( figure 17-3 on page 17-4 ). once the programming is completed, the bitstream or stapl file can be removed from the sy stem, as the configuration profile is stored in the flash fpga fabric and does not need to be reloaded at every system power-on. figure 17-2 ? device programming code relationship stapl file stapl player or directc api programming algorithm and data programming software i/o and memory functions microprocessor programming of actel?s low-power flash devices 17-4 v1.1 flashrom actel low-power flash devices have 1 kbit of user-accessible, nonvolatile, flashrom on-chip. this nonvolatile flashrom can be programmed along with the core or on its own using the standard ieee 1532 jtag programming interface. the flashrom is architected as eight pages of 128 bits. each page can be individually programmed (erased and written). additionally, on-chip aes security decryption can be used selectively to load data securely into the flashrom (e.g., over public or private networks, such as the internet). refer to flashrom in actel?s low-power flash devices . figure 17-3 ? mcu fpga programming model programming software source code microprocessor compiler bin file download to system program device programming file microprocessor programming of actel?s low-power flash devices v1.1 17-5 stapl vs. directc programming the low-power flash devices is perf ormed using directc or the stapl player. both tools use the stapl file as an input. directc is a compiled language, whereas stapl is an interpreted language. microprocessors will be ab le to load the fpga using directc much more quickly than stapl. this speed advantage becomes more apparent when lower clock speeds of 8- or 16-bit microprocessors are used . directc also requires less memory than stapl, since the programming algorithm is directly implemented. stapl does have one advantage over directc? the ability to upgrade. when a new programming algo rithm is required, the stapl user simply needs to regenerate a stapl file using the latest version of the designer software and download it to the system. the directc user must download the latest versio n of directc from actel, compile everything, and down load the result into the system ( figure 17-4 on page 17-5 ). figure 17-4 ? stapl vs. directc stapl flow directc flow directc source code input stapl file microprocessor compiler bin file generate the new stapl file download to system program device download to system program device microprocessor programming of actel?s low-power flash devices 17-6 v1.1 remote upgrade via tcp/ip transmission control protocol (tcp) provides a reliable bitstream transfer service between two endpoints on a network. tcp depends on intern et protocol (ip) to move packets around the network on its behalf. tcp protects against data lo ss, data corruption, packet reordering, and data duplication by adding checksums and sequence numb ers to transmitted data and, on the receiving side, sending back packets and acknowledging the receipt of data. the system containing th e low-power flash device can be assign ed an ip address when deployed in the field. when the device requires an update (core or flashrom), the programming instructions along with the new programming data (aes-encrypted cipher text) can be sent over the internet to the target system via the tcp/ip protocol. once the mcu receives the instruction and data, it can proceed with the fpga update. low-power flash devices support message authentication code (mac), which can be used to validate data for the target device. more details are given in the "message authentication code (mac) validation/authentication" section on page 17-6 . hardware requirement to facilitate the programming of the low-power flash families, the system must have a microprocessor (with access to the device jtag pins) to process the programming algorithm, memory to store the pr ogramming algorithm, pr ogramming data, and the necessary programming voltage. refer to the relevant da tasheet for programming voltages. security read-back prevention the low-power flash devices are designed with securi ty in mind. even without any security measures (such as flashlock with aes), it is not po ssible to read back the programming data from a programmed device. upon programming completi on, the programming algo rithm will reload the programming data into the device. the device will then use built-in circuitry to determine if it was programmed correctly. as an additional se curity measure, the device s are equipped with aes de cryption. aes works in two steps. the first step is to program a key into the devices in a secure or trusted programming center (such as actel in-house programmi ng (ihp) center). the second step is to encrypt any programming files with the same encryption key. the encrypted programming file will only work with the devices that have the same key. the aes used in the low-p ower flash families is the 128-bit aes decryption engine (rijndael algorithm). message authentication code (mac) validation/authentication as part of the aes decryption flow, the devices are equipped with a mac validation/authentication system. mac is an authentication tag, also called a checksum, derived by applying an on-chip authentication scheme to a stapl file as it is loaded into the fpga. macs are computed and verified with the sa me key so they can only be verified by the intended recipi ent. when the mcu system receives the aes-encrypted programming da ta (cipher text), it can validate the data by loading it into the fpga and perfo rming a mac verification prior to loading the data, via a second programming pass, into the fpga core cells. th is prevents erroneous or corrupt data from getting into the fpga. low-power flash devices with aes and mac are superior to devices with only des or 3des encryption. because the mac veri fies the correctness of the data, the fpga is protected from erroneous loading of invalid programming data that could damage a device ( figure 17-5 on page 17-7 ). the aes with mac enables field updates over public networks without fear of having the design stolen. an encrypted programming file can only work on devices with the correct key, rendering microprocessor programming of actel?s low-power flash devices v1.1 17-7 any stolen files useless to the thief. to learn more about th e low-power flash devices? security features, refer to security in low-pow er flash devices . conclusion the actel igloo, fusion, and proasic3 fpgas are id eal for applications that require field upgrades. the single-chip devices save board space by el iminating the need for eeprom. the built-in aes with mac enables transmission of programming da ta over any network without fear of design theft. igloo, fusion, and proasic3 fpgas are i eee 1532?compliant and support stapl, making the target programming software easy to implement. figure 17-5 ? proasic3 device encryption flow proasic3/e aes encryption encr y pted stream aes decryption encr y pted stream designer software decrypted stream mac validation programming control aes key tcp/ip public network microprocessor programming of actel?s low-power flash devices 17-8 v1.1 related documents handbook documents flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf security in low-pow er flash devices http://www.actel.com/docum ents/lpd_secu rity_hbs.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-016-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in th e current version (v1.1) page v1.0 (january 2008) the "microprocessor programming suppor t in low-power de vices" section was updated to include informatio n on the igloo plus family. the "igloo terminology" section and "proasic3 terminology" section are new. 17-2 boundary scan and ujtag v1.1 18-1 boundary scan in low-power flash devices 18 ? boundary scan in low-power flash devices boundary scan low-power flash devices are comp atible with ieee standard 11 49.1, which defines a hardware architecture and the set of mechanisms for boundary scan testing. jtag operations are used during boundary scan testing. the basic boundary scan logic circuit is composed of the tap controller, test data registers, and instruction register ( figure 18-2 on page 18-4 ). low-power flash devices support three types of test data registers: bypass , device identification, and boundary scan. the bypass register is selected when no other register needs to be accessed in a device. this speeds up test data transfer to othe r devices in a test data path. the 32-bit device identification register is a shift re gister with four fields (lsb, id number, part number, and version). the boundary scan register observes and controls th e state of each i/o pin. each i/o cell has three boundary scan register cells, each with serial-in, serial-out, parallel-in, and parallel-out pins. tap controller state machine the tap controller is a 4-bit state machin e (16 states) that operates as shown in figure 18-1 . the 1s and 0s represent the values that must be present on tm s at a rising edge of tck for the given state transition to occur. ir and dr indicate that the instruction register or the data register is operating in that state. the tap controller receives two control inputs (tms and tck) and gene rates control and clock signals for the rest of the test lo gic architecture. on power-up, th e tap controller enters the test- logic-reset state. to guarantee a reset of the co ntroller from any of the possible states, tms must remain high for five tck cycles. the trst pin can also be us ed to asynchronously place the tap controller in the test-logic-reset state. figure 18-1 ? tap controller state machine 1 test_logic_reset run_test_idle select_dr capture_dr shift_dr exit1_dr pause_dr exit2_dr update_dr select_ir capture_ir shift_ir exit1_ir pause_ir exit2_ir update_ir 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 boundary scan in lo w-power flash devices 18-2 v1.1 actel?s flash families support the jtag feature the low-power flash families listed in table 18-1 support the jtag feature and the functions described in this document. actel's low-power flash devices (listed in table 18-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 18-1 . where the information applies to only one fa mily or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 18-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 18-1 ? low-power flash families family 1 description timing numbers 2 igloo ? ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1.5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and addition al i/o standards iglooe dc and switching characteristics proasic ? 3l low-power high-performance 1. 2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher density, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-performance fpgas qualified for automotive applications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. boundary scan in low-power flash devices v1.1 18-3 boundary scan support in low-power devices the information in this document applies to all igloo, fusion, and proasi c3 devices. for igloo, igloo plus, and proasic3l devices, the flash*freeze pin must be deasserted for successful boundary scan operations. devices cannot en ter jtag mode directly from flash*freeze mode. boundary scan opcodes low-power flash devices support all ma ndatory ieee 1149.1 instructions (extest, sample/preload, and bypass) and the optional id code instruction ( table 18-2 ). boundary scan chain the serial pins are used to serial ly connect all the boundary scan register cells in a device into a boundary scan register chain ( figure 18-2 on page 18-4 ), which starts at the tdi pin and ends at the tdo pin. the parallel ports are co nnected to the internal core logi c i/o tile and the input, output, and control ports of an i/o buffer to capture and load data into the register to control or observe the logic state of each i/o. each test section is accessed through the tap, which has five associated pins : tck (test clock input), tdi, tdo (test data input and output), tms (test mo de selector), and trst (test reset input). tms, tdi, and trst are equipped with pu ll-up resistors to ensure proper operation when no input data is supplied to them. these pins are dedicated for boundary scan test usage. refer to the "jtag pins" description in pin descriptions for pull-up/-down recommendat ions for tdo and tck pins. table 18-2 ? boundary scan opcodes hex opcode extest 00 highz 07 usercode 0e sample/preload 01 idcode 0f clamp 05 bypass ff boundary scan in lo w-power flash devices 18-4 v1.1 board level recommendations table 18-3 gives pull-down recommendations for the trst and tck pins. figure 18-2 ? boundary scan chain device logic tdi tck tms trst tdo i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o bypass register instruction register tap controller test data registers table 18-3 ? trst and tck pull-down recommendations v jtag tie-off resistance* v jtag at 3.3 v 200 to 1 k v jtag at 2.5 v 200 to 1 k v jtag at 1.8 v 500 to 1 k v jtag at 1.5 v 500 to 1 k * equivalent parallel resistance if more than one device is on jtag chain ( figure 18-3 ) boundary scan in low-power flash devices v1.1 18-5 related documents handbook documents pin descriptions http://www.actel.com/documents/ lpd_pindescriptions_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet. to improve usability for customers, the device architecture information has now been split into handbook sections, which also include usage info rmation. no technical chan ges were made to the content unless explicitly listed. part number 51700094-019-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. note: tck is correctly wired with an equivalent tie-off resistance of 500 , which satisfies the table for v jtag of 1.5 v. the resistor values for trst are not appropriate in this case, as the tie-off resistance of 375 is below the recommended minimum for v jtag = 1.5 v, but would be appropriate for a v jtag setting of 2.5 v or 3.3 v. figure 18-3 ? parallel resistance on jtag chain of devices tdi tdi tdi tdi tdo tdo tdo tdo jtag header actel fpga 1 actel fpga 2 actel fpga 3 actel fpga 4 2 k 2 k 2 k 2 k 1.5 v tck trst vjtag gnd 1.5 k 1.5 k 1.5 k 1.5 k previous version changes in current version (v1.1) page v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 18-2 v1.1 19-1 ujtag applications in acte l?s low-power flash devices 19 ? ujtag applications in actel?s low-power flash devices introduction in igloo, ? fusion, and proasic ? 3 devices, there is bidirectional access from the jtag port to the core versatiles during normal operation of the device ( figure 19-1 ). user jtag (ujtag) is the ability for the design to use the jtag ports for access to the device for up dates, etc. while regular jtag is used, the ujtag tiles, located at the southeast area of the die, are directly connected to the jtag test access port (tap) controller in normal operatin g mode. as a result, all the functional blocks of the device, such as clock conditioning circuits (ccc) with plls, sram blocks, embedded flashrom, flash memory blocks, and i/o tiles, can be reac hed via the jtag ports. the ujtag functionality is available by instantiating the ujtag macro directly in the source code of a design. access to the fpga core versatiles from the jtag ports enables us ers to implement differ ent applications using the tap controller (jtag port). this document introduces the ujtag tile functionality and discusses a few application examples. however, the possible applications are no t limited to what is presented in this document. ujtag can serve different purposes in many design s as an elementary or auxiliary part of the design. for detailed usage information, refer to boundary scan in low-power flash devices . figure 19-1 ? block diagram of using ujtag to read flashrom contents from addr [6:0] data[7:0] clk enable sdo sdi reset addr[6:0] data[7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] control ujtag address generation and data serlialization ujtag applications in acte l?s low-power flash devices 19-2 v1.1 ujtag support in low-power devices the low-power flash fa milies listed in table 19-1 support the ujtag feature and the functions described in this document. the family name links to the datasheet for each family. any required timing details are linked from th e timing numbers column to th e relevant datasheet sections. actel's low-power flash devices (listed in table 19-1 ) provide a selection of low-power, secure, live-at- power-up, single-chip solutions. the nonvolatile fl ash-based devices do not require a boot prom and incorporate flashlock ? technology, which provides a unique combination of reprogrammability and design security with out external overhead. only low-power flash fpgas can offer these advantages. actel igloo plus fpgas are the industry-leadi ng 1.2 v ultra-low-power programmable logic devices (plds) and consume 90% less static powe r and over 50% less dynamic power than pld alternatives, while proasic3l devices offer a ba lance of low power and higher performance. flash*freeze technology used in igloo, igloo plus, and proasic3l devices enables easy entry to and exit from the ultra-low power mode, which co nsumes as little as 5 w, while retaining sram and register data. igloo plus also offers the abili ty to hold i/o state in flash*freeze mode. flash*freeze technology simpli fies power management thro ugh i/o and clock management without the need to turn off voltages, i/os, or cl ocks at the system level. entering and exiting flash*freeze mode takes less than 1 s. the actel fusion ? family, based on the highly successful proasic3 flash fpga architecture, has been designed as a high-performance , mixed-signal programmable sys tem chip. fusion supports many peripherals, including embedded flash memory, analog-to-digita l converter (adc), high-drive outputs, rc and crystal oscillators, and real-time counter (rtc). the total available on-chip memory, including the flash array blocks, is gr eater than that found in sram fpgas. igloo terminology in documentation, the term igloo fa milies or igloo devices refers to all igloo families as listed in table 19-1 . where the information applies to only one fa mily or limited devices, these exclusions will be explicitly stated. proasic3 terminology in documentation, th e term proasic3 families or proasic3 devices refers to all proasic3 families as listed in table 19-1 . where the information applies to only one family or limited devices, these exclusions will be explicitly stated. table 19-1 ? low-power flash families family 1 description timing numbers 2 igloo ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze? technology igloo dc and switching characteristic s igloo plus ultra-low-power 1.2 v and 1. 5 v fpgas with flash*freeze technology and enhanced i/o capabilities igloo plus dc and switching characteristics iglooe igloo devices enhanced with higher density, five additional plls, and additional i/o standards iglooe dc and switching characteristics proasic3l low-power, high-performance 1.2 v fpgas with flash*freeze technology proasic3l dc and switching characteristics proasic3 low-power, high-performance 1.5 v fpgas proasic3 dc and switching characteristics proasic3e proasic3 enhanced with higher density, five additional plls, and additional i/o standards proasic3e dc and switching characteristics proasic3 automotive low-power, high-pe rformance fpgas qualif ied for automotive applications automotive proasic3 dc and switching characteristics fusion low-power mixed-signal prog rammable system chip (psc) fusion dc and power characteristics notes: 1. the family names are linked to the appropriate product brief. 2. the timing number links go to the re levant timing numbers in the datasheet. ujtag applications in acte l?s low-power flash devices v1.1 19-3 ujtag macro the ujtag tiles can be instantiated in a design using the ujtag macro from the igloo, fusion, or proasic3 macro library. note that "ujtag" is a reserved name and cannot be used for any other user-defined blocks. a bloc k symbol of the ujtag tile macro is presented in figure 19-2 . in this figure, the ports on the left side of the bloc k are connected to the jt ag tap controller, and the right-side ports are accessib le by the fpga core versatiles. the td i, tms, tdo, tck, and trst ports of ujtag are only provided for design simulation pu rposes and should be treated as external signals in the design netl ist. however, these ports must not be connected to any i/o buffer in the netlist. figure 19-3 on page 19-4 illustrates the correc t connection of the uj tag macro to the user design netlist. actel de signer software will auto matically connect these ports to the tap during place-and-route. table 19-2 gives the port descriptions for the rest of the ujtag ports: table 19-2 ? ujtag port descriptions port description uireg [7:0] this 8-bit bus carries the contents of the jtag instruction regi ster of each device. instruction register values 16 to 127 are not reserved and can be employed as user-defined instructions. urstb urstb is an active-low signal and will be asserted when the ta p controller is in test-logic-reset mode. urstb is asserted at power-up, and a pow er-on reset signal resets the tap controller. urstb will stay asserted until an external tap access changes the tap controller state. utdi this port is directly conn ected to the tap's tdi signal. utdo this port is the user tdo ou tput. inputs to the utdo port are sent to the tap tdo output mux when the ir address is in user range. udrsh active-high sign al enabled in the shiftdr tap state udrcap active-high signal enab led in the capturedr tap state udrck this port is directly conn ected to the tap's tck signal. udrupd active-high sign al enabled in the updatedr tap state figure 19-2 ? ujtag tile block symbol tdi tck tdo tms trst uireg0 uireg1 uireg2 uireg3 uireg4 uireg5 uireg6 uireg7 utdi utdo udrck udrcap udrsh udrupd urstb ujtag applications in acte l?s low-power flash devices 19-4 v1.1 ujtag operation there are a few basic functions of the ujtag macr o that users must understand before designing with it. the most important fundamental concept of the ujtag design is its connection with the tap controller state machine. tap controller state machine the 16 states of the tap contro ller state machine are shown in figure 19-4 on page 19-5 . the 1s and 0s, shown adjacent to the sta te transitions, represent the tm s values that must be present at the time of a rising tck edge for a state transiti on to occur. in the state s that include the letters "ir," the instruct ion register operates; in the states that contain the letters "dr," the test data register operates. the tap controller receives tw o control inputs, tms and tck, and generates control and clock signals for the rest of the test logic. on power-up (or the assertion of trst), the tap controller ente rs the test-logic-reset state. to reset the controller from any other state, tms must be held high for at least five tck cycles. after reset, the tap state changes at the rising edge of tck, based on the value of tms. note: do not connect jtag pins (tdo, tdi, tms, tck, or trst) to i/os in the design. figure 19-3 ? connectivity method of ujtag macro tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] inputs outputs tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] inputs outputs a) correct instantiation b) incorrect instantiation fpga versatiles fpga versatiles ujtag applications in acte l?s low-power flash devices v1.1 19-5 ujtag port usage uireg[7:0] hold the contents of the jtag instruct ion register. the uireg vector value is updated when the tap controller state mach ine enters the update_ir state. in structions 16 to 127 are user- defined and can be employed to encode multiple applications and commands within an application. loading new instructions into the uireg vector requires users to send appropriate logic to tms to put the tap controll er in a full ir cycle starting from the select ir_scan state and ending with the update_ir state. utdi, utdo, and udrck are directly connected to the jtag tdi, tdo, and tck ports, respectively. the tdi input can be used to provide either data (t ap controller in the shift_dr state) or the new contents of the instruction register (t ap controller in the shift_ir state). udrsh, udrupd, and udrcap are high when the tap controller state machine is in the shift_dr, update_dr, and capture_dr states, respectively. therefore, they act as flags to indicate the stages of the data shift process. these flags are useful fo r applications in which blocks of data are shifted into the design from jtag pins. for example, an active udrsh can indicate that utdi contains the data bitstream, and udrupd is a candida te for the end-of -data-stream flag. as mentioned earlier, users should not connect the tdi, tdo, tck, tms, and trst ports of the ujtag macro to any port or net of the design ne tlist. the designer soft ware will automatically handle the port connection. figure 19-4 ? tap controller state diagram run_test/ idle 0 test_logic_reset 1 0 1 select_ dr_scan update_dr exit2_dr pause_dr exit1_dr shift_dr capture_dr select_ ir_scan update_ir exit2_ir pause_ir exit1_ir shift_ir capture_ir 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 ujtag applications in acte l?s low-power flash devices 19-6 v1.1 typical ujtag applications bidirectional access to the jtag port from versa tiles?without putting the device into test mode? creates flexibility to implement many different ap plications. this section describes a few of these. all are based on importing/exporting data through the ujtag tiles. clock conditioning circuitry ?dynamic reconfiguration in low-power flash devices, cccs, which include plls, can be configured dynamically through either an 81-bit embedded shift register or static flash programming switches. these 81 bits control all the characteristics of the ccc: routing mux archit ectures, delay values, divider values, etc. table 19-3 lists the 81 configuration bits in the ccc. the embedded 81-bit shift register (for the dynami c configuration of the ccc) is accessible to the versatiles, which, in turn, have access to the uj tag tiles. therefore, the ccc configuration shift register can receive and load the new configuration data stream from jtag. dynamic reconfiguration eliminates the need to reprogram the device when reconfiguration of the ccc functional blocks is needed. the ccc configur ation can be modified wh ile the device continues to operate. employing th e ujtag core requires the user to design a module to provide the configuration data and control the ccc configuratio n shift register. in esse nce, this is a user- designed tap controller re quiring chip resources. table 19-3 ? configuration bits of igloo and proasic3 ccc blocks bit number control function 80 reset enable 79 dyncsel 78 dynbsel 77 dynasel <76:74> vcosel [2:0] 73 statcsel 72 statbsel 71 statasel <70:66> dlyc [4:0] <65:61> dlyb {4:0] <60:56> dlyglc [4:0] <55:51> dlyglb [4:0] <50:46> dlygla [4:0] 45 xdlysel <44:40> fbdly [4:0] <39:38> fbsel <37:35> ocmux [2:0] <34:32> obmux [2:0] <31:29> oamux [2:0] <28:24> ocdiv [4:0] <23:19> obdiv [4:0] <18:14> oadiv [4:0] <13:7> fbdiv [6:0] <6:0> findiv [6:0] ujtag applications in acte l?s low-power flash devices v1.1 19-7 similar reconfiguration capability exists in the actel proasic plus ? family. the only difference is the number of shift register bits controlling the ccc (27 in proasic plus and 81 in igloo, proasic3, and fusion). fine tuning in some applications, design constants or parame ters need to be modifi ed after programming the original design. the tuning process can be done using the ujtag tile without reprogramming the device with new values. if the parameters or constants of a design are stored in distributed registers or embedded sram bloc ks, the new values can be shifted onto the jtag tap controller pins, replacing the old va lues. the ujtag tile is used as the ?bridge? for data tr ansfer between the jtag pins and the fpga versatiles or sram logic. figure 19-5 shows a flow chart example for fine- tuning application steps using the ujtag tile. in figure 19-5 , the tms signal sets the ta p controller state machine to the appropriate states. the flow mainly consists of two steps: a) shifting the defined instructio n and b) shifting the new data. if the target parameter is constantly used in the de sign, the new data can be shifted into a temporary shift register from utdi. the udrsh output of uj tag can be used as a sh ift-enable signal, and udrck is the shift clock to the shift register . once the shift process is completed and the tap controller state is moved to the update_dr state , the udrupd output of the ujtag can latch the new parameter value from the temporary register into a permanent locati on. this avoids any interruption or malfunctioning during the serial shift of the new value. figure 19-5 ? flow chart example of fine-tun ing an application using ujtag yes no tap controller in test_logic_reset state set tap state to shift_ir shift the user-defined instruction of tuning application set tap state to update_ir latch the recorded data onto the location of stored parameter uireg equal to the user-defined instruction set tap state to shift_dr shift data into tdi and record utdi in a shift register set tap state in update_dr ujtag applications in acte l?s low-power flash devices 19-8 v1.1 silicon testing and debugging in many applications, the design ne eds to be tested, debugged, and veri fied on real si licon or in the final embedded application. to debug and test th e functionality of designs, users may need to monitor some internal logic (or ne ts) during device operation. the approach of adding design test pins to monitor the critical intern al signals has many disadvantages, such as limiting the number of user i/os. furthermore, adding external i/os fo r test purposes may require additional or dedicated board area for testing and debugging. the ujtag tiles of low-power flash devices offer a flexible and cost-effective solution for silicon test and debug applications. in this solution, the signals under test are shifted out to the tdo pin of the tap controller. th e main advantage is that all the te st signals are monito red from the tdo pin; no pins or additional board-level resources are required. figure 19-6 illustrates this technique. multiple test nets are brought into an internal mux architecture. the selection of the mux is done using the contents of the tap cont roller instruction register, wher e individual instr uctions (values from 16 to 127) correspond to di fferent signals under test. the selected test signal can be synchronized with the rising or falling edge of tck (optional) and sent out to utdo to drive the tdo output of jtag. the test and debug procedure is not limited to the example in figure 19-5 on page 19-7 . users can customize the debug and test interf ace to make it appropriate for their applications. for example, multiple test signals can be registered and then se nt out through utdo, each at a different edge of tck. in other words, n signals are samp led with an f tck / n sampling rate. the bandwidth of the information sent out to tdo is always proportional to the frequency of tck. sram initialization users can also initialize embedded srams of the lo w-power flash devices. the initialization of the embedded sram blocks of the design can be done using ujtag tiles, where the initialization data is imported using the tap controller. similar functionality is available in proasic plus devices using jtag. the guidelines for implementation and design examples are given in the ram initialization and rom emulation in proasic plus devices application note. srams are volatile by nature; data is lost in th e absence of power. ther efore, the initialization process should be done at each power-up if necessary. figure 19-6 ? ujtag usage example in tes t and debug applications tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] clk dq internal test nets instruction decode to scope channel ujtag applications in acte l?s low-power flash devices v1.1 19-9 flashrom read-back using jtag the low-power flash architecture contains a de dicated nonvolatile flashrom block, which is formatted into eight 128-bit pages. for more information on flashrom, refer to flashrom in actel?s low-power flash devices . the contents of flashrom are av ailable to the versatiles during normal operation through a read operation. as a result, the ujtag macro can be used to provide the flashrom contents to the jtag port duri ng normal operation. figure 19-7 illustrates a simple block diagram of using ujtag to read the contents of flashrom during normal operation. the flashrom read address can be provided from outside the fpga throug h the tdi input or can be generated internally using the core logic. in either case, data serialization logic is required ( figure 19-7 ) and should be designed using the versatile core logic. flashrom contents are read asynchronously in parall el from the flash memory and shifted out in a synchronous serial format to tdo. shifting the se rial data out of the seri alization block should be performed while the tap is in udrsh mode. the coordination between tck and the data shift procedure can be done using the tap state machine by monitori ng udrsh, udrcap, and udrupd. conclusion actel low-power flash fpgas offer many unique advantages, such as security, nonvolatility, reprogrammablity, and low power?all in a single chip. in addition, igloo, fusion, and proasic3 devices provide access to the jtag port from core versa tiles while the device is in normal operating mode. a wide range of available user-defined jtag opcodes allows users to implement various types of applications, exploiting this feature of these devices. the connection between the jtag port and core tiles is implemented through an embedded and hardwired ujtag tile. a ujtag tile can be instantiated in designs using the ujtag library cell. this document presents multiple examples of ujtag applications, such as dynamic reconfiguration, silicon test and debug, fine- tuning of the design, and ram initialization. each of these applications offers many useful advantages. figure 19-7 ? block diagram of using ujtag to read flashrom contents from addr [6:0] data[7:0] clk enable sdo sdi reset addr[6:0] data[7:0] tdi tck tdo tms trst utdi utdo udrck udrcap udrsh udrupd urstb uireg[7:0] control ujtag address generation and data serlialization ujtag applications in acte l?s low-power flash devices 19-10 v1.1 related documents application notes ram initialization and rom emulation in proasic plus devices http://www.actel.com/documents/apa_ram_initd_an.pdf handbook documents boundary scan in lo w-power flash devices http://www.actel.com/documen ts/lpd_boundaryscan_hbs.pdf flashrom in actel?s lo w-power flash devices http://www.actel.com/docum ents/lpd_flashrom_hbs.pdf part number and revision date this document contains content extracted from th e device architecture section of the datasheet, combined with content previously published as an application note describing features and functions of the devi ce. to improve usability for customers, th e device architecture information has now been combined with usage in formation, to reduce duplicatio n and possible inconsistencies in published information. no technical changes were made to the datasheet content unless explicitly listed. changes to the application note content we re made only to be co nsistent with existing datasheet information part number 51700094-020-1 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.1) page v1.0 (january 2008) the chapter was updated to include th e igloo plus family and information regarding 15 k gate devices. n/a the "igloo terminology" section and "proasic3 terminology" section are new. 19-2 board-level requirements v1.3 20-1 application note ac318 20 ? power-up/-down behavior of proasic3/e devices introduction actel proasic ? 3/e devices are flash-based fpgas manufactured on a 0.13 m process node. proasic3/e fpgas offer a single-chip, reprogramma ble solution and support level 0 live at power- up (lapu) due to their nonvolatile architecture. three main voltage pins ar e used by proasic3/e devices during normal operation: 1 ?v cc : voltage supply to the fpga core ?v cci bx: supply voltage to the bank's i/o output buffers and i/o logic. bx is the i/o bank number. ? vmvx: quiet supply voltage to the input buffers of each i/o bank. x is the bank number. the i/o bank vmv pin must be tied to the v cci pin of the same bank. th erefore, the supplies that need to be powered up/down du ring normal operation are v cc and v cci . these power supplies can be powered up/down in any sequence during no rmal operation of proa sic3/e fpgas. during power-up, i/os in each bank will remain trista ted until the last supply (being either v cci bx or v cc ) reaches its functional activation voltage. simila rly, during power-down, i/os of each bank are tristated once the first su pply reaches its brownout deactivation voltage. proasic3/e devices exhibit very low transient current on each po wer supply during power-up. the peak value of the transient current depends on th e device size, temperatur e, voltage levels, and power-up sequence. proasic3/e device inputs can be driven while the de vice is not powered. the driven i/os do not pull up power planes, and the current draw is limit ed to very small leakage current. therefore, proasic3/e fpgas are suitable fo r applications in which cold-sparing is required. all proasic3e devices and the a3p030 device in the proasic3 family are also desi gned to be compatible with hot- swap applications. 2 transient current the source of transient current, also known as inrush current, varies depending on the fpga technology. due to their volati le technology, the internal re gisters in sram fpgas must be initialized before configuration can start. this in itialization is the source of significant inrush current in sram fpgas during power-up. due to the nonvolatile nature of flash technology, proasic3/e devices do not require any initialization at power-up, and there is very little or no crossbar current through pmos and nmos devices. therefore, the transient current at power-up is significantly less than for sram fpgas. figure 20-1 on page 20-2 illustrates the types of power consumption by sram fpgas vs. ac tel's antifuse and flash fpgas. 1. for more information on proasic3/e device voltage su pplies, refer to the appropriate datasheet located at http://www.actel.com/techdocs/ds . 2. for more details on the levels of hot-swap compatibility in proasci3/e devices, refer to the "hot-swap support" section in the i/o structures chapter of the handbook for the device you are using. power-up/-down behavior of proasic3/e devices 20-2 v1.3 transient current on v cc 3 the preliminary characterization of the transient current on v cc has been performed on a3pe600- pq208 eas devices. the transient current measurements are performed on two a3pe600-pq208 eas parts while all the device i/os were interna lly pulled down. the preliminary measurements at typical conditions show that th e maximum transient current on v cc , when the power supply is powered at ramp rates ranging from 15 v/ms to 0.15 v/ms, does not ex ceed the ma ximum standby current specified in the de vice datasheets. refer to proasic3 dc and switching characteristics and proasic3e dc and swit ching characteristics for more information. transient current on v cci 3 the preliminary characterization of the transient current on v cci has been performed on a3pe600- pq208 eas devices, similar to v cc transient current measurements. the preliminary measurements at typical conditions show that the maximum transient current on v cci , when the power supply is powered at ramp rates ranging from 33 v/ms to 0.33 v/ms, does not ex ceed the ma ximum standby current specified in the device datasheet. refer to proasic3 dc and swit ching char acteristics and proasic3e dc and swit ching characteristics for more information. figure 20-1 ? types of power consumption in sram fpgas and actel nonvolatile fpgas 3. the "transient current on v cc " section will be updated after the full characterization of proasic3/e has been completed. sram actel fpgas time (or frequency) current configuration sram fpgas power-on inrush sram fpgas active frequency dependent static system supply voltage power-up/-down behavior of proasic3/e devices v1.3 20-3 i/o behavior at power-up/-down this section discusses the behavior of device i/os, used and unused, during power-up/-down of v cc and v cci . as mentioned earlier, vmvx and v cci bx are tied together, an d therefore, inputs and outputs are powered up/down at the same time. i/o state during power-up/-down this section discusses the charac teristics of i/o behavior during device power-up and power-down. before the start of power-up, all i/os are in tris tate mode. the i/os will remain tristated during power-up until the last voltage supply (v cc or v cci ) is powered to its functi onal level (power supply functional levels ar e discussed in the "power-up to func tional time" section on page 20-4 ). after the last supply reaches the functi onal level, the outputs will exit the tristate mode and drive the logic at the input of the output buffer. similarly, the input buffers will pass the external logic into the fpga fabric once the last supply reaches the functional level. the beha vior of user i/os is independent of the v cc and v cci sequence or the state of ot her voltage supplies of the fpga (v pump and v jtag ). figure 20-2 shows the output buffer behavior during power-up with 10 k external pull-down. in figure 20-2 , v cc is powered first, and v cci is powered 5 ms after v cc . figure 20-3 on page 20-4 shows the state of the i/o when v cci is powered about 5 ms before v cc . in the circuitry shown in figure 20-3 on page 20-4 , the output is externally pulled down. during power-down, device i/os become tristated once the first power supply (v cc or v cci ) drops below its brownout voltage level. the i/o behavior during power-down is also independent of voltage supply sequencing. figure 20-2 ? i/o state when v cc is powered before v cci power-up/-down behavior of proasic3/e devices 20-4 v1.3 power-up to functional time at power-up, device i/os exit the tristate mode and become functional once the last voltage supply in the power-up sequence (v cci or v cc ) reaches its functional activati on level. typical i/o behavior during power-up to functional time is illustrated in figure 20-2 on page 20-3 and figure 20-3 . the functional le vel of the voltage supplies at power-up is designed to be 0.85 v 0.25 v for v cc and 0.9 v 0.3 v for the v cci supply. once the last voltage su pply in the power-up sequence exceeds its functional level, the device i/os will transition into a function al state. therefore, the power-up?to?functional time is the time it takes for the last supply to power up from zero to its functional level. however, the functional level of the power su pply during power-up may vary slightly within the specification in different ramp rates. proasic3/e devices meet level 0 lapu, i.e., can be functional prior to v cc reaching the regulated voltage required. this importan t advantage distinguishes proasi c3/e flash devices from their sram-based counterparts. sram-based fpgas, due to their vo latile technology , require hundreds of milliseconds after power-up to configure the design bitstream before they become functional. refer to figure 20-4 on page 20-5 for more information. figure 20-3 ? i/o state when v cci is powered before v cc power-up/-down behavior of proasic3/e devices v1.3 20-5 figure 20-4 ? i/o state as a function of v cci and v cc voltage levels region 1: i/o buffers are off region 2: i/o buffers are on. i/os are functional (except differential inputs) but slower because v cci /v cc are below specification. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. min v cci datasheet specification voltage at a selected i/o standard; i.e., 1.425 v or 1.7 v or 2.3 v or 3.0 v v cc v cc = 1.425 v region 1: i/o buffers are off activation trip point: v a = 0.85 v 0.25 v deactivation trip point: v d = 0.75 v 0.25 v activation trip point: v a = 0.9 v 0.3 v deactivation trip point: v d = 0.8 v 0.3 v v cc = 1.575 v region 5: i/o buffers are on and power supplies are within specification. i/os meet the entire datasheet and timer specifications for speed, v ih /v il , v oh /v ol , etc. region 4: i/o buffers are on. i/os are functional (except differential but slower because v cci is below specifcation. for the same reason, input buffers do not meet v ih /v il levels, and output buffers do not meet v oh /v ol levels. region 4: i/o buffers are on. i/os are functional (except differential inputs) where vt can be from 0.58 v to 0.9 v (typically 0.75 v) v =v + vt cc cci v cci region 3: i/o buffers are on. i/os are functional; i/o dc specifications are met, but i/os are slower because the v cc is below specification power-up/-down behavior of proasic3/e devices 20-6 v1.3 brownout voltage brownout is a condition in which the voltage supp lies are lower than norm al, causing the device to malfunction as a result of insufficient power. in general, actel does not guarantee the functionality of the design inside proasic3/e devices if voltage supplies ar e below their mi nimum recommended operating condition. actel has performed measurem ents to characterize the brownout levels of fpga power supplies. the brownout levels of th e power supplies for proasic3/e devices are designed to be 0.75 v 0.25 v for v cc and 0.8 v 0.3 v for v cci . for the purpose of characterization, a direct path fro m the device input to output is monitored while voltage supplies are lowered gradually. the brownout point is defined as the voltage level at which the output stops following the input. char acterization tests performed on two a3pe600-pq208 eas devices in typical operating conditions showed the brownout voltage levels to be within the specification. during device power-down, the device i/os become tristated once the first supply in the power- down sequence drops below its brownout deactivation voltage. pll behavior at br ownout condition when pll power supply voltage and/or v cc levels drop below the v cc brownout levels (0.75 v 0.25 v), the pll output lock signal goes low and/or the output clock is lost. the following sections explain pll behavior during and after the brownout condition. v ccpll and v cc tied together in this condition, both v cc and v ccpll drop below the 0.75 v 0.25 v brownout level. during the brownout recovery, once v ccpll and v cc reach the activation point (0.85 0.25 v) again, the pll output lock signal may still remain low with the pll output clock signal toggling. if this condition occurs, there are two ways to re cover the pll output lock signal : 1) recycle the power supplies of the pll (power off and on) by using the pll pown down signal; 2) turn off the input reference clock to the pll and th en turn it back on. only v ccpll is at brownout in this case, only v ccpll drops below the 0.75 v 0.25 v brownout level and the v cc supply remains at nominal recommended operat ing voltage (1.5 v 0.075 v). in this condition, the pll behavior after brownout recovery is simi lar to initial power-up condition, and the pll will regain lock automatically after v ccpll is ramped up above the activation level (0.85 0.25 v). no intervention is necessary in this case. only v cc is at brownout in this condition, v cc drops below the 0.75 v 0.25 v brownout level and v ccpll remains at nominal recommended operating voltage (1.5 v 0.075 v). during the brownout recovery, once v cc reaches the activation point ag ain (0.85 0.25 v), the pll output lock signal may still remain low with the pll output clock signal toggling. if this condition occurs , there are two ways to recover the pll output lock signal: 1) recycle th e power supplies of the pll (power off and on) by using the pll powndown signal; 2) turn off the input re ference clock to the pll and then turn it back on. it is important to note that actel recommend s using a monotonic power supply or voltage regulator to ensure proper power-up behavior. internal pull-up and pull-down proasic3/e device i/os are equipp ed with internal weak pull-up/-do wn resistors that can be used by designers. if used, these internal pull-up/-down resistors will be activated during power-up, once both v cc and v cci are passed their functional activation le vel. similarly, during power-down, these internal pull-up/-down resi stors will turn off once the first su pply voltage falls below its brownout deactivation level. power-up/-down behavior of proasic3/e devices v1.3 20-7 cold-sparing in cold-sparing applications, volt age can be applied to device i/os before and during power-up. cold-sparing applications rely on three important characteristics of the device: 1. i/os must be tristated before and during power-up. 2. voltage applied to the i/os must not power up any part of the device. 3. device reliability must not be compromised if voltage is applied to i/os before or during power-up. as described in the "power-up to functional time" section on page 20-4 , proasic3/e i/os are tristated before and during power-u p until the last voltage supply (v cc or v cci ) is powered up past its functional level. furthermore, applying voltage to the proasic3/e i/os does not pull up v cc or v cci and, therefore, does not pa rtially power up the device. table 20-1 includes the cold-sparing test results on a3pe600-pq208 eas devices. in th is test, leakage current on the device i/o and residual voltage on the power supply rails were measured while voltage was applied to the i/o before power-up. the reliability of proasic3/e i/os is guaranteed if the voltage level, applied to the device i/os, is less than 3.6 v, as specified in the product datasheets. therefore, pr oasic3/e devices meet all three requirements stated earlier in th is section and are suitable fo r cold-sparing applications. hot-swap hot-swapping is the operation of hot insertion or hot removal of a card in a powered-up system. the i/os need to be configured in hot-insertion mode if hot-sw apping compliance is required. all proasic3e devices support hot-swapping, and the on ly proasic3 device supporting hot-swapping is the a3p030. for more details on the levels of hot- swap compatibility in proasic3/e devices, refer to the "hot-swap support" section in the i/o structures chapter of the handbook for the device you are using. conclusion actel's proasic3/e flash fpgas provide an excellent programmable logic solution for a broad range of applications. in addition to high performance, low cost, security, nonvolatility, and single chip, they are live at power-up (meet level 0 of the la pu classification) and offer clear and easy-to-use power-up/-down characteristics. unlike sram fpgas, proasic3/e devices do not require any specific power-up/-down sequencing and have extremely low power-up inrush current in any power-up sequence. proasic3/e fpgas also support both cold-sparing and hot-swapping for applications requiring these capabilities. table 20-1 ? cold-sparing test results for a3pe600 devices device i/o residual voltage (v) leakage current v cc v cci input 0 0.003 <1 a output 0 0.003 <1 a power-up/-down behavior of proasic3/e devices 20-8 v1.3 related documents datasheets proasic3 dc and switching characteristics http://www.actel.com/documents/pa3genspecs_ds.pdf proasic3e dc and swit ching characteristics http://www.actel.com/documents/pa3egenspecs_ds.pdf handbook documents i/o structures in igloo plus devices http://www.actel.com/documents/iglooplus_io_hbs.pdf i/o structures in iglo o and proasic3 devices http://www.actel.com/documents/igloo_pa3_io_hbs.pdf i/o structures in iglo oe and proasic3e device s http://www.actel.com/documen ts/iglooe_pa3e_io_hbs.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content part number 51700094-021-3 revised march 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.3) page v1.2 (january 2008) the "handbook documents" section was updated to include the three different i/o structure handbook chapters. 20-8 v1.1 (january 2008) the first sentence of the "pll behavior at brownout condition" section was updated to read, "when pll power supply voltage and/or v cc levels drop below the v cc brownout levels (0.75 v 0.25 v), the pll output lock signal goes low and/or the output clock is lost." 20-6 v1.0 (january 2008) the "pll behavior at brownout condition" section was added. 20-6 v1.0 21-1 proasic3/e sso and pi n placement guidelines 21 ? proasic3/e sso and pin placement guidelines introduction ground bounce and v cc bounce have always been present in digital integrated circuits (ics). with the advance of technology and shrinking cmos featur es, the speed of designs, i/o slew rates, and the size of i/o busses have increa sed significantly in th e past few years. as a result, simultaneously switching outputs (ssos) and their effects on signal integrity have become an important factor in any digital ic design. when ssos are not properly designed into a board layout or digital ic, data corruption and system failure may result. to prevent sso-induced issues in modern digita l systems, designers must compromise an elegant board layout for reliability. an elegant board layout may include pr actices such as placing all inputs on one side of a chip, outputs on the opposite side, and all bus pins next to each other to make board layout simple. in today's digital systems, utilizing modern fpgas such as actel proasic ? 3/e may result in data corruption due to ground bounce, v cc bounce, or crosstalk. to design a reliable system for proasic3/e fpgas , follow three simple rules: 1. identify the ssos in a design as early in the design cycle as possible, and spread them out across the entire die peripher y. avoid clusters of more than four adjacent sso pins. 2. identify sensitive (and usua lly asynchronous) sy stem signals, and sh ield them from the effects of sso (specific shielding techniqu es are discussed later in this document). 3. use the lowest possible i/o slew rate and drive strength the design timing will support. furthermore, relatively large lead inductance in pq, tq, and vq packages makes these packages more vulnerable to ssos and hence undesirabl e for high-speed designs or designs with a considerable number of ssos. fg or bg packages are preferred in such designs because they show much better sso performance. by following the above three rules, you will create reliable systems free from the effects of ssos. the following sections cover sp ecific sso recommendations and mitigation techniques for designs that do not comp ly with these recommendations. sso effects the total number of ssos for each bus is determined by identifying the outputs that are synchronous to a single clock domain, have their clock-to-out time s within 200 ps of each other, and are placed next to each other on die pads that are on both sides of a sensitive i/o, as shown in figure 21-1 on page 21-2 . the sensitive i/o affected by sso is sometimes referred to as the victim i/o or quiet i/o. ssos may affect the victim i/o if the total number of sso s on both sides of the victim i/o exceeds the proasic3/e sso recommendat ion. it is important to note that the ssos should be referenced to the die pads and not package pins, since neighboring package pins are not necessarily next to each other on the die (e.g., for bg and fg packages). this can be determined by using multiview navigator (mvn) in the designer software, or die/package bonding diagrams provided by actel. however, when routing traces on the board, it is important to note that ssos on neighboring traces on the board may affect the quiet i/o surrounded by the sso traces due to crosstalk or coupling. proasic3/e sso and pi n placement guidelines 21-2 v1.0 sso effect on power and gr ound for quiet outputs if ssos toggle in one direction (either high to low or low to high), a significant amount of current quickly begins to flow to the ground or v cci pins. this current is the sum of the simultaneous sink or sour ce currents of the cmos output buffers. the quick jump in current causes a voltage drop on the parasitic inductance between the board and die v cci and ground (v = l di/dt). for more informat ion about the ground and v cci bounce phenomenon, refer to the simultaneous switching noise application note . the local fluctuations of the v cci and ground levels may cause the signals on quie t outputs (measured with re spect to the fluctuating v cci and ground) to be misinterpreted as unwanted logic glitches. sso effect on inputs ssos may also affect quiet inputs due to the mutu al inductance and capacitance on the package in addition to poss ible crosstalk of signal traces on the board. ssos can cause logic glitches on any quiet inputs they surround. the un wanted glitches may cause func tional failures if they are propagated through the input buffer . in sso characterizati on of proasic3/e devices, glitches are considered errors if they cause intern al latches in the design to trigger. sso effect on output delay (push-out) as the speed and i/o slew rate of digita l ics increase, effec ts of ground and v cci bounce start to surface in digital system designs. one of these effects is output delay or push-out. the ground bounce and v cci dip induced by sso transitions creates a temporary collapse of internal v cci and/or gnd supply levels in the output buffers. this ch ange in supply level in creases the output buffer propagation delay time. it is import ant to note that push-o ut occurs on the sso bus itself as well as on the victim outputs. multiple factors, such as sso bus frequenc y, drive strength, and slew rate, contribute to push-out. these factors can be adjusted to mitigate the push-out phenomenon. if the clock-to-out time of the victim output is important , the push-out delay should be considered in the timing budget of the design. sso effect on minimum input slew rat e (input maximum rise/fall time) if the ssos surrounding an input exceed th e actel recommendation, the minimum slew rate requirement for that input may be affected. the minimum input slew rate is the slowest signal transition time (from 0 to 1 or vice versa) at th e input that does not cause unwanted logic glitches during signal transition. figure 21-2 on page 21-3 illustrates the unwanted logic glitches with slow transition times. as shown, the lo gic glitch due to the slow input transition time may cause logic malfunction at edge-sensitive inputs (i.e., clock sign als). if the sensitive inpu ts are affected by the sso bus, the input minimu m slew rate (maximum rise and fall time) should be re duced from what is listed in the device datasheet. usually, synchronous, level-sensitive inputs are not prone to malfunction due to this phenomenon because thei r logic value is important only when sampled by a clock. figure 21-1 ? basic block diagram of quiet i/o surrounded by sso bus sso bus quiet i/o proasic3/e sso and pi n placement guidelines v1.0 21-3 shielding from ssos when exposure of sensitive signal s (e.g., asynchronous reset) to ssos is inevitable , these signals need to be shielded from the sso s to mitigate the unwanted effects. shielding is basically separating the sensitive signals from ssos using neighboring pins. figure 21-3 shows a basic block diagram depicting a victim output in the presence of an sso bus. there are different shielding tech niques that can be used to protect the victim i/o from the sso bus. before describing these techniques, the concept of virtual ground and virtual v cci should be understood. virtual ground virtual ground , also known as soft ground, is used to improve noise performance. as opposed to a real ground, which is connected to planes within the package, a virtual grou nd is connected to the planes through the impedance of an i/o buffer. a virtual ground is a ground pin implemented using regular i/o ports. to implement a virtual grou nd, instantiate an output buffer (with highest drive strength and slew rate) in th e design. tie the input of this ou tput buffer to zero within the design so the output buffer is constantly driving to the ground level. virtual v cci virtual v cci is similar to virtual ground. the only diff erence is that in the case of virtual v cci , the output buffer is permanently driving to logic high. in general, there are two shielding methods recommended by actel: a) using gnd pins or virtual grounds and b) using any v ccii , gnd, v cci , unused i/o, used (but not sensitive) i/o, or any combination of these pins. shielding using gnd or virtual ground pins when shielding sensitive i/os from the sso bus, gnd or virtual ground pins can be used if required. in this case, two or three gnd or virtual ground pins should be placed on each side of the quiet i/o. the shielding pins should be connected externally to the board-level ground. to prevent any board-level coupling or crosstalk noise on the sens itive i/os, the shielding pi ns should be routed on figure 21-2 ? slow rise/fall time causing glitches at the output of an input buffer board-level input input to core time board-level input input to core logic figure 21-3 ? shielding scheme sso bus shielding quiet i/o proasic3/e sso and pi n placement guidelines 21-4 v1.0 the board alongside the sso bus fo r the whole length of the sso traces and on the same board layer. these shielding traces should be connected to board ground at both ends of their length. shielding using other pins the type of shielding pins is no t restricted to gnd or virtual ground s. the shielding pins can also be v cci , v ccii , virtual v cci , unused i/os, or used i/os that are not sensitive to sso effects (e.g., outputs driving leds). how to use this document the rest of this document is divided based on th ree different sso effects: on outputs, on inputs, and on clock conditioning circuits (cccs). each section includes tables that identify the recommended maximum number of ssos and the requ ired shielding if the number of ssos exceeds the recommendation. the tables ar e categorized by device/package type (e.g., a3p600-fg484) and i/o configuration of the sso bus (i.e., drive streng th and slew rate). if the desired de vice/package combination cannot be found in the tables, choose the sso recommendation for the closest package type and the next smaller die size. the fo llowing example describes two scenarios in which the sso recommendation for anothe r device/package can be used for a member of the proasic3/e family: 1. sso guidelines for a3p250-pq208 can be used when designing for a3p400-pq208. 2. sso guidelines for a3pe600-fg484 can be used when designing for a3pe1500-fg676. you should study this en tire document, consider the desired device/pac kage combination, define the worst-case sso scenario, and us e the sso guidelines or shield ing recommendations described in the tables. at the end of each section, guidelines are given on how to mitigate the effects of ssos. note that the data presented in this document is collected at nominal operating conditions (1.5 v core voltage and room temperature). cmos transisto rs switch faster when cold, and therefore the edge rates become faster, so sso effects are usually worse at lower temperatures. at the end of this document, some general boar d-level design guidelines are included. actel recommends that you follow these gu idelines when designing boards. sso effects on outputs this section describes the sso effects on other outputs. as stated in the "shielding from ssos" section on page 21-3 , in proasic3 and proasic3e devices, th e effects of ssos on quiet outputs are categorized by ground bounce, v cci bounce, and push-out. the following sections give the characteristics of sso effects on outputs and provide guidelines on how to mitigate these effects. ground and v cci bounce the most widely known effects of ssos are ground and v cci bounce. this section characterizes proasic3/e ground and v cci bounce in the presence of ssos. since outputs with higher drive strength or faster slew rate source/sink higher current at the time of switching, ssos are more disruptive when they are configured at higher drive strength and high slew rate. table 21-1 on page 21-5 lists the number of ssos causing specified levels of ground and v cci bounce for various device, package, and sso bus configurations. a disr uptive ground bounce is one with a 1.25 v peak and 1 ns width?enough to trigger a high-speed input to change its value from zero to one. similarly, a disruptive v cci bounce causes oscillations on the quiet output (driving high) with a magnitude of 2 v and width of 1 n s. these values are chosen based on actel bench experiments using typical cmos input sensitivity. proasic3/e sso and pi n placement guidelines v1.0 21-5 output push-out as described in the "sso effect on output delay (push-out)" section on page 21-2 , if an output is surrounded by ssos, the propagation delay of that output may be increased due to the noise on ground or v cci . figure 21-4 shows a simple diagram of the push -out effect. as shown, the push-out effect occurs only if the affected output toggles at the same time as the sso bus. if the outputs surrounded by the sso bus are not switching simultaneously (with in 200 ps of each other) with the ssos, the outputs are not affected by the push-out phenomenon. table 21-1 ? number of ssos causing specified ground and v cci bounce device drive strength (ma) slew rate ssos causing gnd bounce ssos causing v cci bounce a3p250-pq208 24 high 4 2 low 4 6 12 high 8 12 low 16 16 a3pe600-pq208 24 high 6 4 low 8 8 12 high 10 12 low 14 16 a3pe600-fg484 24 high 24 10 low 56 16 12 high >64 32 low >64 >64 figure 21-4 ? sso push-out effect switching output sso bus without sso with sso sso bus proasic3/e sso and pi n placement guidelines 21-6 v1.0 table 21-2 lists the increase in output delay fo r various sso widths and configurations. mitigating sso effects on outputs any effort to mitigate the sso effect starts wi th eliminating the ssos themselves. as described in "introduction" on page 21-1 , the ssos should be sp read across the die pads to avoid a large sso bus concentrated in one area of the die. if possible , the clock-to-out timing of output busses should be staggered to reduce the number of ssos in vicinity of sensitive ou tputs. if placement of sensitive outputs close to an sso bus is inevitable, such outputs should be shielded from the bus. the shielding scheme to protect delay-sensitive out puts is similar to the guidelines presented in table 21-3 on page 21-7 . whenever shielding is required, it is recommended to use gnd or virtual ground pins as shielding. however, it is acceptable to use other shielding pins to protect sensitive outputs from ssos. segmenting sso busses into smaller sections he lps mitigate the sso effect. the sso bus can be segmented by inserting spacers among the sso bus pins when placed on the die pads, as shown in figure 21-5 . the spacers can be gnd or virtual ground, v cci or virtual v cci , unused i/o, or used i/os that are not assigned to sensitiv e signals and do not toggle freque ntly or synchronously with the ssos (e.g., signals driving leds). also, as described in table 21-1 on page 21-5 and table 21-2 , fg and bg packages show much better characteristics with respect to sso effects than pq, tq , or vq packages. therefore, for relatively high-speed designs or designs that have a significant number of wide output busses, fg or bg packages are strongly recommended. in addition to the logic design and device pack age type, board-level design is a key parameter in mitigating sso effects. a well-designed pcb, capable of providing clean voltage supplies to the fpga, is less susceptible to no ise and therefore performs better. table 21-2 ? sso push-out effect on an output surrounded by ssos package drive strength (ma) slew rate 5 < ssos < 10 ssos 10 pq208 24 high <1.1 ns <1.8 ns low <600 ps <1.2 ns 12 high <900 ps <1.5 ns low negligible negligible 8 any negligible negligible fg484 any any negligible negligible notes: 1. table data obtained when output load is 30 pf. 2. larger output load increases the push-out effe ct. as an example, incr easing the output load from 30 pf to 50 pf increases the push-out effect by 40%. figure 21-5 ? example of consolidated and segmented sso bus sso bus consolidated quiet i/o sso bus segmented quiet i/o gnd / virtual gnd unused/used i/o proasic3/e sso and pi n placement guidelines v1.0 21-7 board-level timing analysis with push-out since the push-out effect changes the clock-to-out timing of the signal surrounded by ssos, designers should take care when performing board- level timing analysis for such outputs. the following are the actel recommendat ions for calculating the clock-to -out timing of signals affected by push-out phenomena: ? for board-level setup time calculations: clock-to-out = worst-case cl ock-to-out reported by smarttime + push-out delay ? for board-level hold time calculations: clock-to-out = best-case clock- to-out reported by smarttime sso effects on inputs as described in the "virtual v cci " section on page 21-3 , if a quiet input is surrounded by ssos, the logic driven by that input may experience a glit ch when the sso bus is switching. in proasic3/e devices in fg or bg packages, the inputs are not affected by an sso bus. however, in pq, tq, and vq packages, due to larger lead inductance, the ssos may affect the inputs as de scribed in the "sso effect on inputs" section on page 21-2 and the "sso effect on mini mum input slew rate (input maximum rise/fall time)" section on page 21-2 . table 21-3 describes the input shielding required for various sso sizes with different i/o configurations. for example, in a pq208 package, if a sensitive input (e.g., asynchrono us reset) is surrounded by an sso bus configured with 16 ma drive strength and low slew rate, two shielding pins are required on each side of the sensitive input to prevent any logic glitch on the reset line during transition of the sso bus. in pq, tq, and vq packages, the sensitive inputs may be affected by ssos as described in the "sso effect on minimum inpu t slew rate (input maximum rise /fall time)" section on page 21-2 . if the edge-sensitive inputs surrounded by an sso bus rise or fall at the same time as an sso transition, the maximum rise and fall times of those inputs sh ould be less than 3 ns to avoid any glitches, as described the "sso effect on mini mum input slew rate (input maxi mum rise/fall time)" section on page 21-2 . mitigating sso effects on inputs as illustrated in table 21-1 on page 21-5 , in pq, tq, and vq packages, inputs may be affected by a surrounding sso bus, depending on the configuration and number of the ssos. fg and bg packages show much better sso characteristics due to smaller lead inductance. therefore, designers are encouraged to use these packages in designs that have ssos and are sensitive to table 21-3 ? shielding requirement prot ecting inputs from sso 1 package drive strength (ma) slew rate shielding required 2 for 4 < sso < 8 shielding required 2 for sso > 8 pq208 24 high 2 3 low 2 2 16 high 2 3 low 2 2 12 high 0 1 low 0 0 8any 0 0 fg484 any any 0 0 notes: 1. measurements were performed with a 3.3 v swing on the sso bus. 2. shielding pins required on the side of the sensitive input adjacent to the sso bus. proasic3/e sso and pi n placement guidelines 21-8 v1.0 noise. it is also recommended that designers use the general guidelines described in "introduction" on page 21-1 to eliminate sso conditions that may cause system signal integrity problems. in addition, experiments at actel show that in proasic3/e devices, inpu ts configured with the schmitt trigger option are slightly more tolerant to the noise in duced by an sso bus. therefore, actel recommends that designers select the schmitt trigger option for critic al inputs surrounded by ssos whenever possible. whenever shielding is required by table 21-3 on page 21-7 , it is recommended to use gnd or virtual ground pins as shielding (described in the "shielding using gnd or virtual ground pins" section on page 21-3 ); however, it is acceptable to use ot her shielding pins (as described in the "shielding using other pins" section on page 21-4 ) to protect the sensitive inputs from ssos. mitigating sso effects on clock conditioning circuits in general, analog circuitr y is more sensitive to noise than di gital signals. as described in the "shielding from ssos" section on page 21-3 , any sensitive signal surrounded by an sso bus is affected by the noise induced by sso activity. therefore, if th e analog power supply of the proasic3/e pll (i.e., the v ccplx pin) is surrounded by ssos, the noise induced by the ssos in the analog supply will cause an increas e in the pll output jitter. experi ments at actel show that if the analog supply pin of the pll is surrounded by two or more ssos, the output jitter of the corresponding pll will be increased beyond the ji tter specification in the proasic3/e datasheet. therefore, if plls are used in pr oasic3/e devices, the analog supplies of the plls used should be shielded from any ssos by avoiding the placement of ssos in neighboring i/o banks. refer to figure 21-6 , figure 21-7 on page 21-9 , and figure 21-8 on page 21-9 for more information about the i/o bank neighboring the pll. note: the a3p030 device does not support a pll (v complf and v ccplf pins). figure 21-6 ? naming conventions of proasic3 devices with two i/o banks ccc/pll "f" a3p030 a3p060 a3p125 bank 1 bank 1 bank 0 bank 0 bank 1 bank 0 proasic3/e sso and pi n placement guidelines v1.0 21-9 figure 21-7 ? naming conventions of proasic3 devices with four i/o banks figure 21-8 ? user i/o naming conventions of proasic3e devices a3p250 a3p400 a3p600 a3p1000 bank 3 bank 3 bank 1 bank 1 bank 2 bank 0 ccc/pll "f" a3pe600 ccc/ pll ?f? ccc/ pll ?c? ccc/ pll ?d? ccc/ pll ?b? ccc/ pll ?a? ccc/ pll ?e? bank 0 bank 1 bank 5 bank 4 jtag bank 3 bank 2 jtag bank 6 bank 7 a3pe600 ccc/ pll ?f? ccc/ pll ?c? ccc/ pll ?d? ccc/ pll ?b? ccc/ pll ?a? ccc/ pll ?e? bank 0 bank 1 bank 5 bank 4 jtag bank 3 bank 2 jtag bank 6 bank 7 a3pe600 a3pe1500 a3pe3000 ccc/ pll 'a' bank 0 bank 1 bank 5 bank 4 jtag bank 3 bank 2 jtag bank 6 bank 7 ccc/ pll 'f' ccc/ pll 'e' ccc/ pll 'd' ccc/ pll 'c' ccc/ pll 'b' proasic3/e sso and pi n placement guidelines 21-10 v1.0 conclusion as digital designs get faster and larger, ssos and their effects become a more critical part of system signal integrity analysis . this application note provides data characterizing and predicting the effects of ssos on sensitive inputs and outp uts in proasic3/e fpgas. sso effects should be mitigated to ensure the functionality of the de sign; this application note provides specific techniques fo r doing so. sso mitigation techniques should be conducted in parallel with chip-level and board-level design, as they play important roles in providing a clean digital system. fo r board-level design guidelines, refer to the board-level considerations application note. due to the nature of ssos, fg and bg packages are more tolerant to sso effects than pq or tq packages. therefore, for high-speed designs or designs with large numbers of ssos, fg and bg packages are strongly recommended. related documents application notes simultaneous switching noise http://www.actel.com/documents/ssn_an.pdf board-level considerations http://www.actel.com/documents/boardlevelcons_an.pdf part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-022-0 revised january 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. previous version changes in current version (v1.0) page 51900140-1/6.05 figure 21-6 naming conventions of proasic3 devices with two i/o banks , figure 21-7 naming conventions of proasic3 devices with four i/o banks , and figure 21-8 user i/o naming conventions of proasic3e devices were updated. 21-8 ? 21-9 v1.0 22-1 application note ac312 22 ? metastability characterization report for actel flash fpgas introduction whenever asynchro nous data is registered by a clocked flip-flop, there is a probability of setup or hold time violation on that flip-flop. in applicat ions such as synchronization or data recovery, due to the asynchronous nature of the data input to the flip-flops, the data transition time is unpredictable with respect to the ac tive edge of the clock. the susceptibility of a circuit to reaching this metastable state can be described using a prob abilistic equation. setup or hold violations cause the output of the flip-flop to enter a symmetrically balanced tr ansient state, called a metastable state. the metastable state is manifested in a bista ble device by the outputs glitching, going into an undefined state somewhere be tween 1 and 0, oscillating, or by the output transition being delayed for an indeterminable time. once the f lip-flop has entered the metastable state, the probability that it will still be metastable later has been shown to be an exponentially decreasing function of time. because of this property, a desi gner should simply wait for additional time after the specified propagation delay before sampling th e flip-flop output so th at the designer can be assured that the likelihood of me tastable failure is remote enough to be tolerable. the additional time of waiting becomes shorter, even though sti ll more than zero, as the technology improves and semiconductor devices reach higher ranges of speed. this document discusses a description of me tastability equa tions followed by metastability characterization of proasic, ? proasic plus ? , proasic3, and proasic3e fp gas. this application note also provides examples on the usage of metastability equations. theory of metastability in general, the mean time between failures (mtbf) should be defined statically. figure 22-1 on page 22-2 depicts a simple circuit, used to synchronize asynchronous data with the system clock. eq 22-1 shows the relation between mtbf and the cl ock-to-out settling time of a flip-flop: mtbf = e (ts / ) / (t o f d f c ) eq 22-1 t s = t co + t met eq 22-2 in eq 22-1 and eq 22-2 : t s = total flip-flop output settling time t co = flip-flop clock-to-out delay t met = additional settling time ad ded to the normal clock-to-out delay of the flip-flop before sampling the output of the flip-flop t = metastable decay constant. t 0 = metastability aperture at t co = 0 ns (this parameter represents the likelihood that a flip- flop will enter a metastable state) f d = data transition rate (twice the data freque ncy for periodic signals, since there are two transitions per period) f c = clock frequency metastability characterization report for actel flash fpgas 22-2 v1.0 as mentioned earlier, the aperture represents the likelihood of the flip-f lop entering a metastable state. the aperture is defined as a time window within the clock period. data transitioning inside the aperture will cause the flip-flop outp ut settling time to be greater than t co + t met . the aperture is calculated by recording the nu mber of instances in which the se ttling time exceed s the specified t co + t met . the metastability aperture decreases expo nentially as the allowed settling time (t co + t met ) increases: aperture = t o e ?(tco + tmet)/ eq 22-3 if the data transition occurs wi thin the aperture, the flip-flop will stay metastable beyond the allocated settling time (t co + t met ); and therefore, the second f lip-flop would register invalid data ( figure 22-1 ). the probability of an asyn chronous data transition is uniformly distributed over the clock period. therefore, the prob ability of a single data transi tion occurring in the metastable aperture is calculated by eq 22-4 : p = aperture / t c eq 22-4 where t c is the clock period. in each clock cycle, the failure oc curs if the data transition time is within the aperture. therefore, the number of failures in one clock cycle can be derived by eq 22-5 : n e = n p = n (aperture / t c ) eq 22-5 where n e represents the number of errors per clock cycl e, and n is the number of data transitions per clock period (f d / f c ). the number of clock cycles in the operation time (n ) is the total time divided by the clock period, or n = t operation / t c eq 22-6 combining eq 22-5 and eq 22-6 results in the total number of failures per operation time (n e ): n e = n n e = (t operation / t c ) (f d / f c ) (aperture / t c ) eq 22-7 since t c = 1 / f c , eq 22-7 can be simplified to n e = t operation f d f c aperture eq 22-8 mtbf is defined as the operation time divided by the number of failures, or mtbf = 1/ (f d f c aperture) = 1/ (t 0 e ?(tco + tmet) / f d f c ) eq 22-9 figure 22-1 ? example of synchronization circuit clk dq clk dq f d f c t co async data sync data metastability characterization report for actel flash fpgas v1.0 22-3 fpga metastability characterization like other fgpa manufacturers, to absorb the fixed value the of e tco term, actel simplifies eq 22-9 on page 22-2 to the following form: mtbf = e c2 * tmet / (c1 f d f c ) eq 22-10 where c2 is a constant inversely proportional to the metastability decay constant, and c1 is the proportionality constant, whic h is similar to aperture. the fpga metastability characterizati on is a series of tests conduc ted to identify the value of c1 and c2. there are several envi ronmental and test condition factors that influence the characterization. these factors include but are not li mited to the rise time of data and clock signals, input voltage levels, and operat ing voltage and temperature. mo reover, increased system noise due to switching of both internal nodes and i/os can influence the metastability results. therefore, it is essential to provide a su itable environment for testing. test design description figure 22-2 shows a schematic of the test circuit used to characterize the metastability in actel devices. the propagation delay, operating under specified setup an d hold time, is measured from the output of flip-flop dff#1 to the input of flip-flop dff#3. this value is denoted by eq 22-11 : t min = t cof (dff#1) + t delay + t su (dff#3) eq 22-11 where t delay is the propagation delay from output of dff#1 to input of dff#3, t cof is the clock-to- out delay of dff#3, and t su represents the setup time requirement of dff#3. t min corresponds to the t co in eq 22-9 on page 22-2 and is the reference time to wh ich the additional settling time, t met , is added for characterization of metastability. dff#2 is clocked on the same edge as dff#1. co nversely, dff#3 must resolve the signal driven from the metastable dff#1 before the falling cloc k edge. as can be seen in the design in figure 22-2 , figure 22-2 ? test circuit observation node wired to i/os dff#3 dff#2 a b y metastable catching dff dff#1 d clk q d clk q d clk q metastability event counter (20 bits) enable 30-bit (billion cycle) measurement timer asynchronous data clock reset inverting delay buff a y metastability characterization report for actel flash fpgas 22-4 v1.0 t min + t met is the difference between the rising and falli ng edge of the clock. therefore, it can be easily set or measured by adjusti ng the duty cycle of the clock signal. a detectable metastable event occurs when dff#2 and dff#3 are in the sa me state. in the expected operation, dff#2 and dff#3 are in opposite states due to the invert er in the dff#3 input data path. the xnor gate allows the event counter to record these metastable events. after a billion clock cycles, the counter is read and the mtbf is calculated. in this test, t min was resolved to within 0.01% of the du ty cycle at 10 mhz. this translates to an error of 10 ps. the other test setup parameters were as follows: ? clock and data inputs were driven from in dependent pulse generato rs (<1 ns rise time). ? clock input levels were from 0 v to 2.5 v. thes e levels were required due to the impedance matching of actel's test fixture. data input levels were 0 v to 3.3 v. ? fpga power supplies for all tests were at v ddp = 3.3 v and v dd = 2.5 v. metastability measurement results eq 22-10 on page 22-3 can be reformed into eq 22-12 : ln(mtbf) = c2 t met ? ln(c1 f d f c ) eq 22-12 the plot of eq 22-12 is a linear relationship between ln(mtbf) and t met , where c2 is the slope of the line. figure 22-3 shows the plot of eq 22-12 for actel proasic and proasic plus fpga families. c1 and c2 can be calculated from any two data points. figure 22-3 ? metastability comparison of actel fpga families 6 4 2 0 -2 -4 -6 -8 -10 -12 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 proasic (0.22 m) proasic (0.25 m) ln(mtbf) t met plus metastability characterization report for actel flash fpgas v1.0 22-5 the metastability theory indicate s that c1 and c2 are independ ent of the test clock and data frequency. the test results concur within experimental tolerances. the calculations of c1 and c2 are given in table 22-1 . examples of metastability coefficients usage metastability shows a statistical nature, and desi gners should allow enough additional time (t met ) that the likelihood of metastable failure is re mote enough to be to lerable by the design specification. for example, consider that the simple circuit in figure 22-1 on page 22-2 is implemented in a proasic plus device to synchronize an asynchronous data input to the fpga. the following parameters are given to designer by either design specification or post-layout timing analysis: t co = 10 ns, corresponding to a clock frequency of 100 mhz asynchronous data transition rate = 12.5 mhz tolerable mtbf = 1 year if the designer does not allo w additional sampling time (t met = 0 ns) and run the clock at the rate of 100 mhz, eq 22-12 on page 22-4 will result in mtbf = 51.2 s. this means that a metastability error will occur at the ou tput of the second flip-flop every 51 .2 s. this value exceeds the required mtbf of one year indicated in the design specific ation. to meet this requirement, the designer needs to allow additional t met in the sampling time, which can be calculated as follows: 1 year = 365 24 3,600 = 31,536,000 seconds ln 31,536,000 = 9.148e+09 t met ? ln (1.56e?11 100e6 12.5e6) t met = 2.96 ns therefore, an additional 3 ns sampling time will fulfill the required mtbf. part number and revision date this document was previously published as an application note describing features and functions of the device, and as such has now been inco rporated into the device handbook format. no technical changes have be en made to the content. part number 51700094-023-0 revised january 2008 list of changes the following table lists critical changes that we re made in the current version of the chapter. table 22-1 ? metastability coefficients for actel flash fpgas f c = 10 mhz device family c 1 (s) c 2 (s) proasic 9.95e?11 1.03e+10 proasic plus 1.56e?11 9.148e+09 proasic3/e core registers 9.11e?12 1.57e+10 proasic3/e i/o registers 2.25e?12 1.91e+10 previous version changes in current version (v1.0) page 5190062-1/5.04 table 22-1 metastability coefficients for actel flash fpgas was updated to include proasic3 /e information. 22-5 5190062-0 this document was updated to pr ovide a detailed description of the calculations being made. 51700097-004-3/ actel corporation 2061 stierlin court mountain view, ca 94043-4655 usa phone 650.318.4200 fax 650.318.4600 actel europe ltd. river court,meadows business park station approach, blackwater camberley surrey gu17 9ab united kingdom phone +44 (0) 1276 609 300 fax +44 (0) 1276 607 540 actel japan exos ebisu buillding 4f 1-24-14 ebisu shibuya-ku tokyo 150 japan phone +81.03.3445.7671 fax +81.03.3445.7668 http://jp.actel.com actel hong kong room 2107, china resources building 26 harbour road wanchai, hong kong phone +852 2185 6460 fax +852 2185 6488 www.actel.com.cn www.actel.com actel and the actel logo are registered trademarks of actel corporation. all other trademarks are the property of their owners. 3.08 |
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